arch/ppc/kernel/gt64260_common.c

   1 /*
   2  * arch/ppc/kernel/gt64260_common.c
   3  *
   4  * Common routines for the Marvell/Galileo GT64260 (Discovery) host bridge,
   5  * interrupt controller, memory controller, serial controller, enet controller,
   6  * etc.
   7  *
   8  * Author: Mark A. Greer <mgreer@mvista.com>
   9  *
  10  * 2001-2002 (c) MontaVista, Software, Inc.  This file is licensed under
  11  * the terms of the GNU General Public License version 2.1.  This program
  12  * is licensed "as is" without any warranty of any kind, whether express
  13  * or implied.
  14  */
  15
  16 /*
  17  * The GT64260 port is the result of hard work from many people from
  18  * many companies.  In particular, employees of Marvell/Galileo, Mission
  19  * Critical Linux, Xyterra, Zuma Networks, and MontaVista Software were
  20  * heavily involved.
  21  */
  22
  23 /*
  24  * At last count, the 64260-B-0 has 65 errata and 24 restrictions.  The odds of
  25  * you getting it to work well, under stress, for a long period of time are
  26  * low.  If nothing else, you will likely run into an interrupt controller
  27  * bug.
  28  *
  29  * The newer 64260A-B-0 is much improved but has its own problems.
  30  * Dave Wilhardt <dwilhardt@zyterra.com> has discovered that you must set
  31  * up your PCI snoop regions to be prefetchable with 4-word bursts AND set the
  32  * "Memory Write and Invalidate bit" (bit 4) in the cmd reg of each PCI device
  33  * before coherency works between PCI and other devices.  Many thanks to Dave.
  34  *
  35  * There is now a 64260B-B-0 but I have not yet had one to test so I don't
  36  * know if it will work--MAG.
  37  */
  38 #include <linux/kernel.h>
  39 #include <linux/init.h>
  40 #include <linux/pci.h>
  41 #include <linux/slab.h>
  42 #include <linux/module.h>
  43
  44 #include <asm/byteorder.h>
  45 #include <asm/io.h>
  46 #include <asm/irq.h>
  47 #include <asm/uaccess.h>
  48 #include <asm/machdep.h>
  49 #include <asm/pci-bridge.h>
  50 #include <asm/gt64260.h>
  51 #include <asm/delay.h>
  52
  53
  54 u32     gt64260_base;
  55 u32     gt64260_revision; /* Revision of the chip */
  56 u8      gt64260_pci_exclude_bridge = TRUE;
  57
  58 spinlock_t gt64260_lock = SPIN_LOCK_UNLOCKED;
  59 spinlock_t gt64260_rmw_lock = SPIN_LOCK_UNLOCKED;
  60
  61 /*
  62  *****************************************************************************
  63  *
  64  *      Bridge Initialization Routines
  65  *
  66  *****************************************************************************
  67  */
  68 static void gt64260_check_errata(struct pci_controller *hose_a,
  69                                  struct pci_controller *hose_b);
  70 static void __init gt64260_setup_mem_windows(gt64260_bridge_info_t *info);
  71
  72 /*
  73  * Typical '_find_bridges()' routine for boards with a GT64260 bridge.
  74  *
  75  * Assumes that gt64260_base the virtual base address of the bridge's registers.
  76  */
  77 int __init
  78 gt64260_find_bridges(gt64260_bridge_info_t *info,
  79         int ((*map_irq)(struct pci_dev *, unsigned char, unsigned char)))
  80 {
  81         struct pci_controller           *hose_a, *hose_b;
  82         u32                             io_base_a, io_base_b, val;
  83         int                             rc = 0;
  84
  85
  86         hose_a = info->hose_a;
  87         hose_b = info->hose_b;
  88
  89         if ((hose_a == (struct pci_controller *)NULL) &&
  90             (hose_b == (struct pci_controller *)NULL)) {
  91
  92                 if (ppc_md.progress)
  93                         ppc_md.progress("gt64260_find_bridges: no hoses", 0x0);
  94
  95                 printk("gt64260_find_bridges: No PCI hoses\n");
  96                 return -1;
  97         }
  98
  99         /*
 100          * Map in PCI I/O region.
 101          * ioremap() typically grows down.  Try to put io_base_a lower
 102          * than io_base_b so allocate hose_b's PCI io space first.
 103          */
 104         if (hose_b != (struct pci_controller *)NULL) {
 105                 io_base_b = (u32)ioremap(info->pci_1_io_start_proc,
 106                                         info->pci_1_io_size);
 107                 isa_io_base = io_base_b;
 108         }
 109
 110         /*
 111          * We need to scan the PCI bus before doing the bridge init because
 112          * we need the buses enumerated.  This is okay because the only regs
 113          * that are accessed during the scanning are the PCI config addr/data
 114          * pair on the bridge and config registers on PCI devices (and the
 115          * bridge's regs on the PCI bus will be excluded).
 116          */
 117
 118         /*
 119          * Set up the PCI resources/hose structure and the scan the PCI buses
 120          * under the first PCI hose.
 121          */
 122         if (hose_a != (struct pci_controller *)NULL) {
 123                 io_base_a = (u32)ioremap(info->pci_0_io_start_proc,
 124                                         info->pci_0_io_size);
 125                 isa_io_base = io_base_a;
 126
 127                 setup_indirect_pci(hose_a,
 128                            info->phys_base_addr + GT64260_PCI_0_CONFIG_ADDR,
 129                            info->phys_base_addr + GT64260_PCI_0_CONFIG_DATA);
 130
 131                 pci_init_resource(&hose_a->io_resource,
 132                           io_base_a - isa_io_base,
 133                           io_base_a - isa_io_base + info->pci_0_io_size - 1,
 134                           IORESOURCE_IO,
 135                           "host bridge PCI bus 0");
 136                 hose_a->io_space.start = info->pci_0_io_start_pci;
 137                 hose_a->io_space.end   = info->pci_0_io_start_pci +
 138                                                 info->pci_0_io_size - 1;
 139                 hose_a->io_base_virt = (void *)isa_io_base;
 140
 141                 pci_init_resource(&hose_a->mem_resources[0],
 142                           info->pci_0_mem_start_proc,
 143                           info->pci_0_mem_start_proc + info->pci_0_mem_size - 1,
 144                           IORESOURCE_MEM,
 145                           "host bridge PCI bus 0");
 146                 hose_a->mem_space.start = info->pci_0_mem_start_pci_lo;
 147                 hose_a->mem_space.end   = info->pci_0_mem_start_pci_lo +
 148                                                 info->pci_0_mem_size - 1;
 149                 hose_a->pci_mem_offset = (info->pci_0_mem_start_proc -
 150                                                 info->pci_0_mem_start_pci_lo);
 151                 /* Can't walk PCI bus until bridge is initialized */
 152         }
 153
 154         /* Now scan the second PCI hose */
 155         if (hose_b != (struct pci_controller *)NULL) {
 156                 setup_indirect_pci(hose_b,
 157                            info->phys_base_addr + GT64260_PCI_1_CONFIG_ADDR,
 158                            info->phys_base_addr + GT64260_PCI_1_CONFIG_DATA);
 159
 160                 pci_init_resource(&hose_b->io_resource,
 161                           io_base_b - isa_io_base,
 162                           io_base_b - isa_io_base + info->pci_1_io_size - 1,
 163                           IORESOURCE_IO,
 164                           "host bridge PCI bus 1");
 165                 hose_b->io_space.start = info->pci_1_io_start_pci;
 166                 hose_b->io_space.end   = info->pci_1_io_start_pci +
 167                                                 info->pci_1_io_size - 1;
 168                 hose_b->io_base_virt = (void *)isa_io_base;
 169
 170                 pci_init_resource(&hose_b->mem_resources[0],
 171                           info->pci_1_mem_start_proc,
 172                           info->pci_1_mem_start_proc + info->pci_1_mem_size - 1,
 173                           IORESOURCE_MEM,
 174                           "host bridge PCI bus 1");
 175                 hose_b->mem_space.start = info->pci_1_mem_start_pci_lo;
 176                 hose_b->mem_space.end   = info->pci_1_mem_start_pci_lo +
 177                                                 info->pci_1_mem_size - 1;
 178                 hose_b->pci_mem_offset = (info->pci_1_mem_start_proc -
 179                                                 info->pci_1_mem_start_pci_lo);
 180                 /* Can't walk PCI bus until bridge is initialized */
 181         }
 182
 183         /* Now we can initialize the bridge for real */
 184         if ((rc = gt64260_bridge_init(info)) != 0) {
 185                 if (hose_a != (struct pci_controller *)NULL) {
 186                         iounmap((void *)hose_a->cfg_addr);
 187                         iounmap((void *)hose_a->cfg_data);
 188                 }
 189
 190                 if (hose_b != (struct pci_controller *)NULL) {
 191                         iounmap((void *)hose_b->cfg_addr);
 192                         iounmap((void *)hose_b->cfg_data);
 193                 }
 194
 195                 return -1;
 196         }
 197
 198         pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */
 199
 200         ppc_md.pci_exclude_device = gt64260_pci_exclude_device;
 201         ppc_md.pci_swizzle        = common_swizzle;
 202         ppc_md.pci_map_irq        = map_irq;
 203
 204         /* Now that the bridge is set up, its safe to scan the PCI buses */
 205         if (hose_a != (struct pci_controller *)NULL) {
 206                 hose_a->first_busno = 0;
 207                 hose_a->last_busno  = 0xff;
 208
 209                 hose_a->last_busno = pciauto_bus_scan(hose_a,
 210                                                         hose_a->first_busno);
 211         }
 212
 213         if (hose_b != (struct pci_controller *)NULL) {
 214                 hose_b->first_busno = 0;
 215                 hose_b->last_busno  = 0xff;
 216
 217                 if (hose_a != (struct pci_controller *)NULL) {
 218                         hose_b->first_busno = hose_a->last_busno + 1;
 219
 220                         /* Set bus number for second hose */
 221                         val = gt_read(GT64260_PCI_1_P2P_CONFIG);
 222                         val &= 0xff00ffff;
 223                         val |= ((hose_b->first_busno & 0xff) << 16);
 224                         gt_write(GT64260_PCI_1_P2P_CONFIG, val);
 225                         (void)gt_read(GT64260_PCI_1_P2P_CONFIG);/* Flush FIFO */
 226                 }
 227
 228                 hose_b->last_busno = pciauto_bus_scan(hose_b,
 229                                                         hose_b->first_busno);
 230         }
 231
 232         /*
 233          * Set up the CPU memory-related windows and the PCI BARs based on how
 234          * the CPU SCS windows are set up.  Although, not clearly documented,
 235          * testing has shown that you need the PCI SCS windows to match the
 236          * CPU SCS windows.
 237          */
 238         gt64260_setup_mem_windows(info);
 239
 240         /* Check for errata and adjust accordingly */
 241         gt64260_check_errata(info->hose_a, info->hose_b);
 242
 243         return rc;
 244 } /* gt64260_find_bridges() */
 245
 246 /*
 247  * gt64260_bridge_init()
 248  *
 249  * Perform bridge initialization for a "typical" setup for a PPC system.
 250  */
 251 int __init
 252 gt64260_bridge_init(gt64260_bridge_info_t *info)
 253 {
 254         u16     u16_val;
 255         u32     u32_val;
 256         u8      save_exclude;
 257
 258         /* Bit 12 MUST be 0. */
 259         gt_clr_bits(GT64260_CPU_CONFIG, (1<<12));
 260
 261         /*
 262          * Turn off timer/counters.  Not turning off watchdog timer because
 263          * can't read its reg on the 64260A so don't know if we'll be enabling
 264          * or disabling.
 265          */
 266         gt_clr_bits(GT64260_TIMR_CNTR_0_3_CNTL,
 267                         ((1<<0) | (1<<8) | (1<<16) | (1<<24)));
 268         gt_clr_bits(GT64260_TIMR_CNTR_4_7_CNTL,
 269                         ((1<<0) | (1<<8) | (1<<16) | (1<<24)));
 270
 271         /*
 272          * Shut down CPU windows and PCI BAR's so there aren't any conflicts
 273          * with the new windows we're about to set up.
 274          *
 275          * Note: Can't disable CPU SCS, snoop, and protection windows because
 276          * we're [probably] running out of one of those windows.
 277          */
 278         gt64260_cpu_disable_windows();
 279         gt64260_pci_bar_enable(0, 0); /* Disable BARs on PCI side of bridge */
 280         gt64260_pci_bar_enable(1, 0);
 281
 282         /*
 283          * Set up various parts of the bridge including CPU->PCI windows.
 284          * Depending on the board, there may be only one hose that needs to
 285          * be set up.
 286          */
 287         if (info->hose_a != (struct pci_controller *)NULL) {
 288                 save_exclude = gt64260_pci_exclude_bridge;
 289                 gt64260_pci_exclude_bridge = FALSE;
 290
 291                 /* Set class code to indicate host bridge */
 292                 early_read_config_dword(info->hose_a,
 293                                         0,
 294                                         PCI_DEVFN(0,0),
 295                                         PCI_CLASS_REVISION,
 296                                         &u32_val);
 297                 u32_val &= 0x000000ff;
 298                 gt64260_revision = u32_val;     /* a 64260 or 64260A? */
 299                 u32_val |= (PCI_CLASS_BRIDGE_HOST << 16);
 300                 early_write_config_dword(info->hose_a,
 301                                          0,
 302                                          PCI_DEVFN(0,0),
 303                                          PCI_CLASS_REVISION,
 304                                          u32_val);
 305                 /* Enable 64260 to be PCI master & respond to PCI MEM cycles */
 306                 early_read_config_word(info->hose_a,
 307                                        0,
 308                                        PCI_DEVFN(0,0),
 309                                        PCI_COMMAND,
 310                                        &u16_val);
 311                 u16_val |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 312                 early_write_config_word(info->hose_a,
 313                                         0,
 314                                         PCI_DEVFN(0,0),
 315                                         PCI_COMMAND,
 316                                         u16_val);
 317
 318                 /* Set latency timer, cache line size, clear BIST */
 319                 u32_val = (info->pci_0_latency<<8) | (L1_CACHE_LINE_SIZE>>2);
 320                 early_write_config_dword(info->hose_a,
 321                                          0,
 322                                          PCI_DEVFN(0,0),
 323                                          PCI_CACHE_LINE_SIZE,
 324                                          u32_val);
 325
 326                 gt64260_pci_exclude_bridge = save_exclude;
 327
 328                 /* Set windows from CPU to PCI I/O and MEM space */
 329                 gt64260_cpu_set_pci_io_window(0,
 330                                               info->pci_0_io_start_proc,
 331                                               info->pci_0_io_start_pci,
 332                                               info->pci_0_io_size,
 333                                               info->pci_0_io_swap);
 334
 335                 gt64260_cpu_set_pci_mem_window(0,
 336                                                0,
 337                                                info->pci_0_mem_start_proc,
 338                                                info->pci_0_mem_start_pci_hi,
 339                                                info->pci_0_mem_start_pci_lo,
 340                                                info->pci_0_mem_size,
 341                                                info->pci_0_mem_swap);
 342         }
 343
 344         if (info->hose_b != (struct pci_controller *)NULL) {
 345                 save_exclude = gt64260_pci_exclude_bridge;
 346                 gt64260_pci_exclude_bridge = FALSE;
 347
 348                 /* Set class code to indicate host bridge */
 349                 early_read_config_dword(info->hose_b,
 350                                         0,
 351                                         PCI_DEVFN(0,0),
 352                                         PCI_CLASS_REVISION,
 353                                         &u32_val);
 354                 u32_val &= 0x000000ff;
 355                 gt64260_revision = u32_val;     /* a 64260 or 64260A? */
 356                 u32_val |= (PCI_CLASS_BRIDGE_HOST << 16);
 357                 early_write_config_dword(info->hose_b,
 358                                          0,
 359                                          PCI_DEVFN(0,0),
 360                                          PCI_CLASS_REVISION,
 361                                          u32_val);
 362
 363                 /* Enable 64260 to be PCI master & respond to PCI MEM cycles */
 364                 early_read_config_word(info->hose_b,
 365                                        0,
 366                                        PCI_DEVFN(0,0),
 367                                        PCI_COMMAND,
 368                                        &u16_val);
 369                 u16_val |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 370                 early_write_config_word(info->hose_b,
 371                                         0,
 372                                         PCI_DEVFN(0,0),
 373                                         PCI_COMMAND,
 374                                         u16_val);
 375
 376                 /* Set latency timer, cache line size, clear BIST */
 377                 u32_val = (info->pci_1_latency<<8) | (L1_CACHE_LINE_SIZE>>2);
 378                 early_write_config_dword(info->hose_b,
 379                                          0,
 380                                          PCI_DEVFN(0,0),
 381                                          PCI_CACHE_LINE_SIZE,
 382                                          u32_val);
 383
 384                 gt64260_pci_exclude_bridge = save_exclude;
 385
 386                 /* Set windows from CPU to PCI I/O and MEM space */
 387                 gt64260_cpu_set_pci_io_window(1,
 388                                               info->pci_1_io_start_proc,
 389                                               info->pci_1_io_start_pci,
 390                                               info->pci_1_io_size,
 391                                               info->pci_1_io_swap);
 392
 393                 gt64260_cpu_set_pci_mem_window(1,
 394                                                0,
 395                                                info->pci_1_mem_start_proc,
 396                                                info->pci_1_mem_start_pci_hi,
 397                                                info->pci_1_mem_start_pci_lo,
 398                                                info->pci_1_mem_size,
 399                                                info->pci_1_mem_swap);
 400         }
 401
 402         return 0;
 403 } /* gt64260_bridge_init() */
 404
 405 /*
 406  * gt64260_setup_mem_windows()
 407  *
 408  * Set up all the CPU and PCI windows to match how the CPU SCS size windows
 409  * are set up.  Although this doesn't appear to be necessary according to the
 410  * manual, it appears to be necessary from experience with the chip.
 411  *
 412  * This routine is the result of a patch from Uri Lublin <uri@sangate.com>.
 413  */
 414 static void __init
 415 gt64260_setup_mem_windows(gt64260_bridge_info_t *info)
 416 {
 417         u32     low, hi, size, window, enable_bits;
 418         const struct {
 419                 int low,hi;
 420         } scs_offset_table[GT64260_CPU_SCS_DECODE_WINDOWS] = {
 421                 {GT64260_CPU_SCS_DECODE_0_BOT, GT64260_CPU_SCS_DECODE_0_TOP},
 422                 {GT64260_CPU_SCS_DECODE_1_BOT, GT64260_CPU_SCS_DECODE_1_TOP},
 423                 {GT64260_CPU_SCS_DECODE_2_BOT, GT64260_CPU_SCS_DECODE_2_TOP},
 424                 {GT64260_CPU_SCS_DECODE_3_BOT, GT64260_CPU_SCS_DECODE_3_TOP}
 425         };
 426
 427         /*
 428          * Assume that GT64260_CPU_SCS_DECODE_WINDOWS,
 429          * GT64260_CPU_SNOOP_WINDOWS, GT64260_PCI_SCS_WINDOWS, and
 430          * GT64260_PCI_SNOOP_WINDOWS are all the equal.
 431          * Also assume that GT64260_CPU_PROT_WINDOWS >=
 432          * GT64260_CPU_SCS_DECODE_WINDOWS and
 433          * GT64260_PCI_ACC_CNTL_WINDOWS >= GT64260_PCI_SCS_WINDOWS.
 434          */
 435
 436 #define SCS_ADDR(a) (((a) & 0x0fff) << 20)
 437         enable_bits = 0;
 438
 439         for (window=0; window<GT64260_CPU_SCS_DECODE_WINDOWS; window++) {
 440                 low = gt_read(scs_offset_table[window].low);
 441                 hi  = gt_read(scs_offset_table[window].hi);
 442
 443                 low = SCS_ADDR(low);
 444                 hi = SCS_ADDR(hi);
 445
 446                 size = (low <= hi) ? (hi - low + (SCS_ADDR(1))) : 0;
 447                 if (size) {
 448                         enable_bits |= (1 << window);
 449
 450 #ifdef DEBUG
 451                         printk(__FUNCTION__ ": scs window: %d, %x (%x)\n",
 452                                         window, low, size);
 453 #endif
 454                         gt64260_cpu_prot_set_window(window, low, size,
 455                                         info->cpu_prot_options[window]);
 456                         gt64260_cpu_snoop_set_window(window, low, size,
 457                                              info->cpu_snoop_options[window]);
 458
 459                         if (info->hose_a != (struct pci_controller *)NULL) {
 460                                 gt64260_pci_slave_scs_set_window(info->hose_a,
 461                                                 window, low, low, size);
 462                                 gt64260_pci_acc_cntl_set_window(0, window, 0,
 463                                         low, size,
 464                                         info->pci_0_acc_cntl_options[window]);
 465                                 gt64260_pci_snoop_set_window(0, window, 0,
 466                                         low, size,
 467                                         info->pci_0_snoop_options[window]);
 468                         }
 469                         if (info->hose_b != (struct pci_controller *)NULL) {
 470                                 gt64260_pci_slave_scs_set_window(info->hose_b,
 471                                                 window, low, low, size);
 472                                 gt64260_pci_acc_cntl_set_window(1, window, 0,
 473                                         low, size,
 474                                         info->pci_1_acc_cntl_options[window]);
 475                                 gt64260_pci_snoop_set_window(1, window, 0,
 476                                         low, size,
 477                                         info->pci_1_snoop_options[window]);
 478                         }
 479                 }
 480         }
 481
 482         if (info->hose_a != (struct pci_controller *)NULL) {
 483                 gt64260_pci_bar_enable(0, enable_bits);
 484         }
 485
 486         if (info->hose_b != (struct pci_controller *)NULL) {
 487                 gt64260_pci_bar_enable(1, enable_bits);
 488         }
 489 }
 490
 491
 492
 493 /*
 494  * gt64260_check_errata()
 495  *
 496  * Apply applicable errata and restrictions from 0.5 of the
 497  * Errata and Restrictions document from Marvell/Galileo.
 498  */
 499 static void __init
 500 gt64260_check_errata(struct pci_controller *hose_a,
 501                      struct pci_controller *hose_b)
 502 {
 503         u32     val;
 504         u8      save_exclude;
 505
 506         /* Currently 2 versions, 64260 and 64260A */
 507         if (gt64260_revision == GT64260) {
 508                 save_exclude = gt64260_pci_exclude_bridge;
 509                 gt64260_pci_exclude_bridge = FALSE;
 510
 511                 if (hose_a != (struct pci_controller *)NULL) {
 512                         /* FEr#5, FEr#12 */
 513                         early_read_config_dword(hose_a,
 514                                                 hose_a->first_busno,
 515                                                 PCI_DEVFN(0,0),
 516                                                 PCI_COMMAND,
 517                                                 &val);
 518                         val &= ~(PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY);
 519                         early_write_config_dword(hose_a,
 520                                                  hose_a->first_busno,
 521                                                  PCI_DEVFN(0,0),
 522                                                  PCI_COMMAND,
 523                                                  val);
 524                         /* FEr#12, FEr#13 */
 525                         gt_clr_bits(GT64260_PCI_0_CMD,
 526                                         ((1<<4) | (1<<5) | (1<<9)));
 527                         /* FEr#12, FEr#13 */
 528                         gt_clr_bits(GT64260_PCI_0_CMD,
 529                                         ((1<<4) | (1<<5) | (1<<9)));
 530
 531                         gt_clr_bits(GT64260_PCI_0_CMD, (1<<13));
 532                 }
 533
 534                 if (hose_b != (struct pci_controller *)NULL) {
 535                         early_read_config_dword(hose_b,
 536                                                 hose_b->first_busno,
 537                                                 PCI_DEVFN(0,0),
 538                                                 PCI_COMMAND,
 539                                                 &val);
 540                         val &= ~(PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY);
 541                         early_write_config_dword(hose_b,
 542                                                  hose_b->first_busno,
 543                                                  PCI_DEVFN(0,0),
 544                                                  PCI_COMMAND,
 545                                                  val);
 546                         /* FEr#12, FEr#13 */
 547                         gt_clr_bits(GT64260_PCI_1_CMD,
 548                                         ((1<<4) | (1<<5) | (1<<9)));
 549                         /* FEr#12, FEr#13 */
 550                         gt_clr_bits(GT64260_PCI_1_CMD,
 551                                         ((1<<4) | (1<<5) | (1<<9)));
 552                         gt_clr_bits(GT64260_PCI_1_CMD, (1<<13));
 553                 }
 554
 555                 gt64260_pci_exclude_bridge = save_exclude;
 556
 557                 /* FEr#54 */
 558                 gt_clr_bits(GT64260_CPU_SNOOP_BASE_0, 0xfffcf000);
 559                 gt_clr_bits(GT64260_CPU_SNOOP_BASE_1, 0xfffcf000);
 560                 gt_clr_bits(GT64260_CPU_SNOOP_BASE_2, 0xfffcf000);
 561                 gt_clr_bits(GT64260_CPU_SNOOP_BASE_3, 0xfffcf000);
 562
 563                 /* R#18 */
 564                 gt_set_bits(GT64260_SDRAM_CONFIG, (1<<26));
 565
 566         } else if (gt64260_revision == GT64260A) {
 567                 /* R#18 */
 568                 /* cpu read buffer to buffer 1 (reg 0x0448) */
 569                 gt_set_bits(GT64260_SDRAM_CONFIG, (1<<26));
 570
 571                 /* No longer errata so turn on */
 572                 /* Enable pci read/write combine, master write trigger,
 573                  * disable slave sync barrier
 574                  * readmultiple (reg 0x0c00 and 0x0c80)
 575                  */
 576                 if (hose_a != (struct pci_controller *)NULL) {
 577                         gt_set_bits(GT64260_PCI_0_CMD,
 578                                 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
 579                 }
 580
 581                 if (hose_b != (struct pci_controller *)NULL) {
 582                         gt_set_bits(GT64260_PCI_1_CMD,
 583                                 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
 584                 }
 585         }
 586
 587         return;
 588 } /* gt64260_check_errata() */
 589
 590
 591 /*
 592  *****************************************************************************
 593  *
 594  *      General Window Setting Routines
 595  *
 596  *****************************************************************************
 597  */
 598
 599 static int
 600 gt64260_set_32bit_window(u32 base_addr,
 601                          u32 size,
 602                          u32 other_bits,
 603                          u32 bot_reg,
 604                          u32 top_reg)
 605 {
 606         u32     val;
 607
 608         if (size > 0) {
 609                 /* Set up the window on the CPU side */
 610                 gt_write(bot_reg, (base_addr >> 20) | other_bits);
 611                 gt_write(top_reg, (base_addr + size - 1) >> 20);
 612         } else { /* Disable window */
 613                 gt_write(top_reg, 0x00000000);
 614                 gt_write(bot_reg, 0x00000fff | other_bits);
 615         }
 616
 617         val = gt_read(bot_reg); /* Flush FIFO */
 618         return 0;
 619 } /* gt64260_set_32bit_window() */
 620
 621 static int
 622 gt64260_set_64bit_window(u32 base_addr_hi,
 623                          u32 base_addr_lo,
 624                          u32 size,
 625                          u32 other_bits,
 626                          u32 bot_reg_hi,
 627                          u32 bot_reg_lo,
 628                          u32 top_reg)
 629 {
 630         int     rc;
 631
 632         if ((rc = gt64260_set_32bit_window(base_addr_lo,
 633                                            size,
 634                                            other_bits,
 635                                            bot_reg_lo,
 636                                            top_reg)) == 0) {
 637
 638                 gt_write(bot_reg_hi, base_addr_hi);
 639                 base_addr_hi = gt_read(bot_reg_hi); /* Flush FIFO */
 640         }
 641
 642         return rc;
 643 } /* gt64260_set_64bit_window() */
 644
 645
 646 /*
 647  *****************************************************************************
 648  *
 649  *      CPU Configuration Routines
 650  *
 651  *****************************************************************************
 652  */
 653
 654 #ifdef  NOTDEF
 655 int
 656 gt64260_cpu_scs_set_window(u32 window,
 657                            u32 base_addr,
 658                            u32 size)
 659 {
 660         static u32
 661         cpu_scs_windows[GT64260_CPU_SCS_DECODE_WINDOWS][2] = {
 662                 { GT64260_CPU_SCS_DECODE_0_BOT, GT64260_CPU_SCS_DECODE_0_TOP },
 663                 { GT64260_CPU_SCS_DECODE_1_BOT, GT64260_CPU_SCS_DECODE_1_TOP },
 664                 { GT64260_CPU_SCS_DECODE_2_BOT, GT64260_CPU_SCS_DECODE_2_TOP },
 665                 { GT64260_CPU_SCS_DECODE_3_BOT, GT64260_CPU_SCS_DECODE_3_TOP },
 666         }; /* cpu_scs_windows[][] */
 667         int     rc = -1;
 668
 669         if (window < GT64260_CPU_SCS_DECODE_WINDOWS) {
 670                 rc = gt64260_set_32bit_window(base_addr,
 671                                               size,
 672                                               0,
 673                                               cpu_scs_windows[window][0],
 674                                               cpu_scs_windows[window][1]);
 675         }
 676
 677         return rc;
 678 } /* gt64260_cpu_scs_set_window() */
 679 #endif  /* NOTDEF */
 680
 681 int
 682 gt64260_cpu_cs_set_window(u32 window,
 683                           u32 base_addr,
 684                           u32 size)
 685 {
 686         static u32
 687         cpu_cs_windows[GT64260_CPU_CS_DECODE_WINDOWS][2] = {
 688                 { GT64260_CPU_CS_DECODE_0_BOT, GT64260_CPU_CS_DECODE_0_TOP },
 689                 { GT64260_CPU_CS_DECODE_1_BOT, GT64260_CPU_CS_DECODE_1_TOP },
 690                 { GT64260_CPU_CS_DECODE_2_BOT, GT64260_CPU_CS_DECODE_2_TOP },
 691                 { GT64260_CPU_CS_DECODE_3_BOT, GT64260_CPU_CS_DECODE_3_TOP },
 692         }; /* cpu_cs_windows[][] */
 693         int     rc = -1;
 694
 695         if (window < GT64260_CPU_CS_DECODE_WINDOWS) {
 696                 rc = gt64260_set_32bit_window(base_addr,
 697                                               size,
 698                                               0,
 699                                               cpu_cs_windows[window][0],
 700                                               cpu_cs_windows[window][1]);
 701         }
 702
 703         return rc;
 704 } /* gt64260_cpu_cs_set_window() */
 705
 706 int
 707 gt64260_cpu_boot_set_window(u32 base_addr,
 708                             u32 size)
 709 {
 710         int     rc;
 711
 712         rc = gt64260_set_32bit_window(base_addr,
 713                                       size,
 714                                       0,
 715                                       GT64260_CPU_BOOT_CS_DECODE_0_BOT,
 716                                       GT64260_CPU_BOOT_CS_DECODE_0_TOP);
 717
 718         return rc;
 719 } /* gt64260_cpu_boot_set_window() */
 720
 721 /*
 722  * gt64260_cpu_set_pci_io_window()
 723  *
 724  * Set up a CPU window into PCI I/O or MEM space.
 725  * Always do Read/Modify/Write to window regs.
 726  */
 727 static int
 728 gt64260_cpu_pci_set_window(u32 cpu_base_addr,
 729                            u32 pci_base_addr,
 730                            u32 size,
 731                            u32 other_bits,
 732                            u32 bot_reg,
 733                            u32 top_reg,
 734                            u32 remap_reg)
 735 {
 736         u32     val;
 737         int     rc;
 738
 739         if ((rc = gt64260_set_32bit_window(cpu_base_addr,
 740                                            size,
 741                                            other_bits,
 742                                            bot_reg,
 743                                            top_reg)) == 0) {
 744
 745                 /* Set up CPU->PCI remapping (on lower 32 bits) */
 746                 gt_write(remap_reg, pci_base_addr >> 20);
 747                 val = gt_read(bot_reg); /* Flush FIFO */
 748         }
 749
 750         return rc;
 751 } /* gt64260_cpu_pci_set_window() */
 752
 753
 754 /*
 755  * gt64260_cpu_set_pci_io_window()
 756  *
 757  * Set up a CPU window into PCI I/O space.
 758  * Always do Read/Modify/Write to window regs.
 759  */
 760 int
 761 gt64260_cpu_set_pci_io_window(u32 pci_bus,
 762                               u32 cpu_base_addr,
 763                               u32 pci_base_addr,
 764                               u32 size,
 765                               u32 swap)
 766 {
 767         /* 2 PCI buses with 1 I/O window each (from CPU point of view) */
 768         static u32
 769         cpu_pci_io_windows[GT64260_PCI_BUSES][3] = {
 770                 { GT64260_CPU_PCI_0_IO_DECODE_BOT,
 771                   GT64260_CPU_PCI_0_IO_DECODE_TOP,
 772                   GT64260_CPU_PCI_0_IO_REMAP },
 773
 774                 { GT64260_CPU_PCI_1_IO_DECODE_BOT,
 775                   GT64260_CPU_PCI_1_IO_DECODE_TOP,
 776                   GT64260_CPU_PCI_1_IO_REMAP },
 777         }; /* cpu_pci_io_windows[][] */
 778         int     rc = -1;
 779
 780         if (pci_bus < GT64260_PCI_BUSES) {
 781                 rc =  gt64260_cpu_pci_set_window(cpu_base_addr,
 782                                           pci_base_addr,
 783                                           size,
 784                                           swap,
 785                                           cpu_pci_io_windows[pci_bus][0],
 786                                           cpu_pci_io_windows[pci_bus][1],
 787                                           cpu_pci_io_windows[pci_bus][2]);
 788         }
 789
 790         return rc;
 791 } /* gt64260_cpu_set_pci_io_window() */
 792
 793 /*
 794  * gt64260_cpu_set_pci_mem_window()
 795  *
 796  * Set up a CPU window into PCI MEM space (4 PCI MEM windows per PCI bus).
 797  * Always do Read/Modify/Write to window regs.
 798  */
 799 int
 800 gt64260_cpu_set_pci_mem_window(u32 pci_bus,
 801                                u32 window,
 802                                u32 cpu_base_addr,
 803                                u32 pci_base_addr_hi,
 804                                u32 pci_base_addr_lo,
 805                                u32 size,
 806                                u32 swap_64bit)
 807 {
 808         /* 2 PCI buses with 4 memory windows each (from CPU point of view) */
 809         static u32
 810         cpu_pci_mem_windows[GT64260_PCI_BUSES][GT64260_PCI_MEM_WINDOWS_PER_BUS][4] = {
 811                 { /* PCI 0 */
 812                         { GT64260_CPU_PCI_0_MEM_0_DECODE_BOT,
 813                           GT64260_CPU_PCI_0_MEM_0_DECODE_TOP,
 814                           GT64260_CPU_PCI_0_MEM_0_REMAP_HI,
 815                           GT64260_CPU_PCI_0_MEM_0_REMAP_LO },
 816
 817                         { GT64260_CPU_PCI_0_MEM_1_DECODE_BOT,
 818                           GT64260_CPU_PCI_0_MEM_1_DECODE_TOP,
 819                           GT64260_CPU_PCI_0_MEM_1_REMAP_HI,
 820                           GT64260_CPU_PCI_0_MEM_1_REMAP_LO },
 821
 822                         { GT64260_CPU_PCI_0_MEM_2_DECODE_BOT,
 823                           GT64260_CPU_PCI_0_MEM_2_DECODE_TOP,
 824                           GT64260_CPU_PCI_0_MEM_2_REMAP_HI,
 825                           GT64260_CPU_PCI_0_MEM_2_REMAP_LO },
 826
 827                         { GT64260_CPU_PCI_0_MEM_3_DECODE_BOT,
 828                           GT64260_CPU_PCI_0_MEM_3_DECODE_TOP,
 829                           GT64260_CPU_PCI_0_MEM_3_REMAP_HI,
 830                           GT64260_CPU_PCI_0_MEM_3_REMAP_LO }
 831                 },
 832
 833                 { /* PCI 1 */
 834                         { GT64260_CPU_PCI_1_MEM_0_DECODE_BOT,
 835                           GT64260_CPU_PCI_1_MEM_0_DECODE_TOP,
 836                           GT64260_CPU_PCI_1_MEM_0_REMAP_HI,
 837                           GT64260_CPU_PCI_1_MEM_0_REMAP_LO },
 838
 839                         { GT64260_CPU_PCI_1_MEM_1_DECODE_BOT,
 840                           GT64260_CPU_PCI_1_MEM_1_DECODE_TOP,
 841                           GT64260_CPU_PCI_1_MEM_1_REMAP_HI,
 842                           GT64260_CPU_PCI_1_MEM_1_REMAP_LO },
 843
 844                         { GT64260_CPU_PCI_1_MEM_2_DECODE_BOT,
 845                           GT64260_CPU_PCI_1_MEM_2_DECODE_TOP,
 846                           GT64260_CPU_PCI_1_MEM_2_REMAP_HI,
 847                           GT64260_CPU_PCI_1_MEM_2_REMAP_LO },
 848
 849                         { GT64260_CPU_PCI_1_MEM_3_DECODE_BOT,
 850                           GT64260_CPU_PCI_1_MEM_3_DECODE_TOP,
 851                           GT64260_CPU_PCI_1_MEM_3_REMAP_HI,
 852                           GT64260_CPU_PCI_1_MEM_3_REMAP_LO },
 853                 }
 854         }; /* cpu_pci_mem_windows[][][] */
 855         u32             remap_reg, remap;
 856         int             rc = -1;
 857
 858         if ((pci_bus < GT64260_PCI_BUSES) &&
 859             (window < GT64260_PCI_MEM_WINDOWS_PER_BUS)) {
 860
 861                 if (gt64260_cpu_pci_set_window(
 862                         cpu_base_addr,
 863                         pci_base_addr_lo,
 864                         size,
 865                         swap_64bit,
 866                         cpu_pci_mem_windows[pci_bus][window][0],
 867                         cpu_pci_mem_windows[pci_bus][window][1],
 868                         cpu_pci_mem_windows[pci_bus][window][3]) == 0) {
 869
 870                         remap_reg = cpu_pci_mem_windows[pci_bus][window][2];
 871                         gt_write(remap_reg, pci_base_addr_hi);
 872
 873                         remap = gt_read(remap_reg); /* Flush FIFO */
 874
 875                         rc = 0;
 876                 }
 877         }
 878
 879         return rc;
 880 } /* gt64260_cpu_set_pci_mem_window() */
 881
 882 int
 883 gt64260_cpu_prot_set_window(u32 window,
 884                             u32 base_addr,
 885                             u32 size,
 886                             u32 access_bits)
 887 {
 888         static u32
 889         cpu_prot_windows[GT64260_CPU_PROT_WINDOWS][2] = {
 890                 { GT64260_CPU_PROT_BASE_0, GT64260_CPU_PROT_TOP_0 },
 891                 { GT64260_CPU_PROT_BASE_1, GT64260_CPU_PROT_TOP_1 },
 892                 { GT64260_CPU_PROT_BASE_2, GT64260_CPU_PROT_TOP_2 },
 893                 { GT64260_CPU_PROT_BASE_3, GT64260_CPU_PROT_TOP_3 },
 894                 { GT64260_CPU_PROT_BASE_4, GT64260_CPU_PROT_TOP_4 },
 895                 { GT64260_CPU_PROT_BASE_5, GT64260_CPU_PROT_TOP_5 },
 896                 { GT64260_CPU_PROT_BASE_6, GT64260_CPU_PROT_TOP_6 },
 897                 { GT64260_CPU_PROT_BASE_7, GT64260_CPU_PROT_TOP_7 },
 898         }; /* cpu_prot_windows[][] */
 899         int     rc = -1;
 900
 901         if (window < GT64260_CPU_PROT_WINDOWS) {
 902                 rc = gt64260_set_32bit_window(base_addr,
 903                                               size,
 904                                               access_bits,
 905                                               cpu_prot_windows[window][0],
 906                                               cpu_prot_windows[window][1]);
 907         }
 908
 909         return rc;
 910 } /* gt64260_cpu_prot_set_window() */
 911
 912 int
 913 gt64260_cpu_snoop_set_window(u32 window,
 914                              u32 base_addr,
 915                              u32 size,
 916                              u32  snoop_type)
 917 {
 918         static u32
 919         cpu_snoop_windows[GT64260_CPU_SNOOP_WINDOWS][2] = {
 920                 { GT64260_CPU_SNOOP_BASE_0, GT64260_CPU_SNOOP_TOP_0 },
 921                 { GT64260_CPU_SNOOP_BASE_1, GT64260_CPU_SNOOP_TOP_1 },
 922                 { GT64260_CPU_SNOOP_BASE_2, GT64260_CPU_SNOOP_TOP_2 },
 923                 { GT64260_CPU_SNOOP_BASE_3, GT64260_CPU_SNOOP_TOP_3 },
 924         }; /* cpu_snoop_windows[][] */
 925         int     rc = -1;
 926
 927         if ((window < GT64260_CPU_SNOOP_WINDOWS) &&
 928             (snoop_type <= GT64260_CPU_SNOOP_WB)) {
 929
 930                 rc = gt64260_set_32bit_window(base_addr,
 931                                               size,
 932                                               snoop_type,
 933                                               cpu_snoop_windows[window][0],
 934                                               cpu_snoop_windows[window][1]);
 935         }
 936
 937         return rc;
 938 } /* gt64260_cpu_snoop_set_window() */
 939
 940 void
 941 gt64260_cpu_disable_windows(void)
 942 {
 943         int     pci_bus, window;
 944
 945         /* Leave SCS windows alone because we're running from memory */
 946
 947         /*
 948          * Note: Don't put any progress msgs between shutting down CS windows
 949          * and re-enabling them because the console device may be behind one
 950          * of those windows.
 951          */
 952         for (window=0; window<GT64260_PCI_CS_WINDOWS; window++) {
 953                 gt64260_cpu_cs_set_window(window, 0, 0);
 954         }
 955
 956         gt64260_cpu_boot_set_window(0, 0);
 957
 958         for (pci_bus=0; pci_bus<GT64260_PCI_BUSES; pci_bus++) {
 959                 gt64260_cpu_set_pci_io_window(pci_bus, 0, 0, 0, 0);
 960
 961                 for (window=0;window<GT64260_PCI_MEM_WINDOWS_PER_BUS;window++) {
 962                         gt64260_cpu_set_pci_mem_window(pci_bus,
 963                                                        window,
 964                                                        0, 0, 0, 0, 0);
 965                 }
 966         }
 967
 968         return;
 969 } /* gt64260_cpu_disable_windows() */
 970
 971
 972 /*
 973  *****************************************************************************
 974  *
 975  *      PCI Slave Window Configuration Routines
 976  *
 977  *****************************************************************************
 978  */
 979
 980 int
 981 gt64260_pci_bar_enable(u32 pci_bus,
 982                        u32 enable_bits)
 983 {
 984         u32     reg;
 985         int     rc = -1;
 986
 987         if (pci_bus < GT64260_PCI_BUSES) {
 988                 reg = (pci_bus == 0) ? GT64260_PCI_0_SLAVE_BAR_REG_ENABLES :
 989                                        GT64260_PCI_1_SLAVE_BAR_REG_ENABLES;
 990
 991                 /* Note: '0' enables, '1' disables */
 992                 gt_write(reg, ~enable_bits);
 993                 gt_read(reg); /* Flush FIFO */
 994
 995                 rc = 0;
 996         }
 997
 998         return rc;
 999 } /* gt64260_pci_bar_enable() */
1000
1001 static int
1002 gt64260_pci_slave_set_window(struct pci_controller *hose,
1003                              u32 pci_base_addr,
1004                              u32 cpu_base_addr,
1005                              u32 bar_size,
1006                              u32 pci_cfg_fcn,
1007                              u32 pci_cfg_hdr_offset,
1008                              u32 bar_size_reg,
1009                              u32 remap_reg)
1010 {
1011         u32     val;
1012         int     devfn;
1013         u8      save_exclude;
1014
1015         pci_base_addr &= 0xfffff000;
1016         cpu_base_addr &= 0xfffff000;
1017         bar_size &= 0xfffff000;
1018         devfn = PCI_DEVFN(0, pci_cfg_fcn);
1019
1020         gt_write(bar_size_reg, (bar_size - 1) & 0xfffff000);
1021         gt_write(remap_reg, cpu_base_addr);
1022         gt_read(remap_reg); /* Flush FIFO */
1023
1024         save_exclude = gt64260_pci_exclude_bridge;
1025         gt64260_pci_exclude_bridge = FALSE;
1026         early_read_config_dword(hose,
1027                                 hose->first_busno,
1028                                 devfn,
1029                                 pci_cfg_hdr_offset,
1030                                 &val);
1031         val &= 0x0000000f;
1032
1033 #ifdef DEBUG
1034         printk(__FUNCTION__ ": setting busno %08x, devfn %08x, offset %08x -> %08x\n",
1035                 hose->first_busno,  devfn, pci_cfg_hdr_offset, pci_base_addr | val);
1036 #endif
1037
1038         early_write_config_dword(hose,
1039                                  hose->first_busno,
1040                                  devfn,
1041                                  pci_cfg_hdr_offset,
1042                                  pci_base_addr | val);
1043         gt64260_pci_exclude_bridge = save_exclude;
1044
1045         return 0;
1046 } /* gt64260_pci_slave_set_window() */
1047
1048 int
1049 gt64260_pci_slave_scs_set_window(struct pci_controller *hose,
1050                                  u32 window,
1051                                  u32 pci_base_addr,
1052                                  u32 cpu_base_addr,
1053                                  u32 size)
1054 {
1055         static u32
1056         pci_scs_windows[GT64260_PCI_BUSES][GT64260_PCI_SCS_WINDOWS][4] = {
1057                 { /* PCI 0 */
1058                         { 0, 0x10,
1059                           GT64260_PCI_0_SLAVE_SCS_0_SIZE,
1060                           GT64260_PCI_0_SLAVE_SCS_0_REMAP },
1061                         { 0, 0x14,
1062                           GT64260_PCI_0_SLAVE_SCS_1_SIZE,
1063                           GT64260_PCI_0_SLAVE_SCS_1_REMAP },
1064                         { 0, 0x18,
1065                           GT64260_PCI_0_SLAVE_SCS_2_SIZE,
1066                           GT64260_PCI_0_SLAVE_SCS_2_REMAP },
1067                         { 0, 0x1c,
1068                           GT64260_PCI_0_SLAVE_SCS_3_SIZE,
1069                           GT64260_PCI_0_SLAVE_SCS_3_REMAP },
1070                 },
1071                 { /* PCI 1 */
1072                         { 0, 0x10,
1073                           GT64260_PCI_1_SLAVE_SCS_0_SIZE,
1074                           GT64260_PCI_1_SLAVE_SCS_0_REMAP },
1075                         { 0, 0x14,
1076                           GT64260_PCI_1_SLAVE_SCS_1_SIZE,
1077                           GT64260_PCI_1_SLAVE_SCS_1_REMAP },
1078                         { 0, 0x18,
1079                           GT64260_PCI_1_SLAVE_SCS_2_SIZE,
1080                           GT64260_PCI_1_SLAVE_SCS_2_REMAP },
1081                         { 0, 0x1c,
1082                           GT64260_PCI_1_SLAVE_SCS_3_SIZE,
1083                           GT64260_PCI_1_SLAVE_SCS_3_REMAP },
1084                 }
1085         }; /* pci_scs_windows[][][] */
1086         int     pci_bus;
1087         int     rc = -1;
1088
1089         if (window < GT64260_PCI_SCS_WINDOWS) {
1090                 pci_bus = (hose->first_busno == 0) ? 0 : 1;
1091
1092 #ifdef DEBUG
1093                 printk(__FUNCTION__ ": bus %d: hose->first_busno: %d\n", pci_bus, hose->first_busno);
1094 #endif
1095                 rc = gt64260_pci_slave_set_window(
1096                                 hose,
1097                                 pci_base_addr,
1098                                 cpu_base_addr,
1099                                 size,
1100                                 pci_scs_windows[pci_bus][window][0],
1101                                 pci_scs_windows[pci_bus][window][1],
1102                                 pci_scs_windows[pci_bus][window][2],
1103                                 pci_scs_windows[pci_bus][window][3]);
1104         }
1105
1106         return rc;
1107 } /* gt64260_pci_slave_scs_set_window() */
1108
1109 #ifdef  NOTDEF
1110 int
1111 gt64260_pci_slave_cs_set_window(struct pci_controller *hose,
1112                                 u32 window,
1113                                 u32 pci_base_addr,
1114                                 u32 cpu_base_addr,
1115                                 u32 size)
1116 {
1117         static u32
1118         pci_cs_windows[GT64260_PCI_BUSES][GT64260_PCI_CS_WINDOWS][4] = {
1119                 { /* PCI 0 */
1120                         { 1, 0x10,
1121                           GT64260_PCI_0_SLAVE_CS_0_SIZE,
1122                           GT64260_PCI_0_SLAVE_CS_0_REMAP },
1123                         { 1, 0x14,
1124                           GT64260_PCI_0_SLAVE_CS_1_SIZE,
1125                           GT64260_PCI_0_SLAVE_CS_1_REMAP },
1126                         { 1, 0x18,
1127                           GT64260_PCI_0_SLAVE_CS_2_SIZE,
1128                           GT64260_PCI_0_SLAVE_CS_2_REMAP },
1129                         { 1, 0x1c,
1130                           GT64260_PCI_0_SLAVE_CS_3_SIZE,
1131                           GT64260_PCI_0_SLAVE_CS_3_REMAP },
1132                 },
1133                 { /* PCI 1 */
1134                         { 1, 0x10,
1135                           GT64260_PCI_1_SLAVE_CS_0_SIZE,
1136                           GT64260_PCI_1_SLAVE_CS_0_REMAP },
1137                         { 1, 0x14,
1138                           GT64260_PCI_1_SLAVE_CS_1_SIZE,
1139                           GT64260_PCI_1_SLAVE_CS_1_REMAP },
1140                         { 1, 0x18,
1141                           GT64260_PCI_1_SLAVE_CS_2_SIZE,
1142                           GT64260_PCI_1_SLAVE_CS_2_REMAP },
1143                         { 1, 0x1c,
1144                           GT64260_PCI_1_SLAVE_CS_3_SIZE,
1145                           GT64260_PCI_1_SLAVE_CS_3_REMAP },
1146                 }
1147         }; /* pci_cs_windows[][][] */
1148         int     pci_bus;
1149         int     rc = -1;
1150
1151         if (window < GT64260_PCI_CS_WINDOWS) {
1152                 pci_bus = (hose->first_busno == 0) ? 0 : 1;
1153
1154                 rc = gt64260_pci_slave_set_window(
1155                                 hose,
1156                                 pci_base_addr,
1157                                 cpu_base_addr,
1158                                 size,
1159                                 pci_cs_windows[pci_bus][window][0],
1160                                 pci_cs_windows[pci_bus][window][1],
1161                                 pci_cs_windows[pci_bus][window][2],
1162                                 pci_cs_windows[pci_bus][window][3]);
1163         }
1164
1165         return rc;
1166 } /* gt64260_pci_slave_cs_set_window() */
1167
1168 int
1169 gt64260_pci_slave_boot_set_window(struct pci_controller *hose,
1170                                   u32 pci_base_addr,
1171                                   u32 cpu_base_addr,
1172                                   u32 size)
1173 {
1174         static u32
1175         pci_boot_table[GT64260_PCI_BUSES][2] = {
1176                 { /* PCI 0 */
1177                   GT64260_PCI_0_SLAVE_BOOT_SIZE,
1178                   GT64260_PCI_0_SLAVE_BOOT_REMAP,
1179                 },
1180                 { /* PCI 1 */
1181                   GT64260_PCI_1_SLAVE_BOOT_SIZE,
1182                   GT64260_PCI_1_SLAVE_BOOT_REMAP,
1183                 }
1184         }; /* pci_boot_table[][] */
1185         int     pci_bus;
1186         int     rc;
1187
1188         pci_bus = (hose->first_busno == 0) ? 0 : 1;
1189
1190         rc = gt64260_pci_slave_set_window(hose,
1191                                           pci_base_addr,
1192                                           cpu_base_addr,
1193                                           size,
1194                                           1,
1195                                           0x20,
1196                                           pci_boot_table[pci_bus][0],
1197                                           pci_boot_table[pci_bus][1]);
1198
1199         return rc;
1200 } /* gt64260_pci_slave_boot_set_window() */
1201
1202 int
1203 gt64260_pci_slave_p2p_mem_set_window(struct pci_controller *hose,
1204                                      u32 window,
1205                                      u32 pci_base_addr,
1206                                      u32 other_bus_base_addr,
1207                                      u32 size)
1208 {
1209         static u32
1210         pci_p2p_mem_windows[GT64260_PCI_BUSES][GT64260_PCI_P2P_MEM_WINDOWS][4]={
1211                 { /* PCI 0 */
1212                         { 2, 0x10,
1213                           GT64260_PCI_0_SLAVE_P2P_MEM_0_SIZE,
1214                           GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_LO },
1215                         { 2, 0x14,
1216                           GT64260_PCI_0_SLAVE_P2P_MEM_1_SIZE,
1217                           GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_LO },
1218                 },
1219                 { /* PCI 1 */
1220                         { 2, 0x10,
1221                           GT64260_PCI_1_SLAVE_P2P_MEM_0_SIZE,
1222                           GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_LO },
1223                         { 2, 0x14,
1224                           GT64260_PCI_1_SLAVE_P2P_MEM_1_SIZE,
1225                           GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_LO },
1226                 }
1227         }; /* pci_p2p_mem_windows[][][] */
1228         int     pci_bus;
1229         int     rc = -1;
1230
1231         if (window < GT64260_PCI_P2P_MEM_WINDOWS) {
1232                 pci_bus = (hose->first_busno == 0) ? 0 : 1;
1233
1234                 rc = gt64260_pci_slave_set_window(
1235                                 hose,
1236                                 pci_base_addr,
1237                                 other_bus_base_addr,
1238                                 size,
1239                                 pci_p2p_mem_windows[pci_bus][window][0],
1240                                 pci_p2p_mem_windows[pci_bus][window][1],
1241                                 pci_p2p_mem_windows[pci_bus][window][2],
1242                                 pci_p2p_mem_windows[pci_bus][window][3]);
1243         }
1244
1245         return rc;
1246 } /* gt64260_pci_slave_p2p_mem_set_window() */
1247
1248 int
1249 gt64260_pci_slave_p2p_io_set_window(struct pci_controller *hose,
1250                                     u32 pci_base_addr,
1251                                     u32 other_bus_base_addr,
1252                                     u32 size)
1253 {
1254         static u32
1255         pci_p2p_io_table[GT64260_PCI_BUSES][2] = {
1256                 { /* PCI 0 */
1257                   GT64260_PCI_0_SLAVE_P2P_IO_SIZE,
1258                   GT64260_PCI_0_SLAVE_P2P_IO_REMAP,
1259                 },
1260                 { /* PCI 1 */
1261                   GT64260_PCI_1_SLAVE_P2P_IO_SIZE,
1262                   GT64260_PCI_1_SLAVE_P2P_IO_REMAP,
1263                 }
1264         }; /* pci_p2p_io_table[][] */
1265         int     pci_bus;
1266         int     rc;
1267
1268         pci_bus = (hose->first_busno == 0) ? 0 : 1;
1269
1270         rc = gt64260_pci_slave_set_window(hose,
1271                                   pci_base_addr,
1272                                   other_bus_base_addr,
1273                                   size,
1274                                   2,
1275                                   0x18,
1276                                   pci_p2p_io_table[pci_bus][0],
1277                                   pci_p2p_io_table[pci_bus][1]);
1278
1279         return rc;
1280 } /* gt64260_pci_slave_p2p_io_set_window() */
1281
1282 int
1283 gt64260_pci_slave_dac_scs_set_window(struct pci_controller *hose,
1284                                      u32 window,
1285                                      u32 pci_base_addr_hi,
1286                                      u32 pci_base_addr_lo,
1287                                      u32 cpu_base_addr,
1288                                      u32 size)
1289 {
1290         static u32
1291         pci_dac_scs_windows[GT64260_PCI_BUSES][GT64260_PCI_DAC_SCS_WINDOWS][5]={
1292                 { /* PCI 0 */
1293                         { 4, 0x10, 0x14,
1294                           GT64260_PCI_0_SLAVE_DAC_SCS_0_SIZE,
1295                           GT64260_PCI_0_SLAVE_DAC_SCS_0_REMAP },
1296                         { 4, 0x18, 0x1c,
1297                           GT64260_PCI_0_SLAVE_DAC_SCS_1_SIZE,
1298                           GT64260_PCI_0_SLAVE_DAC_SCS_1_REMAP },
1299                         { 5, 0x10, 0x14,
1300                           GT64260_PCI_0_SLAVE_DAC_SCS_2_SIZE,
1301                           GT64260_PCI_0_SLAVE_DAC_SCS_2_REMAP },
1302                         { 5, 0x18, 0x1c,
1303                           GT64260_PCI_0_SLAVE_DAC_SCS_3_SIZE,
1304                           GT64260_PCI_0_SLAVE_DAC_SCS_3_REMAP },
1305                 },
1306                 { /* PCI 1 */
1307                         { 4, 0x10, 0x14,
1308                           GT64260_PCI_1_SLAVE_DAC_SCS_0_SIZE,
1309                           GT64260_PCI_1_SLAVE_DAC_SCS_0_REMAP },
1310                         { 4, 0x18, 0x1c,
1311                           GT64260_PCI_1_SLAVE_DAC_SCS_1_SIZE,
1312                           GT64260_PCI_1_SLAVE_DAC_SCS_1_REMAP },
1313                         { 5, 0x10, 0x14,
1314                           GT64260_PCI_1_SLAVE_DAC_SCS_2_SIZE,
1315                           GT64260_PCI_1_SLAVE_DAC_SCS_2_REMAP },
1316                         { 5, 0x18, 0x1c,
1317                           GT64260_PCI_1_SLAVE_DAC_SCS_3_SIZE,
1318                           GT64260_PCI_1_SLAVE_DAC_SCS_3_REMAP },
1319                 }
1320         }; /* pci_dac_scs_windows[][][] */
1321         int     pci_bus;
1322         int     rc = -1;
1323
1324         if (window < GT64260_PCI_DAC_SCS_WINDOWS) {
1325                 pci_bus = (hose->first_busno == 0) ? 0 : 1;
1326
1327                 rc = gt64260_pci_slave_set_window(
1328                                 hose,
1329                                 pci_base_addr_lo,
1330                                 cpu_base_addr,
1331                                 size,
1332                                 pci_dac_scs_windows[pci_bus][window][0],
1333                                 pci_dac_scs_windows[pci_bus][window][1],
1334                                 pci_dac_scs_windows[pci_bus][window][3],
1335                                 pci_dac_scs_windows[pci_bus][window][4]);
1336
1337                 early_write_config_dword(
1338                         hose,
1339                         hose->first_busno,
1340                         PCI_DEVFN(0, pci_dac_scs_windows[pci_bus][window][0]),
1341                         pci_dac_scs_windows[pci_bus][window][2],
1342                         pci_base_addr_hi);
1343         }
1344
1345         return rc;
1346 } /* gt64260_pci_slave_dac_scs_set_window() */
1347
1348 int
1349 gt64260_pci_slave_dac_cs_set_window(struct pci_controller *hose,
1350                                     u32 window,
1351                                     u32 pci_base_addr_hi,
1352                                     u32 pci_base_addr_lo,
1353                                     u32 cpu_base_addr,
1354                                     u32 size)
1355 {
1356         static u32
1357         pci_dac_cs_windows[GT64260_PCI_BUSES][GT64260_PCI_DAC_CS_WINDOWS][5] = {
1358                 { /* PCI 0 */
1359                         { 6, 0x10, 0x14,
1360                           GT64260_PCI_0_SLAVE_DAC_CS_0_SIZE,
1361                           GT64260_PCI_0_SLAVE_DAC_CS_0_REMAP },
1362                         { 6, 0x18, 0x1c,
1363                           GT64260_PCI_0_SLAVE_DAC_CS_1_SIZE,
1364                           GT64260_PCI_0_SLAVE_DAC_CS_1_REMAP },
1365                         { 6, 0x20, 0x24,
1366                           GT64260_PCI_0_SLAVE_DAC_CS_2_SIZE,
1367                           GT64260_PCI_0_SLAVE_DAC_CS_2_REMAP },
1368                         { 7, 0x10, 0x14,
1369                           GT64260_PCI_0_SLAVE_DAC_CS_3_SIZE,
1370                           GT64260_PCI_0_SLAVE_DAC_CS_3_REMAP },
1371                 },
1372                 { /* PCI 1 */
1373                         { 6, 0x10, 0x14,
1374                           GT64260_PCI_1_SLAVE_DAC_CS_0_SIZE,
1375                           GT64260_PCI_1_SLAVE_DAC_CS_0_REMAP },
1376                         { 6, 0x18, 0x1c,
1377                           GT64260_PCI_1_SLAVE_DAC_CS_1_SIZE,
1378                           GT64260_PCI_1_SLAVE_DAC_CS_1_REMAP },
1379                         { 6, 0x20, 0x24,
1380                           GT64260_PCI_1_SLAVE_DAC_CS_2_SIZE,
1381                           GT64260_PCI_1_SLAVE_DAC_CS_2_REMAP },
1382                         { 7, 0x10, 0x14,
1383                           GT64260_PCI_1_SLAVE_DAC_CS_3_SIZE,
1384                           GT64260_PCI_1_SLAVE_DAC_CS_3_REMAP },
1385                 }
1386         }; /* pci_dac_cs_windows[][][] */
1387         int     pci_bus;
1388         int     rc = -1;
1389
1390         if (window < GT64260_PCI_CS_WINDOWS) {
1391                 pci_bus = (hose->first_busno == 0) ? 0 : 1;
1392
1393                 rc = gt64260_pci_slave_set_window(
1394                                 hose,
1395                                 pci_base_addr_lo,
1396                                 cpu_base_addr,
1397                                 size,
1398                                 pci_dac_cs_windows[pci_bus][window][0],
1399                                 pci_dac_cs_windows[pci_bus][window][1],
1400                                 pci_dac_cs_windows[pci_bus][window][3],
1401                                 pci_dac_cs_windows[pci_bus][window][4]);
1402
1403                 early_write_config_dword(
1404                         hose,
1405                         hose->first_busno,
1406                         PCI_DEVFN(0, pci_dac_cs_windows[pci_bus][window][0]),
1407                         pci_dac_cs_windows[pci_bus][window][2],
1408                         pci_base_addr_hi);
1409         }
1410
1411         return rc;
1412 } /* gt64260_pci_slave_dac_cs_set_window() */
1413
1414 int
1415 gt64260_pci_slave_dac_boot_set_window(struct pci_controller *hose,
1416                                       u32 pci_base_addr_hi,
1417                                       u32 pci_base_addr_lo,
1418                                       u32 cpu_base_addr,
1419                                       u32 size)
1420 {
1421         static u32
1422         pci_dac_boot_table[GT64260_PCI_BUSES][2] = {
1423                 { /* PCI 0 */
1424                   GT64260_PCI_0_SLAVE_DAC_BOOT_SIZE,
1425                   GT64260_PCI_0_SLAVE_DAC_BOOT_REMAP,
1426                 },
1427                 { /* PCI 1 */
1428                   GT64260_PCI_1_SLAVE_DAC_BOOT_SIZE,
1429                   GT64260_PCI_1_SLAVE_DAC_BOOT_REMAP,
1430                 }
1431         }; /* pci_dac_boot_table[][] */
1432         int     pci_bus;
1433         int     rc;
1434
1435         pci_bus = (hose->first_busno == 0) ? 0 : 1;
1436
1437         rc = gt64260_pci_slave_set_window(hose,
1438                                           pci_base_addr_lo,
1439                                           cpu_base_addr,
1440                                           size,
1441                                           7,
1442                                           0x18,
1443                                           pci_dac_boot_table[pci_bus][0],
1444                                           pci_dac_boot_table[pci_bus][1]);
1445
1446         early_write_config_dword(hose,
1447                                  hose->first_busno,
1448                                  PCI_DEVFN(0, 7),
1449                                  0x1c,
1450                                  pci_base_addr_hi);
1451
1452         return rc;
1453 } /* gt64260_pci_slave_dac_boot_set_window() */
1454
1455 int
1456 gt64260_pci_slave_dac_p2p_mem_set_window(struct pci_controller *hose,
1457                                          u32 window,
1458                                          u32 pci_base_addr_hi,
1459                                          u32 pci_base_addr_lo,
1460                                          u32 other_bus_base_addr,
1461                                          u32 size)
1462 {
1463         static u32
1464         pci_dac_p2p_mem_windows[GT64260_PCI_BUSES][GT64260_PCI_DAC_P2P_MEM_WINDOWS][5] = {
1465                 { /* PCI 0 */
1466                         { 4, 0x20, 0x24,
1467                           GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_SIZE,
1468                           GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_LO },
1469                         { 5, 0x20, 0x24,
1470                           GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_SIZE,
1471                           GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_LO },
1472                 },
1473                 { /* PCI 1 */
1474                         { 4, 0xa0, 0xa4,
1475                           GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_SIZE,
1476                           GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_LO },
1477                         { 5, 0xa0, 0xa4,
1478                           GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_SIZE,
1479                           GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_LO },
1480                 }
1481         }; /* pci_dac_p2p_windows[][][] */
1482         int     pci_bus;
1483         int     rc = -1;
1484
1485         if (window < GT64260_PCI_P2P_MEM_WINDOWS) {
1486                 pci_bus = (hose->first_busno == 0) ? 0 : 1;
1487
1488                 rc = gt64260_pci_slave_set_window(
1489                                 hose,
1490                                 pci_base_addr_lo,
1491                                 other_bus_base_addr,
1492                                 size,
1493                                 pci_dac_p2p_mem_windows[pci_bus][window][0],
1494                                 pci_dac_p2p_mem_windows[pci_bus][window][1],
1495                                 pci_dac_p2p_mem_windows[pci_bus][window][3],
1496                                 pci_dac_p2p_mem_windows[pci_bus][window][4]);
1497
1498                 early_write_config_dword(
1499                     hose,
1500                     hose->first_busno,
1501                     PCI_DEVFN(0, pci_dac_p2p_mem_windows[pci_bus][window][0]),
1502                     pci_dac_p2p_mem_windows[pci_bus][window][2],
1503                     pci_base_addr_hi);
1504         }
1505
1506         return rc;
1507 } /* gt64260_pci_slave_dac_p2p_mem_set_window() */
1508 #endif  /* NOTDEF */
1509
1510
1511 /*
1512  *****************************************************************************
1513  *
1514  *      PCI Control Configuration Routines
1515  *
1516  *****************************************************************************
1517  */
1518
1519
1520 int
1521 gt64260_pci_acc_cntl_set_window(u32 pci_bus,
1522                                 u32 window,
1523                                 u32 base_addr_hi,
1524                                 u32 base_addr_lo,
1525                                 u32 size,
1526                                 u32 features)
1527 {
1528         static u32
1529         pci_acc_cntl_windows[GT64260_PCI_BUSES][GT64260_PCI_ACC_CNTL_WINDOWS][3] = {
1530                 { /* PCI 0 */
1531                         { GT64260_PCI_0_ACC_CNTL_0_BASE_HI,
1532                           GT64260_PCI_0_ACC_CNTL_0_BASE_LO,
1533                           GT64260_PCI_0_ACC_CNTL_0_TOP },
1534
1535                         { GT64260_PCI_0_ACC_CNTL_1_BASE_HI,
1536                           GT64260_PCI_0_ACC_CNTL_1_BASE_LO,
1537                           GT64260_PCI_0_ACC_CNTL_1_TOP },
1538
1539                         { GT64260_PCI_0_ACC_CNTL_2_BASE_HI,
1540                           GT64260_PCI_0_ACC_CNTL_2_BASE_LO,
1541                           GT64260_PCI_0_ACC_CNTL_2_TOP },
1542
1543                         { GT64260_PCI_0_ACC_CNTL_3_BASE_HI,
1544                           GT64260_PCI_0_ACC_CNTL_3_BASE_LO,
1545                           GT64260_PCI_0_ACC_CNTL_3_TOP },
1546
1547                         { GT64260_PCI_0_ACC_CNTL_4_BASE_HI,
1548                           GT64260_PCI_0_ACC_CNTL_4_BASE_LO,
1549                           GT64260_PCI_0_ACC_CNTL_4_TOP },
1550
1551                         { GT64260_PCI_0_ACC_CNTL_5_BASE_HI,
1552                           GT64260_PCI_0_ACC_CNTL_5_BASE_LO,
1553                           GT64260_PCI_0_ACC_CNTL_5_TOP },
1554
1555                         { GT64260_PCI_0_ACC_CNTL_6_BASE_HI,
1556                           GT64260_PCI_0_ACC_CNTL_6_BASE_LO,
1557                           GT64260_PCI_0_ACC_CNTL_6_TOP },
1558
1559                         { GT64260_PCI_0_ACC_CNTL_7_BASE_HI,
1560                           GT64260_PCI_0_ACC_CNTL_7_BASE_LO,
1561                           GT64260_PCI_0_ACC_CNTL_7_TOP },
1562                 },
1563                 { /* PCI 1 */
1564                         { GT64260_PCI_1_ACC_CNTL_0_BASE_HI,
1565                           GT64260_PCI_1_ACC_CNTL_0_BASE_LO,
1566                           GT64260_PCI_1_ACC_CNTL_0_TOP },
1567
1568                         { GT64260_PCI_1_ACC_CNTL_1_BASE_HI,
1569                           GT64260_PCI_1_ACC_CNTL_1_BASE_LO,
1570                           GT64260_PCI_1_ACC_CNTL_1_TOP },
1571
1572                         { GT64260_PCI_1_ACC_CNTL_2_BASE_HI,
1573                           GT64260_PCI_1_ACC_CNTL_2_BASE_LO,
1574                           GT64260_PCI_1_ACC_CNTL_2_TOP },
1575
1576                         { GT64260_PCI_1_ACC_CNTL_3_BASE_HI,
1577                           GT64260_PCI_1_ACC_CNTL_3_BASE_LO,
1578                           GT64260_PCI_1_ACC_CNTL_3_TOP },
1579
1580                         { GT64260_PCI_1_ACC_CNTL_4_BASE_HI,
1581                           GT64260_PCI_1_ACC_CNTL_4_BASE_LO,
1582                           GT64260_PCI_1_ACC_CNTL_4_TOP },
1583
1584                         { GT64260_PCI_1_ACC_CNTL_5_BASE_HI,
1585                           GT64260_PCI_1_ACC_CNTL_5_BASE_LO,
1586                           GT64260_PCI_1_ACC_CNTL_5_TOP },
1587
1588                         { GT64260_PCI_1_ACC_CNTL_6_BASE_HI,
1589                           GT64260_PCI_1_ACC_CNTL_6_BASE_LO,
1590                           GT64260_PCI_1_ACC_CNTL_6_TOP },
1591
1592                         { GT64260_PCI_1_ACC_CNTL_7_BASE_HI,
1593                           GT64260_PCI_1_ACC_CNTL_7_BASE_LO,
1594                           GT64260_PCI_1_ACC_CNTL_7_TOP },
1595                 }
1596         }; /* pci_acc_cntl_windows[][][] */
1597         int     rc = -1;
1598
1599         if ((pci_bus < GT64260_PCI_BUSES) &&
1600             (window < GT64260_PCI_ACC_CNTL_WINDOWS)) {
1601
1602                 rc = gt64260_set_64bit_window(
1603                               base_addr_hi,
1604                               base_addr_lo,
1605                               size,
1606                               features,
1607                               pci_acc_cntl_windows[pci_bus][window][0],
1608                               pci_acc_cntl_windows[pci_bus][window][1],
1609                               pci_acc_cntl_windows[pci_bus][window][2]);
1610         }
1611
1612         return rc;
1613 } /* gt64260_pci_acc_cntl_set_window() */
1614
1615 int
1616 gt64260_pci_snoop_set_window(u32 pci_bus,
1617                              u32 window,
1618                              u32 base_addr_hi,
1619                              u32 base_addr_lo,
1620                              u32 size,
1621                              u32 snoop_type)
1622 {
1623         static u32
1624         pci_snoop_windows[GT64260_PCI_BUSES][GT64260_PCI_SNOOP_WINDOWS][3] = {
1625                 { /* PCI 0 */
1626                         { GT64260_PCI_0_SNOOP_0_BASE_HI,
1627                           GT64260_PCI_0_SNOOP_0_BASE_LO,
1628                           GT64260_PCI_0_SNOOP_0_TOP },
1629
1630                         { GT64260_PCI_0_SNOOP_1_BASE_HI,
1631                           GT64260_PCI_0_SNOOP_1_BASE_LO,
1632                           GT64260_PCI_0_SNOOP_1_TOP },
1633
1634                         { GT64260_PCI_0_SNOOP_2_BASE_HI,
1635                           GT64260_PCI_0_SNOOP_2_BASE_LO,
1636                           GT64260_PCI_0_SNOOP_2_TOP },
1637
1638                         { GT64260_PCI_0_SNOOP_3_BASE_HI,
1639                           GT64260_PCI_0_SNOOP_3_BASE_LO,
1640                           GT64260_PCI_0_SNOOP_3_TOP },
1641                 },
1642                 { /* PCI 1 */
1643                         { GT64260_PCI_1_SNOOP_0_BASE_HI,
1644                           GT64260_PCI_1_SNOOP_0_BASE_LO,
1645                           GT64260_PCI_1_SNOOP_0_TOP },
1646
1647                         { GT64260_PCI_1_SNOOP_1_BASE_HI,
1648                           GT64260_PCI_1_SNOOP_1_BASE_LO,
1649                           GT64260_PCI_1_SNOOP_1_TOP },
1650
1651                         { GT64260_PCI_1_SNOOP_2_BASE_HI,
1652                           GT64260_PCI_1_SNOOP_2_BASE_LO,
1653                           GT64260_PCI_1_SNOOP_2_TOP },
1654
1655                         { GT64260_PCI_1_SNOOP_3_BASE_HI,
1656                           GT64260_PCI_1_SNOOP_3_BASE_LO,
1657                           GT64260_PCI_1_SNOOP_3_TOP },
1658                 },
1659         }; /* pci_snoop_windows[][][] */
1660         int     rc = -1;
1661
1662         if ((pci_bus < GT64260_PCI_BUSES) &&
1663             (window < GT64260_PCI_SNOOP_WINDOWS)) {
1664
1665                 rc = gt64260_set_64bit_window(
1666                               base_addr_hi,
1667                               base_addr_lo,
1668                               size,
1669                               snoop_type,
1670                               pci_snoop_windows[pci_bus][window][0],
1671                               pci_snoop_windows[pci_bus][window][1],
1672                               pci_snoop_windows[pci_bus][window][2]);
1673         }
1674
1675         return rc;
1676 } /* gt64260_pci_snoop_set_window() */
1677
1678 /*
1679  *****************************************************************************
1680  *
1681  *      64260's Register Base Address Routines
1682  *
1683  *****************************************************************************
1684  */
1685
1686 /*
1687  * gt64260_remap_bridge_regs()
1688  *
1689  * Move the bridge's register to the specified base address.
1690  * Assume that there are no other windows overlapping this area and that
1691  * all but the highest 3 nibbles are 0.
1692  */
1693 int
1694 gt64260_set_base(u32 new_phys_base)
1695 {
1696         u32     val;
1697         int     limit = 100000;
1698         int     rc = 0;
1699
1700         val = gt_read(GT64260_INTERNAL_SPACE_DECODE);
1701         val = (new_phys_base >> 20) | (val & 0xffff0000);
1702         gt_write(GT64260_INTERNAL_SPACE_DECODE, val);
1703
1704         iounmap((void *)gt64260_base);
1705         gt64260_base = (u32)ioremap((new_phys_base & 0xfff00000),
1706                                     GT64260_INTERNAL_SPACE_SIZE);
1707
1708         /* Wait for bridge to move its regs */
1709         while ((gt_read(GT64260_INTERNAL_SPACE_DECODE)!=val) && (limit-- > 0));
1710
1711         if (limit <= 0) {
1712                 rc = -1;
1713         }
1714
1715         return rc;
1716 } /* gt64260_remap_bridge_regs() */
1717
1718 /*
1719  * gt64260_get_base()
1720  *
1721  * Return the current virtual base address of the 64260's registers.
1722  */
1723 int
1724 gt64260_get_base(u32 *base)
1725 {
1726         *base = gt64260_base;
1727         return 0;
1728 } /* gt64260_remap_bridge_regs() */
1729
1730
1731 /*
1732  *****************************************************************************
1733  *
1734  *      Exclude PCI config space access to bridge itself
1735  *
1736  *****************************************************************************
1737  */
1738
1739 /*
1740  * gt64260_exclude_pci_device()
1741  *
1742  * This routine causes the PCI subsystem to skip the PCI device in slot 0
1743  * (which is the 64260 itself) unless explicitly allowed.
1744  */
1745 int
1746 gt64260_pci_exclude_device(u8 bus, u8 devfn)
1747 {
1748         struct pci_controller   *hose;
1749
1750         hose = pci_bus_to_hose(bus);
1751
1752         /* Skip slot 0 on both hoses */
1753         if ((gt64260_pci_exclude_bridge == TRUE) &&
1754             (PCI_SLOT(devfn) == 0) &&
1755             (hose->first_busno == bus)) {
1756                 return PCIBIOS_DEVICE_NOT_FOUND;
1757         }
1758         else {
1759                 return PCIBIOS_SUCCESSFUL;
1760         }
1761 } /* gt64260_pci_exclude_device() */
1762
1763 /*
1764  *****************************************************************************
1765  *
1766  *      Misc Routines
1767  *
1768  *****************************************************************************
1769  */
1770 /*
1771  * gt64260_get_mem_size()
1772  *
1773  * Read memory controller's registers to determine the amount of memory
1774  * in the system.  Assumes that the memeory controller has been set up
1775  * to the proper memory size.
1776  */
1777 ulong __init
1778 gt64260_get_mem_size(void)
1779 {
1780         static u32
1781         cpu_scs_windows[GT64260_CPU_SCS_DECODE_WINDOWS][2] = {
1782                 { GT64260_CPU_SCS_DECODE_0_BOT, GT64260_CPU_SCS_DECODE_0_TOP },
1783                 { GT64260_CPU_SCS_DECODE_1_BOT, GT64260_CPU_SCS_DECODE_1_TOP },
1784                 { GT64260_CPU_SCS_DECODE_2_BOT, GT64260_CPU_SCS_DECODE_2_TOP },
1785                 { GT64260_CPU_SCS_DECODE_3_BOT, GT64260_CPU_SCS_DECODE_3_TOP },
1786         }; /* cpu_scs_windows[][] */
1787         u32             window, top, bot;
1788         static u32      total = 0;
1789         static int      first_time = 1;
1790
1791         if (first_time) {
1792                 for (window=0; window<GT64260_CPU_SCS_DECODE_WINDOWS; window++){
1793                         bot = gt_read(cpu_scs_windows[window][0]) << 20;
1794                         top = (gt_read(cpu_scs_windows[window][1]) << 20) +
1795                                                                 0x00100000;
1796
1797                         if (top > bot) { /* Is window really open? */
1798                                 total += (top - bot);
1799                         }
1800                 }
1801
1802                 first_time = 0;
1803         }
1804
1805         return total;
1806 } /* gt64260_get_mem_size() */
1807
1808 #if defined(CONFIG_SERIAL_TEXT_DEBUG)
1809 /*
1810  *****************************************************************************
1811  *
1812  *      Low-level MPSC/UART I/O routines
1813  *
1814  *****************************************************************************
1815  */
1816
1817 /*
1818  * gt64260_putc()
1819  *
1820  * Dump a character out the MPSC port for gt64260_mpsc_progress
1821  * this assumes the baud rate has already been set up and the
1822  * MPSC initialized by the bootloader or firmware.
1823  */
1824
1825 static inline void
1826 gt_putc(char c)
1827 {
1828         mb();
1829         gt_write(GT64260_MPSC_0_CHR_1, c);
1830         mb();
1831         gt_write(GT64260_MPSC_0_CHR_2, 0x200);
1832         mb();
1833
1834         udelay(10000);
1835 }
1836
1837 void
1838 puthex(unsigned long val)
1839 {
1840
1841         int i;
1842
1843         for (i = 7;  i >= 0;  i--) {
1844                 gt_putc("0123456789ABCDEF"[(val>>28) & 0x0f]);
1845                 val <<= 4;
1846         }
1847         gt_putc('\r');
1848         gt_putc('\n');
1849
1850 }
1851
1852 void
1853 gt64260_mpsc_progress(char *s, unsigned short hex)
1854 {
1855         /* spit stuff out the 64260 mpsc */
1856
1857         volatile char   c;
1858         while ((c = *s++) != 0){
1859                 gt_putc(c);
1860                 if ( c == '\n' ) gt_putc('\r');
1861         }
1862         gt_putc('\n');
1863         gt_putc('\r');
1864
1865         return;
1866 }
1867
1868 #endif /* CONFIG_DEBUG_TEXT */
1869
1870 EXPORT_SYMBOL(gt64260_set_base);
1871 EXPORT_SYMBOL(gt64260_get_base);