2 * BK Id: SCCS/s.pci.c 1.70 01/12/03 10:51:00 benh
5 * Common pmac/prep/chrp pci routines. -- Cort
8 #include <linux/config.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/delay.h>
12 #include <linux/string.h>
13 #include <linux/init.h>
14 #include <linux/capability.h>
15 #include <linux/sched.h>
16 #include <linux/errno.h>
17 #include <linux/bootmem.h>
19 #include <asm/processor.h>
22 #include <asm/sections.h>
23 #include <asm/pci-bridge.h>
24 #include <asm/byteorder.h>
26 #include <asm/uaccess.h>
31 #define DBG(x...) printk(x)
36 unsigned long isa_io_base = 0;
37 unsigned long isa_mem_base = 0;
38 unsigned long pci_dram_offset = 0;
40 void pcibios_make_OF_bus_map(void);
42 static int pci_relocate_bridge_resource(struct pci_bus *bus, int i);
43 static int probe_resource(struct pci_bus *parent, struct resource *pr,
44 struct resource *res, struct resource **conflict);
45 static void update_bridge_base(struct pci_bus *bus, int i);
46 static void pcibios_fixup_resources(struct pci_dev* dev);
47 static void fixup_broken_pcnet32(struct pci_dev* dev);
48 static int reparent_resources(struct resource *parent, struct resource *res);
49 static void fixup_rev1_53c810(struct pci_dev* dev);
50 static void fixup_cpc710_pci64(struct pci_dev* dev);
52 static void pcibios_fixup_cardbus(struct pci_dev* dev);
53 static u8* pci_to_OF_bus_map;
56 /* By default, we don't re-assign bus numbers. We do this only on
59 int pci_assign_all_busses;
61 struct pci_controller* hose_head;
62 struct pci_controller** hose_tail = &hose_head;
64 static int pci_bus_count;
66 struct pci_fixup pcibios_fixups[] = {
67 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32 },
68 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810 },
69 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64},
70 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources },
72 /* We should add per-machine fixup support in xxx_setup.c or xxx_pci.c */
73 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_TI, PCI_ANY_ID, pcibios_fixup_cardbus },
74 #endif /* CONFIG_ALL_PPC */
79 fixup_rev1_53c810(struct pci_dev* dev)
81 /* rev 1 ncr53c810 chips don't set the class at all which means
82 * they don't get their resources remapped. Fix that here.
85 if ((dev->class == PCI_CLASS_NOT_DEFINED)) {
86 printk("NCR 53c810 rev 1 detected, setting PCI class.\n");
87 dev->class = PCI_CLASS_STORAGE_SCSI;
92 fixup_broken_pcnet32(struct pci_dev* dev)
94 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
95 dev->vendor = PCI_VENDOR_ID_AMD;
96 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
102 fixup_cpc710_pci64(struct pci_dev* dev)
106 /* Hide the PCI64 BARs from the kernel as their content doesn't
107 * fit well in the resource management
109 for (i=0; i<DEVICE_COUNT_RESOURCE; i++) {
110 dev->resource[i].start = dev->resource[i].end = 0;
111 dev->resource[i].flags = 0;
116 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
117 struct resource *res, int resource)
121 struct pci_controller* hose = dev->sysdata;
122 unsigned long io_offset;
125 res->flags &= ~IORESOURCE_UNSET;
126 if (hose && res->flags & IORESOURCE_IO) {
127 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
130 if (hose && res->flags & IORESOURCE_MEM)
131 new -= hose->pci_mem_offset;
132 new |= (res->flags & PCI_REGION_FLAG_MASK);
134 reg = PCI_BASE_ADDRESS_0 + 4*resource;
135 } else if (resource == PCI_ROM_RESOURCE) {
136 res->flags |= PCI_ROM_ADDRESS_ENABLE;
137 reg = dev->rom_base_reg;
139 /* Somebody might have asked allocation of a non-standard resource */
143 pci_write_config_dword(dev, reg, new);
144 pci_read_config_dword(dev, reg, &check);
145 if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
146 printk(KERN_ERR "PCI: Error while updating region "
147 "%s/%d (%08x != %08x)\n", dev->slot_name, resource,
150 printk(KERN_INFO "PCI: moved device %s resource %d (%lx) to %x\n",
151 dev->slot_name, resource, res->flags,
152 new & ~PCI_REGION_FLAG_MASK);
156 pcibios_fixup_resources(struct pci_dev *dev)
158 struct pci_controller* hose = (struct pci_controller *)dev->sysdata;
160 unsigned long offset;
163 printk(KERN_ERR "No hose for PCI dev %s!\n", dev->slot_name);
166 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
167 struct resource *res = dev->resource + i;
170 if (!res->start || res->end == 0xffffffff) {
171 DBG("PCI:%s Resource %d [%08lx-%08lx] is unassigned\n",
172 dev->slot_name, i, res->start, res->end);
173 res->end -= res->start;
175 res->flags |= IORESOURCE_UNSET;
179 if (res->flags & IORESOURCE_MEM) {
180 offset = hose->pci_mem_offset;
181 } else if (res->flags & IORESOURCE_IO) {
182 offset = (unsigned long) hose->io_base_virt
186 res->start += offset;
189 printk("Fixup res %d (%lx) of dev %s: %lx -> %lx\n",
190 i, res->flags, dev->slot_name,
191 res->start - offset, res->start);
196 /* Call machine specific resource fixup */
197 if (ppc_md.pcibios_fixup_resources)
198 ppc_md.pcibios_fixup_resources(dev);
201 #ifdef CONFIG_ALL_PPC
203 pcibios_fixup_cardbus(struct pci_dev* dev)
205 if (_machine != _MACH_Pmac)
208 * Fix the interrupt routing on the various cardbus bridges
211 if (dev->vendor != PCI_VENDOR_ID_TI)
213 if (dev->device == PCI_DEVICE_ID_TI_1130 ||
214 dev->device == PCI_DEVICE_ID_TI_1131) {
216 /* Enable PCI interrupt */
217 if (pci_read_config_byte(dev, 0x91, &val) == 0)
218 pci_write_config_byte(dev, 0x91, val | 0x30);
219 /* Disable ISA interrupt mode */
220 if (pci_read_config_byte(dev, 0x92, &val) == 0)
221 pci_write_config_byte(dev, 0x92, val & ~0x06);
223 if (dev->device == PCI_DEVICE_ID_TI_1210 ||
224 dev->device == PCI_DEVICE_ID_TI_1211 ||
225 dev->device == PCI_DEVICE_ID_TI_1410) {
227 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
228 signal out the MFUNC0 pin */
229 if (pci_read_config_byte(dev, 0x8c, &val) == 0)
230 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2);
231 /* Disable ISA interrupt mode */
232 if (pci_read_config_byte(dev, 0x92, &val) == 0)
233 pci_write_config_byte(dev, 0x92, val & ~0x06);
236 #endif /* CONFIG_ALL_PPC */
239 * We need to avoid collisions with `mirrored' VGA ports
240 * and other strange ISA hardware, so we always want the
241 * addresses to be allocated in the 0x000-0x0ff region
244 * Why? Because some silly external IO cards only decode
245 * the low 10 bits of the IO address. The 0x00-0xff region
246 * is reserved for motherboard devices that decode all 16
247 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
248 * but we want to try to avoid allocating at 0x2900-0x2bff
249 * which might have be mirrored at 0x0100-0x03ff..
252 pcibios_align_resource(void *data, struct resource *res, unsigned long size,
255 struct pci_dev *dev = data;
257 if (res->flags & IORESOURCE_IO) {
258 unsigned long start = res->start;
261 printk(KERN_ERR "PCI: I/O Region %s/%d too large"
262 " (%ld bytes)\n", dev->slot_name,
263 dev->resource - res, size);
267 start = (start + 0x3ff) & ~0x3ff;
275 * Handle resources of PCI devices. If the world were perfect, we could
276 * just allocate all the resource regions and do nothing more. It isn't.
277 * On the other hand, we cannot just re-allocate all devices, as it would
278 * require us to know lots of host bridge internals. So we attempt to
279 * keep as much of the original configuration as possible, but tweak it
280 * when it's found to be wrong.
282 * Known BIOS problems we have to work around:
283 * - I/O or memory regions not configured
284 * - regions configured, but not enabled in the command register
285 * - bogus I/O addresses above 64K used
286 * - expansion ROMs left enabled (this may sound harmless, but given
287 * the fact the PCI specs explicitly allow address decoders to be
288 * shared between expansion ROMs and other resource regions, it's
289 * at least dangerous)
292 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
293 * This gives us fixed barriers on where we can allocate.
294 * (2) Allocate resources for all enabled devices. If there is
295 * a collision, just mark the resource as unallocated. Also
296 * disable expansion ROMs during this step.
297 * (3) Try to allocate resources for disabled devices. If the
298 * resources were assigned correctly, everything goes well,
299 * if they weren't, they won't disturb allocation of other
301 * (4) Assign new addresses to resources which were either
302 * not configured at all or misconfigured. If explicitly
303 * requested by the user, configure expansion ROM address
308 pcibios_allocate_bus_resources(struct list_head *bus_list)
310 struct list_head *ln;
313 struct resource *res, *pr;
315 /* Depth-First Search on bus tree */
316 for (ln = bus_list->next; ln != bus_list; ln=ln->next) {
318 for (i = 0; i < 4; ++i) {
319 if ((res = bus->resource[i]) == NULL || !res->flags
320 || res->start > res->end)
322 if (bus->parent == NULL)
323 pr = (res->flags & IORESOURCE_IO)?
324 &ioport_resource: &iomem_resource;
326 pr = pci_find_parent_resource(bus->self, res);
328 /* this happens when the generic PCI
329 * code (wrongly) decides that this
330 * bridge is transparent -- paulus
336 DBG("PCI: bridge rsrc %lx..%lx (%lx), parent %p\n",
337 res->start, res->end, res->flags, pr);
339 if (request_resource(pr, res) == 0)
342 * Must be a conflict with an existing entry.
343 * Move that entry (or entries) under the
344 * bridge resource and try again.
346 if (reparent_resources(pr, res) == 0)
349 printk(KERN_ERR "PCI: Cannot allocate resource region "
350 "%d of PCI bridge %d\n", i, bus->number);
351 if (pci_relocate_bridge_resource(bus, i))
352 bus->resource[i] = NULL;
354 pcibios_allocate_bus_resources(&bus->children);
359 * Reparent resource children of pr that conflict with res
360 * under res, and make res replace those children.
363 reparent_resources(struct resource *parent, struct resource *res)
365 struct resource *p, **pp;
366 struct resource **firstpp = NULL;
368 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
369 if (p->end < res->start)
371 if (res->end < p->start)
373 if (p->start < res->start || p->end > res->end)
374 return -1; /* not completely contained */
379 return -1; /* didn't find any conflicting entries? */
380 res->parent = parent;
381 res->child = *firstpp;
385 for (p = res->child; p != NULL; p = p->sibling) {
387 DBG(KERN_INFO "PCI: reparented %s [%lx..%lx] under %s\n",
388 p->name, p->start, p->end, res->name);
394 * A bridge has been allocated a range which is outside the range
395 * of its parent bridge, so it needs to be moved.
398 pci_relocate_bridge_resource(struct pci_bus *bus, int i)
400 struct resource *res, *pr, *conflict;
401 unsigned long try, size;
403 struct pci_bus *parent = bus->parent;
405 if (parent == NULL) {
406 /* shouldn't ever happen */
407 printk(KERN_ERR "PCI: can't move host bridge resource\n");
410 res = bus->resource[i];
412 for (j = 0; j < 4; j++) {
413 struct resource *r = parent->resource[j];
416 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
418 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) {
422 if (res->flags & IORESOURCE_PREFETCH)
427 size = res->end - res->start;
428 if (pr->start > pr->end || size > pr->end - pr->start)
433 if (res->flags & IORESOURCE_MEM)
435 res->start = try - size - 1;
437 if (try <= size || res->start < pr->start)
439 if (probe_resource(bus->parent, pr, res, &conflict) == 0)
441 if (conflict->start <= pr->start + size)
443 try = conflict->start;
445 if (request_resource(pr, res)) {
446 DBG(KERN_ERR "PCI: huh? couldn't move to %lx..%lx\n",
447 res->start, res->end);
448 return -1; /* "can't happen" */
450 update_bridge_base(bus, i);
451 printk(KERN_INFO "PCI: bridge %d resource %d moved to %lx..%lx\n",
452 bus->number, i, res->start, res->end);
457 probe_resource(struct pci_bus *parent, struct resource *pr,
458 struct resource *res, struct resource **conflict)
463 struct list_head *ln;
466 for (r = pr->child; r != NULL; r = r->sibling) {
467 if (r->end >= res->start && res->end >= r->start) {
472 for (ln = parent->children.next; ln != &parent->children;
475 for (i = 0; i < 4; ++i) {
476 if ((r = bus->resource[i]) == NULL)
478 if (!r->flags || r->start > r->end || r == res)
480 if (pci_find_parent_resource(bus->self, r) != pr)
482 if (r->end >= res->start && res->end >= r->start) {
488 for (ln = parent->devices.next; ln != &parent->devices; ln=ln->next) {
490 for (i = 0; i < 6; ++i) {
491 r = &dev->resource[i];
492 if (!r->flags || (r->flags & IORESOURCE_UNSET))
494 if (pci_find_parent_resource(bus->self, r) != pr)
496 if (r->end >= res->start && res->end >= r->start) {
506 update_bridge_base(struct pci_bus *bus, int i)
508 struct resource *res = bus->resource[i];
509 u8 io_base_lo, io_limit_lo;
510 u16 mem_base, mem_limit;
512 unsigned long start, end, off;
513 struct pci_dev *dev = bus->self;
514 struct pci_controller *hose = dev->sysdata;
517 printk("update_bridge_base: no hose?\n");
520 pci_read_config_word(dev, PCI_COMMAND, &cmd);
521 pci_write_config_word(dev, PCI_COMMAND,
522 cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
523 if (res->flags & IORESOURCE_IO) {
525 off = (unsigned long) hose->io_base_virt - isa_io_base;
526 start = res->start - off;
527 end = res->end - off;
528 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
529 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
530 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &bu);
531 io_limit_lo &= PCI_IO_RANGE_TYPE_MASK;
532 if (io_base_lo == PCI_IO_RANGE_TYPE_16 && end > 0xffff) {
533 printk(KERN_ERR "bridge only supports 16-bit I/O!\n");
536 io_base_lo |= (start >> 8) & PCI_IO_RANGE_MASK;
537 io_limit_lo |= (end >> 8) & PCI_IO_RANGE_MASK;
538 pci_write_config_word(dev, PCI_IO_BASE_UPPER16, start >> 16);
539 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
540 pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo);
541 pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo);
543 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
545 off = hose->pci_mem_offset;
546 mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK;
547 mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK;
548 pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base);
549 pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit);
551 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
552 == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) {
553 off = hose->pci_mem_offset;
554 mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK;
555 mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK;
556 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base);
557 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);
560 DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n",
561 dev->slot_name, i, res->flags);
564 pci_write_config_word(dev, PCI_COMMAND, cmd);
567 static inline void alloc_resource(struct pci_dev *dev, int idx)
569 struct resource *pr, *r = &dev->resource[idx];
571 DBG("PCI:%s: Resource %d: %08lx-%08lx (f=%lx)\n",
572 dev->slot_name, idx, r->start, r->end, r->flags);
573 pr = pci_find_parent_resource(dev, r);
574 if (!pr || request_resource(pr, r) < 0) {
575 printk(KERN_ERR "PCI: Cannot allocate resource region %d"
576 " of device %s\n", idx, dev->slot_name);
578 DBG("PCI: parent is %p: %08lx-%08lx (f=%lx)\n",
579 pr, pr->start, pr->end, pr->flags);
580 /* We'll assign a new address later */
581 r->flags |= IORESOURCE_UNSET;
588 pcibios_allocate_resources(int pass)
595 pci_for_each_dev(dev) {
596 pci_read_config_word(dev, PCI_COMMAND, &command);
597 for (idx = 0; idx < 6; idx++) {
598 r = &dev->resource[idx];
599 if (r->parent) /* Already allocated */
601 if (!r->flags || (r->flags & IORESOURCE_UNSET))
602 continue; /* Not assigned at all */
603 if (r->flags & IORESOURCE_IO)
604 disabled = !(command & PCI_COMMAND_IO);
606 disabled = !(command & PCI_COMMAND_MEMORY);
607 if (pass == disabled)
608 alloc_resource(dev, idx);
612 r = &dev->resource[PCI_ROM_RESOURCE];
613 if (r->flags & PCI_ROM_ADDRESS_ENABLE) {
614 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
616 DBG("PCI: Switching off ROM of %s\n", dev->slot_name);
617 r->flags &= ~PCI_ROM_ADDRESS_ENABLE;
618 pci_read_config_dword(dev, dev->rom_base_reg, ®);
619 pci_write_config_dword(dev, dev->rom_base_reg,
620 reg & ~PCI_ROM_ADDRESS_ENABLE);
626 pcibios_assign_resources(void)
632 pci_for_each_dev(dev) {
633 int class = dev->class >> 8;
635 /* Don't touch classless devices and host bridges */
636 if (!class || class == PCI_CLASS_BRIDGE_HOST)
639 for (idx = 0; idx < 6; idx++) {
640 r = &dev->resource[idx];
643 * We shall assign a new address to this resource,
644 * either because the BIOS (sic) forgot to do so
645 * or because we have decided the old address was
646 * unusable for some reason.
648 if ((r->flags & IORESOURCE_UNSET) && r->end &&
649 (!ppc_md.pcibios_enable_device_hook ||
650 !ppc_md.pcibios_enable_device_hook(dev, 1)))
651 pci_assign_resource(dev, idx);
654 #if 0 /* don't assign ROMs */
655 r = &dev->resource[PCI_ROM_RESOURCE];
659 pci_assign_resource(dev, PCI_ROM_RESOURCE);
666 pcibios_enable_resources(struct pci_dev *dev)
672 pci_read_config_word(dev, PCI_COMMAND, &cmd);
674 for (idx=0; idx<6; idx++) {
675 r = &dev->resource[idx];
676 if (r->flags & IORESOURCE_UNSET) {
677 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", dev->slot_name);
680 if (r->flags & IORESOURCE_IO)
681 cmd |= PCI_COMMAND_IO;
682 if (r->flags & IORESOURCE_MEM)
683 cmd |= PCI_COMMAND_MEMORY;
685 if (dev->resource[PCI_ROM_RESOURCE].start)
686 cmd |= PCI_COMMAND_MEMORY;
687 if (cmd != old_cmd) {
688 printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
689 pci_write_config_word(dev, PCI_COMMAND, cmd);
694 static int next_controller_index;
696 struct pci_controller * __init
697 pcibios_alloc_controller(void)
699 struct pci_controller *hose;
701 hose = (struct pci_controller *)alloc_bootmem(sizeof(*hose));
702 memset(hose, 0, sizeof(struct pci_controller));
705 hose_tail = &hose->next;
707 hose->index = next_controller_index++;
712 #ifdef CONFIG_ALL_PPC
714 * Functions below are used on OpenFirmware machines.
716 static void __openfirmware
717 make_one_node_map(struct device_node* node, u8 pci_bus)
722 if (pci_bus >= pci_bus_count)
724 bus_range = (int *) get_property(node, "bus-range", &len);
725 if (bus_range == NULL || len < 2 * sizeof(int)) {
726 printk(KERN_WARNING "Can't get bus-range for %s\n",
730 pci_to_OF_bus_map[pci_bus] = bus_range[0];
732 for (node=node->child; node != 0;node = node->sibling) {
734 unsigned int *class_code, *reg;
736 class_code = (unsigned int *) get_property(node, "class-code", 0);
737 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
738 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
740 reg = (unsigned int *)get_property(node, "reg", 0);
743 dev = pci_find_slot(pci_bus, ((reg[0] >> 8) & 0xff));
744 if (!dev || !dev->subordinate)
746 make_one_node_map(node, dev->subordinate->number);
751 pcibios_make_OF_bus_map(void)
754 struct pci_controller* hose;
757 pci_to_OF_bus_map = (u8*)kmalloc(pci_bus_count, GFP_KERNEL);
758 if (!pci_to_OF_bus_map) {
759 printk(KERN_ERR "Can't allocate OF bus map !\n");
763 /* We fill the bus map with invalid values, that helps
766 for (i=0; i<pci_bus_count; i++)
767 pci_to_OF_bus_map[i] = 0xff;
769 /* For each hose, we begin searching bridges */
770 for(hose=hose_head; hose; hose=hose->next) {
771 struct device_node* node;
772 node = (struct device_node *)hose->arch_data;
775 make_one_node_map(node, hose->first_busno);
777 of_prop_map = get_property(find_path_device("/"), "pci-OF-bus-map", 0);
779 memcpy(of_prop_map, pci_to_OF_bus_map, pci_bus_count);
781 printk("PCI->OF bus map:\n");
782 for (i=0; i<pci_bus_count; i++) {
783 if (pci_to_OF_bus_map[i] == 0xff)
785 printk("%d -> %d\n", i, pci_to_OF_bus_map[i]);
790 typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data);
792 static struct device_node* __openfirmware
793 scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data)
795 struct device_node* sub_node;
797 for (; node != 0;node = node->sibling) {
798 unsigned int *class_code;
800 if (filter(node, data))
803 /* For PCI<->PCI bridges or CardBus bridges, we go down
804 * Note: some OFs create a parent node "multifunc-device" as
805 * a fake root for all functions of a multi-function device,
806 * we go down them as well.
808 class_code = (unsigned int *) get_property(node, "class-code", 0);
809 if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
810 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
811 strcmp(node->name, "multifunc-device"))
813 sub_node = scan_OF_pci_childs(node->child, filter, data);
821 scan_OF_pci_childs_iterator(struct device_node* node, void* data)
824 u8* fdata = (u8*)data;
826 reg = (unsigned int *) get_property(node, "reg", 0);
827 if (reg && ((reg[0] >> 8) & 0xff) == fdata[1]
828 && ((reg[0] >> 16) & 0xff) == fdata[0])
833 static struct device_node* __openfirmware
834 scan_OF_childs_for_device(struct device_node* node, u8 bus, u8 dev_fn)
836 u8 filter_data[2] = {bus, dev_fn};
838 return scan_OF_pci_childs(node, scan_OF_pci_childs_iterator, filter_data);
842 * Scans the OF tree for a device node matching a PCI device
845 pci_device_to_OF_node(struct pci_dev *dev)
847 struct pci_controller *hose;
848 struct device_node *node;
854 /* Lookup the hose */
855 bus = dev->bus->number;
856 hose = pci_bus_to_hose(bus);
860 /* Check it has an OF node associated */
861 node = (struct device_node *) hose->arch_data;
865 /* Fixup bus number according to what OF think it is. */
866 if (pci_to_OF_bus_map)
867 bus = pci_to_OF_bus_map[bus];
871 /* Now, lookup childs of the hose */
872 return scan_OF_childs_for_device(node->child, bus, dev->devfn);
875 /* This routine is meant to be used early during boot, when the
876 * PCI bus numbers have not yet been assigned, and you need to
877 * issue PCI config cycles to an OF device.
878 * It could also be used to "fix" RTAS config cycles if you want
879 * to set pci_assign_all_busses to 1 and still use RTAS for PCI
882 struct pci_controller*
883 pci_find_hose_for_OF_device(struct device_node* node)
888 struct pci_controller* hose;
889 for (hose=hose_head;hose;hose=hose->next)
890 if (hose->arch_data == node)
897 static int __openfirmware
898 find_OF_pci_device_filter(struct device_node* node, void* data)
900 return ((void *)node == data);
904 * Returns the PCI device matching a given OF node
907 pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn)
910 struct pci_controller* hose;
915 /* Make sure it's really a PCI device */
916 hose = pci_find_hose_for_OF_device(node);
917 if (!hose || !hose->arch_data)
919 if (!scan_OF_pci_childs(((struct device_node*)hose->arch_data)->child,
920 find_OF_pci_device_filter, (void *)node))
922 reg = (unsigned int *) get_property(node, "reg", 0);
925 *bus = (reg[0] >> 16) & 0xff;
926 *devfn = ((reg[0] >> 8) & 0xff);
928 /* Ok, here we need some tweak. If we have already renumbered
929 * all busses, we can't rely on the OF bus number any more.
930 * the pci_to_OF_bus_map is not enough as several PCI busses
931 * may match the same OF bus number.
933 if (!pci_to_OF_bus_map)
935 pci_for_each_dev(dev) {
936 if (pci_to_OF_bus_map[dev->bus->number] != *bus)
938 if (dev->devfn != *devfn)
940 *bus = dev->bus->number;
947 pci_process_bridge_OF_ranges(struct pci_controller *hose,
948 struct device_node *dev, int primary)
950 unsigned int *ranges, *prev;
953 struct resource *res;
954 int na = prom_n_addr_cells(dev);
958 /* First we try to merge ranges to fix a problem with some pmacs
959 * that can have more than 3 ranges, fortunately using contiguous
962 ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
964 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
966 if (prev[0] == ranges[0] && prev[1] == ranges[1] &&
967 (prev[2] + prev[na+4]) == ranges[2] &&
968 (prev[na+2] + prev[na+4]) == ranges[na+2]) {
969 prev[na+4] += ranges[na+4];
980 * The ranges property is laid out as an array of elements,
981 * each of which comprises:
982 * cells 0 - 2: a PCI address
983 * cells 3 or 3+4: a CPU physical address
984 * (size depending on dev->n_addr_cells)
985 * cells 4+5 or 5+6: the size of the range
988 hose->io_base_phys = 0;
989 ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
990 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
993 switch (ranges[0] >> 24) {
994 case 1: /* I/O space */
997 hose->io_base_phys = ranges[na+2];
998 /* limit I/O to 16MB */
999 if (size > 0x01000000)
1001 hose->io_base_virt = ioremap(ranges[na+2], size);
1003 isa_io_base = (unsigned long) hose->io_base_virt;
1004 res = &hose->io_resource;
1005 res->flags = IORESOURCE_IO;
1006 res->start = ranges[2];
1008 case 2: /* memory space */
1010 if (ranges[1] == 0 && ranges[2] == 0
1011 && ranges[na+4] <= (16 << 20)) {
1012 /* 1st 16MB, i.e. ISA memory area */
1014 isa_mem_base = ranges[na+2];
1017 while (memno < 3 && hose->mem_resources[memno].flags)
1020 hose->pci_mem_offset = ranges[na+2] - ranges[2];
1022 res = &hose->mem_resources[memno];
1023 res->flags = IORESOURCE_MEM;
1024 res->start = ranges[na+2];
1029 res->name = dev->full_name;
1030 res->end = res->start + size - 1;
1032 res->sibling = NULL;
1039 /* We create the "pci-OF-bus-map" property now so it appears in the
1043 pci_create_OF_bus_map(void)
1045 struct property* of_prop;
1047 of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256);
1048 if (of_prop && find_path_device("/")) {
1049 memset(of_prop, -1, sizeof(struct property) + 256);
1050 of_prop->name = "pci-OF-bus-map";
1051 of_prop->length = 256;
1052 of_prop->value = (unsigned char *)&of_prop[1];
1053 prom_add_property(find_path_device("/"), of_prop);
1056 #endif /* CONFIG_ALL_PPC */
1059 * This set of routines checks for PCI<->PCI bridges that have closed
1060 * IO resources and have child devices. It tries to re-open an IO
1063 * This is a _temporary_ fix to workaround a problem with Apple's OF
1064 * closing IO windows on P2P bridges when the OF drivers of cards
1065 * below this bridge don't claim any IO range (typically ATI or
1068 * A more complete fix would be to use drivers/pci/setup-bus.c, which
1069 * involves a working pcibios_fixup_pbus_ranges(), some more care about
1070 * ordering when creating the host bus resources, and maybe a few more
1074 /* Initialize bridges with base/limit values we have collected */
1076 do_update_p2p_io_resource(struct pci_bus *bus, int enable_vga)
1078 struct pci_dev *bridge = bus->self;
1079 struct pci_controller* hose = (struct pci_controller *)bridge->sysdata;
1082 struct resource res;
1084 res = *(bus->resource[0]);
1086 DBG("Remapping Bus %d, bridge: %s\n", bus->number, bridge->name);
1087 res.start -= ((unsigned long) hose->io_base_virt - isa_io_base);
1088 res.end -= ((unsigned long) hose->io_base_virt - isa_io_base);
1089 DBG(" IO window: %08lx-%08lx\n", res.start, res.end);
1091 /* Set up the top and bottom of the PCI I/O segment for this bus. */
1092 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
1094 l |= (res.start >> 8) & 0x00f0;
1095 l |= res.end & 0xf000;
1096 pci_write_config_dword(bridge, PCI_IO_BASE, l);
1098 if ((l & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
1099 l = (res.start >> 16) | (res.end & 0xffff0000);
1100 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, l);
1103 pci_read_config_word(bridge, PCI_COMMAND, &w);
1104 w |= PCI_COMMAND_IO;
1105 pci_write_config_word(bridge, PCI_COMMAND, w);
1107 #if 0 /* Enabling this causes XFree 4.2.0 to hang during PCI probe */
1109 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &w);
1110 w |= PCI_BRIDGE_CTL_VGA;
1111 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, w);
1116 /* This function is pretty basic and actually quite broken for the
1117 * general case, it's enough for us right now though. It's supposed
1118 * to tell us if we need to open an IO range at all or not and what
1122 check_for_io_childs(struct pci_bus *bus, struct resource* res, int *found_vga)
1124 struct list_head *ln;
1128 #define push_end(res, size) do { unsigned long __sz = (size) ; \
1129 res->end = ((res->end + __sz) / (__sz + 1)) * (__sz + 1) + __sz; \
1132 for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) {
1133 struct pci_dev *dev = pci_dev_b(ln);
1134 u16 class = dev->class >> 8;
1136 if (class == PCI_CLASS_DISPLAY_VGA ||
1137 class == PCI_CLASS_NOT_DEFINED_VGA)
1139 if (class >> 8 == PCI_BASE_CLASS_BRIDGE && dev->subordinate)
1140 rc |= check_for_io_childs(dev->subordinate, res, found_vga);
1141 if (class == PCI_CLASS_BRIDGE_CARDBUS)
1142 push_end(res, 0xfff);
1144 for (i=0; i<PCI_NUM_RESOURCES; i++) {
1146 unsigned long r_size;
1148 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI
1149 && i >= PCI_BRIDGE_RESOURCES)
1151 r = &dev->resource[i];
1152 r_size = r->end - r->start;
1155 if (r->flags & IORESOURCE_IO && (r_size) != 0) {
1157 push_end(res, r_size);
1165 /* Here we scan all P2P bridges of a given level that have a closed
1166 * IO window. Note that the test for the presence of a VGA card should
1167 * be improved to take into account already configured P2P bridges,
1168 * currently, we don't see them and might end up configuring 2 bridges
1169 * with VGA pass through enabled
1172 do_fixup_p2p_level(struct pci_bus *bus)
1174 struct list_head *ln;
1178 for (parent_io=0; parent_io<4; parent_io++)
1179 if (bus->resource[parent_io]->flags & IORESOURCE_IO)
1184 for (ln=bus->children.next; ln != &bus->children; ln=ln->next) {
1185 struct pci_bus *b = pci_bus_b(ln);
1186 struct pci_dev *d = b->self;
1187 struct pci_controller* hose = (struct pci_controller *)d->sysdata;
1188 struct resource *res = b->resource[0];
1189 struct resource tmp_res;
1193 memset(&tmp_res, 0, sizeof(tmp_res));
1194 tmp_res.start = bus->resource[parent_io]->start;
1196 /* We don't let low addresses go through that closed P2P bridge, well,
1197 * that may not be necessary but I feel safer that way
1199 if (tmp_res.start == 0)
1200 tmp_res.start = 0x1000;
1202 if (!list_empty(&b->devices) && res && res->flags == 0 &&
1203 res != bus->resource[parent_io] &&
1204 (d->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
1205 check_for_io_childs(b, &tmp_res, &found_vga)) {
1208 printk(KERN_INFO "Fixing up IO bus %s\n", b->name);
1212 printk(KERN_WARNING "Skipping VGA, already active"
1213 " on bus segment\n");
1218 pci_read_config_byte(d, PCI_IO_BASE, &io_base_lo);
1220 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32)
1221 max = ((unsigned long) hose->io_base_virt
1222 - isa_io_base) + 0xffffffff;
1224 max = ((unsigned long) hose->io_base_virt
1225 - isa_io_base) + 0xffff;
1228 res->flags = IORESOURCE_IO;
1229 res->name = b->name;
1231 /* Find a resource in the parent where we can allocate */
1232 for (i = 0 ; i < 4; i++) {
1233 struct resource *r = bus->resource[i];
1236 if ((r->flags & IORESOURCE_IO) == 0)
1238 DBG("Trying to allocate from %08lx, size %08lx from parent"
1239 " res %d: %08lx -> %08lx\n",
1240 res->start, res->end, i, r->start, r->end);
1242 if (allocate_resource(r, res, res->end + 1, res->start, max,
1243 res->end + 1, NULL, NULL) < 0) {
1247 do_update_p2p_io_resource(b, found_vga);
1251 do_fixup_p2p_level(b);
1256 pcibios_fixup_p2p_bridges(void)
1258 struct list_head *ln;
1260 for(ln=pci_root_buses.next; ln != &pci_root_buses; ln=ln->next) {
1261 struct pci_bus *b = pci_bus_b(ln);
1262 do_fixup_p2p_level(b);
1269 struct pci_controller *hose;
1270 struct pci_bus *bus;
1271 int next_busno, bus_offset;
1273 printk(KERN_INFO "PCI: Probing PCI hardware\n");
1275 /* There is a problem with bus renumbering currently. If
1276 * you have 2 sibling pci<->pci bridges, and during PCI
1277 * probe, the first one gets assigned a new number equal
1278 * to the old number of the second one, you'll end up
1279 * probing that branch with 2 bridges racing on the bus
1281 * I work around this on pmac by adding a large offset
1282 * between host bridges, though a better long term solution
1283 * will have to be found in the generic code. --BenH
1285 #ifdef CONFIG_ALL_PPC
1286 if (machine_is_compatible("MacRISC"))
1291 /* Scan all of the recorded PCI controllers. */
1292 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
1293 if (pci_assign_all_busses)
1294 hose->first_busno = next_busno;
1295 hose->last_busno = 0xff;
1296 bus = pci_scan_bus(hose->first_busno, hose->ops, hose);
1297 hose->last_busno = bus->subordinate;
1298 if (pci_assign_all_busses || next_busno <= hose->last_busno)
1299 next_busno = hose->last_busno + bus_offset;
1301 pci_bus_count = next_busno;
1303 /* OpenFirmware based machines need a map of OF bus
1304 * numbers vs. kernel bus numbers since we may have to
1307 if (pci_assign_all_busses && have_of)
1308 pcibios_make_OF_bus_map();
1310 /* Do machine dependent PCI interrupt routing */
1311 if (ppc_md.pci_swizzle && ppc_md.pci_map_irq)
1312 pci_fixup_irqs(ppc_md.pci_swizzle, ppc_md.pci_map_irq);
1314 /* Call machine dependant fixup */
1315 if (ppc_md.pcibios_fixup)
1316 ppc_md.pcibios_fixup();
1318 /* Allocate and assign resources */
1319 pcibios_allocate_bus_resources(&pci_root_buses);
1320 pcibios_allocate_resources(0);
1321 pcibios_allocate_resources(1);
1322 pcibios_fixup_p2p_bridges();
1323 pcibios_assign_resources();
1325 /* Call machine dependent post-init code */
1326 if (ppc_md.pcibios_after_init)
1327 ppc_md.pcibios_after_init();
1330 unsigned char __init
1331 common_swizzle(struct pci_dev *dev, unsigned char *pinp)
1333 struct pci_controller *hose = dev->sysdata;
1335 if (dev->bus->number != hose->first_busno) {
1338 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
1339 /* Move up the chain of bridges. */
1340 dev = dev->bus->self;
1341 } while (dev->bus->self);
1344 /* The slot is the idsel of the last bridge. */
1346 return PCI_SLOT(dev->devfn);
1350 pcibios_fixup_pbus_ranges(struct pci_bus * bus, struct pbus_set_ranges_data * ranges)
1352 ranges->io_start -= bus->resource[0]->start;
1353 ranges->io_end -= bus->resource[0]->start;
1354 ranges->mem_start -= bus->resource[1]->start;
1355 ranges->mem_end -= bus->resource[1]->start;
1358 unsigned long resource_fixup(struct pci_dev * dev, struct resource * res,
1359 unsigned long start, unsigned long size)
1364 void __init pcibios_fixup_bus(struct pci_bus *bus)
1366 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1367 unsigned long io_offset;
1368 struct resource *res;
1371 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1372 if (bus->parent == NULL) {
1373 /* This is a host bridge - fill in its resources */
1376 bus->resource[0] = res = &hose->io_resource;
1379 printk(KERN_ERR "I/O resource not set for host"
1380 " bridge %d\n", hose->index);
1382 res->end = IO_SPACE_LIMIT;
1383 res->flags = IORESOURCE_IO;
1385 res->start += io_offset;
1386 res->end += io_offset;
1388 for (i = 0; i < 3; ++i) {
1389 res = &hose->mem_resources[i];
1393 printk(KERN_ERR "Memory resource not set for "
1394 "host bridge %d\n", hose->index);
1395 res->start = hose->pci_mem_offset;
1397 res->flags = IORESOURCE_MEM;
1399 bus->resource[i+1] = res;
1402 /* This is a subordinate bridge */
1403 pci_read_bridge_bases(bus);
1405 for (i = 0; i < 4; ++i) {
1406 if ((res = bus->resource[i]) == NULL)
1410 if (io_offset && (res->flags & IORESOURCE_IO)) {
1411 res->start += io_offset;
1412 res->end += io_offset;
1413 } else if (hose->pci_mem_offset
1414 && (res->flags & IORESOURCE_MEM)) {
1415 res->start += hose->pci_mem_offset;
1416 res->end += hose->pci_mem_offset;
1421 if (ppc_md.pcibios_fixup_bus)
1422 ppc_md.pcibios_fixup_bus(bus);
1425 char __init *pcibios_setup(char *str)
1430 /* the next one is stolen from the alpha port... */
1432 pcibios_update_irq(struct pci_dev *dev, int irq)
1434 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
1435 /* XXX FIXME - update OF device tree node interrupt property */
1438 int pcibios_enable_device(struct pci_dev *dev, int mask)
1444 if (ppc_md.pcibios_enable_device_hook)
1445 if (ppc_md.pcibios_enable_device_hook(dev, 0))
1448 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1450 for (idx=0; idx<6; idx++) {
1451 if(!(mask & (1<<idx)))
1454 r = &dev->resource[idx];
1455 if (r->flags & IORESOURCE_UNSET) {
1456 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", dev->slot_name);
1459 if (r->flags & IORESOURCE_IO)
1460 cmd |= PCI_COMMAND_IO;
1461 if (r->flags & IORESOURCE_MEM)
1462 cmd |= PCI_COMMAND_MEMORY;
1464 if (cmd != old_cmd) {
1465 printk("PCI: Enabling device %s (%04x -> %04x)\n",
1466 dev->slot_name, old_cmd, cmd);
1467 pci_write_config_word(dev, PCI_COMMAND, cmd);
1472 struct pci_controller*
1473 pci_bus_to_hose(int bus)
1475 struct pci_controller* hose = hose_head;
1477 for (; hose; hose = hose->next)
1478 if (bus >= hose->first_busno && bus <= hose->last_busno)
1484 pci_bus_io_base(unsigned int bus)
1486 struct pci_controller *hose;
1488 hose = pci_bus_to_hose(bus);
1491 return hose->io_base_virt;
1495 pci_bus_io_base_phys(unsigned int bus)
1497 struct pci_controller *hose;
1499 hose = pci_bus_to_hose(bus);
1502 return hose->io_base_phys;
1506 pci_bus_mem_base_phys(unsigned int bus)
1508 struct pci_controller *hose;
1510 hose = pci_bus_to_hose(bus);
1513 return hose->pci_mem_offset;
1517 pci_resource_to_bus(struct pci_dev *pdev, struct resource *res)
1519 /* Hack alert again ! See comments in chrp_pci.c
1521 struct pci_controller* hose =
1522 (struct pci_controller *)pdev->sysdata;
1523 if (hose && res->flags & IORESOURCE_MEM)
1524 return res->start - hose->pci_mem_offset;
1525 /* We may want to do something with IOs here... */
1530 * Return the index of the PCI controller for device pdev.
1532 int pci_controller_num(struct pci_dev *dev)
1534 struct pci_controller *hose = (struct pci_controller *) dev->sysdata;
1540 * Platform support for /proc/bus/pci/X/Y mmap()s,
1541 * modelled on the sparc64 implementation by Dave Miller.
1546 * Adjust vm_pgoff of VMA such that it is the physical page offset
1547 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
1549 * Basically, the user finds the base address for his device which he wishes
1550 * to mmap. They read the 32-bit value from the config space base register,
1551 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
1552 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
1554 * Returns negative error code on failure, zero on success.
1556 static __inline__ int
1557 __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
1558 enum pci_mmap_state mmap_state)
1560 struct pci_controller *hose = (struct pci_controller *) dev->sysdata;
1561 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1562 unsigned long size = vma->vm_end - vma->vm_start;
1564 struct resource *res;
1569 return -EINVAL; /* should never happen */
1570 if (offset + size <= offset)
1573 if (mmap_state == pci_mmap_mem) {
1574 /* PCI memory space */
1575 base = hose->pci_mem_offset;
1576 for (i = 0; i < 3; ++i) {
1577 res = &hose->mem_resources[i];
1578 if (offset >= res->start - base
1579 && offset + size - 1 <= res->end - base) {
1584 offset += hose->pci_mem_offset;
1587 base = (unsigned long)hose->io_base_virt - isa_io_base;
1588 res = &hose->io_resource;
1589 if (offset >= res->start - base
1590 && offset + size - 1 <= res->end - base)
1592 offset += hose->io_base_phys;
1595 vma->vm_pgoff = offset >> PAGE_SHIFT;
1600 * Set vm_flags of VMA, as appropriate for this architecture, for a pci device
1603 static __inline__ void
1604 __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
1605 enum pci_mmap_state mmap_state)
1607 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
1611 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1614 static __inline__ void
1615 __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
1616 enum pci_mmap_state mmap_state, int write_combine)
1618 int prot = pgprot_val(vma->vm_page_prot);
1620 /* XXX would be nice to have a way to ask for write-through */
1621 prot |= _PAGE_NO_CACHE;
1623 prot |= _PAGE_GUARDED;
1624 vma->vm_page_prot = __pgprot(prot);
1628 * Perform the actual remap of the pages for a PCI device mapping, as
1629 * appropriate for this architecture. The region in the process to map
1630 * is described by vm_start and vm_end members of VMA, the base physical
1631 * address is found in vm_pgoff.
1632 * The pci device structure is provided so that architectures may make mapping
1633 * decisions on a per-device or per-bus basis.
1635 * Returns a negative error code on failure, zero on success.
1637 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1638 enum pci_mmap_state mmap_state,
1643 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
1647 __pci_mmap_set_flags(dev, vma, mmap_state);
1648 __pci_mmap_set_pgprot(dev, vma, mmap_state, write_combine);
1650 ret = remap_page_range(vma->vm_start, vma->vm_pgoff << PAGE_SHIFT,
1651 vma->vm_end - vma->vm_start, vma->vm_page_prot);
1656 /* Obsolete functions. Should be removed once the symbios driver
1660 phys_to_bus(unsigned long pa)
1662 struct pci_controller *hose;
1665 for (hose = hose_head; hose; hose = hose->next) {
1666 for (i = 0; i < 3; ++i) {
1667 if (pa >= hose->mem_resources[i].start
1668 && pa <= hose->mem_resources[i].end) {
1670 * XXX the hose->pci_mem_offset really
1671 * only applies to mem_resources[0].
1672 * We need a way to store an offset for
1673 * the others. -- paulus
1676 pa -= hose->pci_mem_offset;
1681 /* hmmm, didn't find it */
1686 pci_phys_to_bus(unsigned long pa, int busnr)
1688 struct pci_controller* hose = pci_bus_to_hose(busnr);
1691 return pa - hose->pci_mem_offset;
1695 pci_bus_to_phys(unsigned int ba, int busnr)
1697 struct pci_controller* hose = pci_bus_to_hose(busnr);
1700 return ba + hose->pci_mem_offset;
1703 /* Provide information on locations of various I/O regions in physical
1704 * memory. Do this on a per-card basis so that we choose the right
1706 * Note that the returned IO or memory base is a physical address
1710 sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1712 struct pci_controller* hose = pci_bus_to_hose(bus);
1713 long result = -EOPNOTSUPP;
1719 case IOBASE_BRIDGE_NUMBER:
1720 return (long)hose->first_busno;
1722 return (long)hose->pci_mem_offset;
1724 return (long)hose->io_base_phys;
1726 return (long)isa_io_base;
1727 case IOBASE_ISA_MEM:
1728 return (long)isa_mem_base;
1735 pci_init_resource(struct resource *res, unsigned long start, unsigned long end,
1736 int flags, char *name)
1743 res->sibling = NULL;
1748 * Null PCI config access functions, for the case when we can't
1751 #define NULL_PCI_OP(rw, size, type) \
1753 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1755 return PCIBIOS_DEVICE_NOT_FOUND; \
1758 NULL_PCI_OP(read, byte, u8 *)
1759 NULL_PCI_OP(read, word, u16 *)
1760 NULL_PCI_OP(read, dword, u32 *)
1761 NULL_PCI_OP(write, byte, u8)
1762 NULL_PCI_OP(write, word, u16)
1763 NULL_PCI_OP(write, dword, u32)
1765 static struct pci_ops null_pci_ops =
1767 null_read_config_byte,
1768 null_read_config_word,
1769 null_read_config_dword,
1770 null_write_config_byte,
1771 null_write_config_word,
1772 null_write_config_dword
1776 * These functions are used early on before PCI scanning is done
1777 * and all of the pci_dev and pci_bus structures have been created.
1779 static struct pci_dev *
1780 fake_pci_dev(struct pci_controller *hose, int busnr, int devfn)
1782 static struct pci_dev dev;
1783 static struct pci_bus bus;
1786 hose = pci_bus_to_hose(busnr);
1788 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1794 bus.ops = hose? hose->ops: &null_pci_ops;
1798 #define EARLY_PCI_OP(rw, size, type) \
1799 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1800 int devfn, int offset, type value) \
1802 return pci_##rw##_config_##size(fake_pci_dev(hose, bus, devfn), \
1806 EARLY_PCI_OP(read, byte, u8 *)
1807 EARLY_PCI_OP(read, word, u16 *)
1808 EARLY_PCI_OP(read, dword, u32 *)
1809 EARLY_PCI_OP(write, byte, u8)
1810 EARLY_PCI_OP(write, word, u16)
1811 EARLY_PCI_OP(write, dword, u32)