arch/ppc/kernel/pci_auto.c

   1 /*
   2  * arch/ppc/kernel/pci_auto.c
   3  *
   4  * PCI autoconfiguration library
   5  *
   6  * Author: Matt Porter <mporter@mvista.com>
   7  *
   8  * Copyright 2001 MontaVista Software Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 /*
  17  * The CardBus support is very preliminary.  Preallocating space is
  18  * the way to go but will require some change in card services to
  19  * make it useful.  Eventually this will ensure that we can put
  20  * multiple CB bridges behind multiple P2P bridges.  For now, at
  21  * least it ensures that we place the CB bridge BAR and assigned
  22  * initial bus numbers.  I definitely need to do something about
  23  * the lack of 16-bit I/O support. -MDP
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/init.h>
  28 #include <linux/pci.h>
  29
  30 #include <asm/pci-bridge.h>
  31
  32 #define PCIAUTO_IDE_MODE_MASK           0x05
  33
  34 #undef DEBUG
  35 //#define DEBUG
  36
  37 #ifdef DEBUG
  38 #define DBG(x...) printk(x)
  39 #else
  40 #define DBG(x...)
  41 #endif /* DEBUG */
  42
  43 static int pciauto_upper_iospc;
  44 static int pciauto_upper_memspc;
  45
  46 void __init pciauto_setup_bars(struct pci_controller *hose,
  47                 int current_bus,
  48                 int pci_devfn,
  49                 int bar_limit)
  50 {
  51         int bar_response, bar_size, bar_value;
  52         int bar, addr_mask;
  53         int * upper_limit;
  54         int found_mem64 = 0;
  55
  56         DBG("PCI Autoconfig: Found Bus %d, Device %d, Function %d\n",
  57                 current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn) );
  58
  59         for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) {
  60                 /* Tickle the BAR and get the response */
  61                 early_write_config_dword(hose,
  62                                 current_bus,
  63                                 pci_devfn,
  64                                 bar,
  65                                 0xffffffff);
  66                 early_read_config_dword(hose,
  67                                 current_bus,
  68                                 pci_devfn,
  69                                 bar,
  70                                 &bar_response);
  71
  72                 /* If BAR is not implemented go to the next BAR */
  73                 if (!bar_response)
  74                         continue;
  75
  76                 /* Check the BAR type and set our address mask */
  77                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
  78                         addr_mask = PCI_BASE_ADDRESS_IO_MASK;
  79                         upper_limit = &pciauto_upper_iospc;
  80                         DBG("PCI Autoconfig: BAR 0x%x, I/O, ", bar);
  81                 } else {
  82                         if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
  83                         PCI_BASE_ADDRESS_MEM_TYPE_64)
  84                                 found_mem64 = 1;
  85
  86                         addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
  87                         upper_limit = &pciauto_upper_memspc;
  88                         DBG("PCI Autoconfig: BAR 0x%x, Mem ", bar);
  89                 }
  90
  91                 /* Calculate requested size */
  92                 bar_size = ~(bar_response & addr_mask) + 1;
  93
  94                 /* Allocate a base address */
  95                 bar_value = (*upper_limit - bar_size) & ~(bar_size - 1);
  96
  97                 /* Write it out and update our limit */
  98                 early_write_config_dword(hose,
  99                                 current_bus,
 100                                 pci_devfn,
 101                                 bar,
 102                                 bar_value);
 103
 104                 *upper_limit = bar_value;
 105
 106                 /*
 107                  * If we are a 64-bit decoder then increment to the
 108                  * upper 32 bits of the bar and force it to locate
 109                  * in the lower 4GB of memory.
 110                  */
 111                 if (found_mem64) {
 112                         bar += 4;
 113                         early_write_config_dword(hose,
 114                                         current_bus,
 115                                         pci_devfn,
 116                                         bar,
 117                                         0x00000000);
 118                         found_mem64 = 0;
 119                 }
 120
 121                 DBG("size=0x%x, address=0x%x\n",
 122                         bar_size, bar_value);
 123         }
 124
 125 }
 126
 127 void __init pciauto_prescan_setup_bridge(struct pci_controller *hose,
 128                 int current_bus,
 129                 int pci_devfn,
 130                 int sub_bus,
 131                 int *iosave,
 132                 int *memsave)
 133 {
 134         /* Configure bus number registers */
 135         early_write_config_byte(hose,
 136                         current_bus,
 137                         pci_devfn,
 138                         PCI_PRIMARY_BUS,
 139                         current_bus);
 140         early_write_config_byte(hose,
 141                         current_bus,
 142                         pci_devfn,
 143                         PCI_SECONDARY_BUS,
 144                         sub_bus + 1);
 145         early_write_config_byte(hose,
 146                         current_bus,
 147                         pci_devfn,
 148                         PCI_SUBORDINATE_BUS,
 149                         0xff);
 150
 151         /* Round memory allocator to 1MB boundary */
 152         pciauto_upper_memspc &= ~(0x100000 - 1);
 153         *memsave = pciauto_upper_memspc;
 154
 155         /* Round I/O allocator to 4KB boundary */
 156         pciauto_upper_iospc &= ~(0x1000 - 1);
 157         *iosave = pciauto_upper_iospc;
 158
 159         /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 160         early_write_config_word(hose,
 161                         current_bus,
 162                         pci_devfn,
 163                         PCI_MEMORY_LIMIT,
 164                         ((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
 165         early_write_config_byte(hose,
 166                         current_bus,
 167                         pci_devfn,
 168                         PCI_IO_LIMIT,
 169                         ((pciauto_upper_iospc - 1) & 0x0000f000) >> 8);
 170         early_write_config_word(hose,
 171                         current_bus,
 172                         pci_devfn,
 173                         PCI_IO_LIMIT_UPPER16,
 174                         ((pciauto_upper_iospc - 1) & 0xffff0000) >> 16);
 175
 176         /* Zero upper 32 bits of prefetchable base/limit */
 177         early_write_config_dword(hose,
 178                         current_bus,
 179                         pci_devfn,
 180                         PCI_PREF_BASE_UPPER32,
 181                         0);
 182         early_write_config_dword(hose,
 183                         current_bus,
 184                         pci_devfn,
 185                         PCI_PREF_LIMIT_UPPER32,
 186                         0);
 187 }
 188
 189 void __init pciauto_postscan_setup_bridge(struct pci_controller *hose,
 190                 int current_bus,
 191                 int pci_devfn,
 192                 int sub_bus,
 193                 int *iosave,
 194                 int *memsave)
 195 {
 196         int cmdstat;
 197
 198         /* Configure bus number registers */
 199         early_write_config_byte(hose,
 200                         current_bus,
 201                         pci_devfn,
 202                         PCI_SUBORDINATE_BUS,
 203                         sub_bus);
 204
 205         /*
 206          * Round memory allocator to 1MB boundary.
 207          * If no space used, allocate minimum.
 208          */
 209         pciauto_upper_memspc &= ~(0x100000 - 1);
 210         if (*memsave == pciauto_upper_memspc)
 211                 pciauto_upper_memspc -= 0x00100000;
 212
 213         early_write_config_word(hose,
 214                         current_bus,
 215                         pci_devfn,
 216                         PCI_MEMORY_BASE,
 217                         pciauto_upper_memspc >> 16);
 218
 219         /* Allocate 1MB for pre-fretch */
 220         early_write_config_word(hose,
 221                         current_bus,
 222                         pci_devfn,
 223                         PCI_PREF_MEMORY_LIMIT,
 224                         ((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
 225
 226         pciauto_upper_memspc -= 0x100000;
 227
 228         early_write_config_word(hose,
 229                         current_bus,
 230                         pci_devfn,
 231                         PCI_PREF_MEMORY_BASE,
 232                         pciauto_upper_memspc >> 16);
 233
 234         /* Round I/O allocator to 4KB boundary */
 235         pciauto_upper_iospc &= ~(0x1000 - 1);
 236         if (*iosave == pciauto_upper_iospc)
 237                 pciauto_upper_iospc -= 0x1000;
 238
 239         early_write_config_byte(hose,
 240                         current_bus,
 241                         pci_devfn,
 242                         PCI_IO_BASE,
 243                         (pciauto_upper_iospc & 0x0000f000) >> 8);
 244         early_write_config_word(hose,
 245                         current_bus,
 246                         pci_devfn,
 247                         PCI_IO_BASE_UPPER16,
 248                         pciauto_upper_iospc >> 16);
 249
 250         /* Enable memory and I/O accesses, enable bus master */
 251         early_read_config_dword(hose,
 252                         current_bus,
 253                         pci_devfn,
 254                         PCI_COMMAND,
 255                         &cmdstat);
 256         early_write_config_dword(hose,
 257                         current_bus,
 258                         pci_devfn,
 259                         PCI_COMMAND,
 260                         cmdstat |
 261                         PCI_COMMAND_IO |
 262                         PCI_COMMAND_MEMORY |
 263                         PCI_COMMAND_MASTER);
 264 }
 265
 266 void __init pciauto_prescan_setup_cardbus_bridge(struct pci_controller *hose,
 267                 int current_bus,
 268                 int pci_devfn,
 269                 int sub_bus,
 270                 int *iosave,
 271                 int *memsave)
 272 {
 273         /* Configure bus number registers */
 274         early_write_config_byte(hose,
 275                         current_bus,
 276                         pci_devfn,
 277                         PCI_PRIMARY_BUS,
 278                         current_bus);
 279         early_write_config_byte(hose,
 280                         current_bus,
 281                         pci_devfn,
 282                         PCI_SECONDARY_BUS,
 283                         sub_bus + 1);
 284         early_write_config_byte(hose,
 285                         current_bus,
 286                         pci_devfn,
 287                         PCI_SUBORDINATE_BUS,
 288                         0xff);
 289
 290         /* Round memory allocator to 4KB boundary */
 291         pciauto_upper_memspc &= ~(0x1000 - 1);
 292         *memsave = pciauto_upper_memspc;
 293
 294         /* Round I/O allocator to 4 byte boundary */
 295         pciauto_upper_iospc &= ~(0x4 - 1);
 296         *iosave = pciauto_upper_iospc;
 297
 298         /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 299         early_write_config_dword(hose,
 300                         current_bus,
 301                         pci_devfn,
 302                         0x20,
 303                         pciauto_upper_memspc - 1);
 304         early_write_config_dword(hose,
 305                         current_bus,
 306                         pci_devfn,
 307                         0x30,
 308                         pciauto_upper_iospc - 1);
 309 }
 310
 311 void __init pciauto_postscan_setup_cardbus_bridge(struct pci_controller *hose,
 312                 int current_bus,
 313                 int pci_devfn,
 314                 int sub_bus,
 315                 int *iosave,
 316                 int *memsave)
 317 {
 318         int cmdstat;
 319
 320         /*
 321          * Configure subordinate bus number.  The PCI subsystem
 322          * bus scan will renumber buses (reserving three additional
 323          * for this PCI<->CardBus bridge for the case where a CardBus
 324          * adapter contains a P2P or CB2CB bridge.
 325          */
 326         early_write_config_byte(hose,
 327                         current_bus,
 328                         pci_devfn,
 329                         PCI_SUBORDINATE_BUS,
 330                         sub_bus);
 331
 332         /*
 333          * Reserve an additional 4MB for mem space and 16KB for
 334          * I/O space.  This should cover any additional space
 335          * requirement of unusual CardBus devices with
 336          * additional bridges that can consume more address space.
 337          *
 338          * Although pcmcia-cs currently will reprogram bridge
 339          * windows, the goal is to add an option to leave them
 340          * alone and use the bridge window ranges as the regions
 341          * that are searched for free resources upon hot-insertion
 342          * of a device.  This will allow a PCI<->CardBus bridge
 343          * configured by this routine to happily live behind a
 344          * P2P bridge in a system.
 345          */
 346         pciauto_upper_memspc -= 0x00400000;
 347         pciauto_upper_iospc -= 0x00004000;
 348
 349         /* Round memory allocator to 4KB boundary */
 350         pciauto_upper_memspc &= ~(0x1000 - 1);
 351
 352         early_write_config_dword(hose,
 353                         current_bus,
 354                         pci_devfn,
 355                         0x1c,
 356                         pciauto_upper_memspc);
 357
 358         /* Round I/O allocator to 4 byte boundary */
 359         pciauto_upper_iospc &= ~(0x4 - 1);
 360         early_write_config_dword(hose,
 361                         current_bus,
 362                         pci_devfn,
 363                         0x2c,
 364                         pciauto_upper_iospc);
 365
 366         /* Enable memory and I/O accesses, enable bus master */
 367         early_read_config_dword(hose,
 368                         current_bus,
 369                         pci_devfn,
 370                         PCI_COMMAND,
 371                         &cmdstat);
 372         early_write_config_dword(hose,
 373                         current_bus,
 374                         pci_devfn,
 375                         PCI_COMMAND,
 376                         cmdstat |
 377                         PCI_COMMAND_IO |
 378                         PCI_COMMAND_MEMORY |
 379                         PCI_COMMAND_MASTER);
 380 }
 381
 382 int __init pciauto_bus_scan(struct pci_controller *hose, int current_bus)
 383 {
 384         int sub_bus, pci_devfn, pci_class, cmdstat, found_multi = 0;
 385         unsigned short vid;
 386         unsigned char header_type;
 387
 388         /*
 389          * Fetch our I/O and memory space upper boundaries used
 390          * to allocated base addresses on this hose.
 391          */
 392         if (current_bus == hose->first_busno) {
 393                 pciauto_upper_iospc = hose->io_space.end + 1;
 394                 pciauto_upper_memspc = hose->mem_space.end + 1;
 395         }
 396
 397         sub_bus = current_bus;
 398
 399         for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
 400                 /* Skip our host bridge */
 401                 if ( (current_bus == hose->first_busno) && (pci_devfn == 0) )
 402                         continue;
 403
 404                 if (PCI_FUNC(pci_devfn) && !found_multi)
 405                         continue;
 406
 407                 /* If config space read fails from this device, move on */
 408                 if (early_read_config_byte(hose,
 409                                 current_bus,
 410                                 pci_devfn,
 411                                 PCI_HEADER_TYPE,
 412                                 &header_type))
 413                         continue;
 414
 415                 if (!PCI_FUNC(pci_devfn))
 416                         found_multi = header_type & 0x80;
 417
 418                 early_read_config_word(hose,
 419                                 current_bus,
 420                                 pci_devfn,
 421                                 PCI_VENDOR_ID,
 422                                 &vid);
 423
 424                 if (vid != 0xffff) {
 425                         early_read_config_dword(hose,
 426                                         current_bus,
 427                                         pci_devfn,
 428                                         PCI_CLASS_REVISION, &pci_class);
 429                         if ( (pci_class >> 16) == PCI_CLASS_BRIDGE_PCI ) {
 430                                 int iosave, memsave;
 431
 432                                 DBG("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_SLOT(pci_devfn));
 433                                 /* Allocate PCI I/O and/or memory space */
 434                                 pciauto_setup_bars(hose,
 435                                                 current_bus,
 436                                                 pci_devfn,
 437                                                 PCI_BASE_ADDRESS_1);
 438
 439                                 pciauto_prescan_setup_bridge(hose,
 440                                                 current_bus,
 441                                                 pci_devfn,
 442                                                 sub_bus,
 443                                                 &iosave,
 444                                                 &memsave);
 445                                 sub_bus = pciauto_bus_scan(hose, sub_bus+1);
 446                                 pciauto_postscan_setup_bridge(hose,
 447                                                 current_bus,
 448                                                 pci_devfn,
 449                                                 sub_bus,
 450                                                 &iosave,
 451                                                 &memsave);
 452                         } else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) {
 453                                 int iosave, memsave;
 454
 455                                 DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
 456                                 /* Place CardBus Socket/ExCA registers */
 457                                 pciauto_setup_bars(hose,
 458                                                 current_bus,
 459                                                 pci_devfn,
 460                                                 PCI_BASE_ADDRESS_0);
 461
 462                                 pciauto_prescan_setup_cardbus_bridge(hose,
 463                                                 current_bus,
 464                                                 pci_devfn,
 465                                                 sub_bus,
 466                                                 &iosave,
 467                                                 &memsave);
 468                                 sub_bus = pciauto_bus_scan(hose, sub_bus+1);
 469                                 pciauto_postscan_setup_cardbus_bridge(hose,
 470                                                 current_bus,
 471                                                 pci_devfn,
 472                                                 sub_bus,
 473                                                 &iosave,
 474                                                 &memsave);
 475                         } else {
 476                                 if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
 477                                         unsigned char prg_iface;
 478
 479                                         early_read_config_byte(hose,
 480                                                         current_bus,
 481                                                         pci_devfn,
 482                                                         PCI_CLASS_PROG,
 483                                                         &prg_iface);
 484                                         if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
 485                                                 DBG("PCI Autoconfig: Skipping legacy mode IDE controller\n");
 486                                                 continue;
 487                                         }
 488                                 }
 489                                 /* Allocate PCI I/O and/or memory space */
 490                                 pciauto_setup_bars(hose,
 491                                                 current_bus,
 492                                                 pci_devfn,
 493                                                 PCI_BASE_ADDRESS_5);
 494
 495                                 /*
 496                                  * Enable some standard settings
 497                                  */
 498                                 early_read_config_dword(hose,
 499                                                 current_bus,
 500                                                 pci_devfn,
 501                                                 PCI_COMMAND,
 502                                                 &cmdstat);
 503                                 early_write_config_dword(hose,
 504                                                 current_bus,
 505                                                 pci_devfn,
 506                                                 PCI_COMMAND,
 507                                                 cmdstat |
 508                                                 PCI_COMMAND_IO |
 509                                                 PCI_COMMAND_MEMORY |
 510                                                 PCI_COMMAND_MASTER);
 511                                 early_write_config_byte(hose,
 512                                                 current_bus,
 513                                                 pci_devfn,
 514                                                 PCI_LATENCY_TIMER,
 515                                                 0x80);
 516                         }
 517                 }
 518         }
 519         return sub_bus;
 520 }