arch/ppc/kernel/todc_time.c

   1 /*
   2  * arch/ppc/kernel/todc_time.c
   3  *
   4  * Time of Day Clock support for the M48T35, M48T37, M48T59, and MC146818
   5  * Real Time Clocks/Timekeepers.
   6  *
   7  * Author: Mark A. Greer
   8  *         mgreer@mvista.com
   9  *
  10  * Copyright 2001 MontaVista Software Inc.
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  */
  17 #include <linux/errno.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/time.h>
  21 #include <linux/timex.h>
  22
  23 #include <asm/machdep.h>
  24 #include <asm/io.h>
  25 #include <asm/time.h>
  26 #include <asm/todc.h>
  27
  28 /*
  29  * Depending on the hardware on your board and your board design, the
  30  * RTC/NVRAM may be accessed either directly (like normal memory) or via
  31  * address/data registers.  If your board uses the direct method, set
  32  * 'nvram_data' to the base address of your nvram and leave 'nvram_as0' and
  33  * 'nvram_as1' NULL.  If your board uses address/data regs to access nvram,
  34  * set 'nvram_as0' to the address of the lower byte, set 'nvram_as1' to the
  35  * address of the upper byte (leave NULL if using mv146818), and set
  36  * 'nvram_data' to the address of the 8-bit data register.
  37  *
  38  * You also need to set 'ppc_md.nvram_read_val' and 'ppc_md.nvram_write_val' to
  39  * the proper routines.  There are standard ones defined further down in
  40  * this file that you can use.
  41  *
  42  * There is a built in assumption that the RTC and NVRAM are accessed by the
  43  * same mechanism (i.e., ppc_md.nvram_read_val, etc works for both).
  44  *
  45  * Note: Even though the documentation for the various RTC chips say that it
  46  *       take up to a second before it starts updating once the 'R' bit is
  47  *       cleared, they always seem to update even though we bang on it many
  48  *       times a second.  This is true, except for the Dallas Semi 1746/1747
  49  *       (possibly others).  Those chips seem to have a real problem whenever
  50  *       we set the 'R' bit before reading them, they basically stop counting.
  51  *                                              --MAG
  52  */
  53
  54 extern spinlock_t       rtc_lock;
  55
  56 /*
  57  * 'todc_info' should be initialized in your *_setup.c file to
  58  * point to a fully initialized 'todc_info_t' structure.
  59  * This structure holds all the register offsets for your particular
  60  * TODC/RTC chip.
  61  * TODC_ALLOC()/TODC_INIT() will allocate and initialize this table for you.
  62  */
  63
  64 #ifdef  RTC_FREQ_SELECT
  65 #undef  RTC_FREQ_SELECT
  66 #define RTC_FREQ_SELECT         control_b       /* Register A */
  67 #endif
  68
  69 #ifdef  RTC_CONTROL
  70 #undef  RTC_CONTROL
  71 #define RTC_CONTROL             control_a       /* Register B */
  72 #endif
  73
  74 #ifdef  RTC_INTR_FLAGS
  75 #undef  RTC_INTR_FLAGS
  76 #define RTC_INTR_FLAGS          watchdog        /* Register C */
  77 #endif
  78
  79 #ifdef  RTC_VALID
  80 #undef  RTC_VALID
  81 #define RTC_VALID               interrupts      /* Register D */
  82 #endif
  83
  84 /* Access routines when RTC accessed directly (like normal memory) */
  85 u_char
  86 todc_direct_read_val(int addr)
  87 {
  88         return readb(todc_info->nvram_data + addr);
  89 }
  90
  91 void
  92 todc_direct_write_val(int addr, unsigned char val)
  93 {
  94         writeb(val, todc_info->nvram_data + addr);
  95         return;
  96 }
  97
  98 /* Access routines for accessing m48txx type chips via addr/data regs */
  99 u_char
 100 todc_m48txx_read_val(int addr)
 101 {
 102         outb(addr, todc_info->nvram_as0);
 103         outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
 104         return inb(todc_info->nvram_data);
 105 }
 106
 107 void
 108 todc_m48txx_write_val(int addr, unsigned char val)
 109 {
 110         outb(addr, todc_info->nvram_as0);
 111         outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
 112         outb(val, todc_info->nvram_data);
 113         return;
 114 }
 115
 116 /* Access routines for accessing mc146818 type chips via addr/data regs */
 117 u_char
 118 todc_mc146818_read_val(int addr)
 119 {
 120         outb(addr, todc_info->nvram_as0);
 121         return inb(todc_info->nvram_data);
 122 }
 123
 124 void
 125 todc_mc146818_write_val(int addr, unsigned char val)
 126 {
 127         outb(addr, todc_info->nvram_as0);
 128         outb(val, todc_info->nvram_data);
 129         return;
 130 }
 131
 132
 133 /*
 134  * Routines to make RTC chips with NVRAM buried behind an addr/data pair
 135  * have the NVRAM and clock regs appear at the same level.
 136  * The NVRAM will appear to start at addr 0 and the clock regs will appear
 137  * to start immediately after the NVRAM (actually, start at offset
 138  * todc_info->nvram_size).
 139  */
 140 static inline u_char
 141 todc_read_val(int addr)
 142 {
 143         u_char  val;
 144
 145         if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
 146                 if (addr < todc_info->nvram_size) { /* NVRAM */
 147                         ppc_md.nvram_write_val(todc_info->nvram_addr_reg, addr);
 148                         val = ppc_md.nvram_read_val(todc_info->nvram_data_reg);
 149                 }
 150                 else { /* Clock Reg */
 151                         addr -= todc_info->nvram_size;
 152                         val = ppc_md.nvram_read_val(addr);
 153                 }
 154         }
 155         else {
 156                 val = ppc_md.nvram_read_val(addr);
 157         }
 158
 159         return val;
 160 }
 161
 162 static inline void
 163 todc_write_val(int addr, u_char val)
 164 {
 165         if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
 166                 if (addr < todc_info->nvram_size) { /* NVRAM */
 167                         ppc_md.nvram_write_val(todc_info->nvram_addr_reg, addr);
 168                         ppc_md.nvram_write_val(todc_info->nvram_data_reg, val);
 169                 }
 170                 else { /* Clock Reg */
 171                         addr -= todc_info->nvram_size;
 172                         ppc_md.nvram_write_val(addr, val);
 173                 }
 174         }
 175         else {
 176                 ppc_md.nvram_write_val(addr, val);
 177         }
 178 }
 179
 180 /*
 181  * TODC routines
 182  *
 183  * There is some ugly stuff in that there are assumptions for the mc146818.
 184  *
 185  * Assumptions:
 186  *      - todc_info->control_a has the offset as mc146818 Register B reg
 187  *      - todc_info->control_b has the offset as mc146818 Register A reg
 188  *      - m48txx control reg's write enable or 'W' bit is same as
 189  *        mc146818 Register B 'SET' bit (i.e., 0x80)
 190  *
 191  * These assumptions were made to make the code simpler.
 192  */
 193 long __init
 194 todc_time_init(void)
 195 {
 196         static u_char   not_initialized = 1;
 197
 198         /* Make sure clocks are running */
 199         if (not_initialized) {
 200                 u_char  cntl_b;
 201
 202                 cntl_b = todc_read_val(todc_info->control_b);
 203
 204                 if (todc_info->rtc_type == TODC_TYPE_MC146818) {
 205                         if ((cntl_b & 0x70) != 0x20) {
 206                                 printk(KERN_INFO "TODC %s %s\n",
 207                                         "real-time-clock was stopped.",
 208                                         "Now starting...");
 209                                 cntl_b &= ~0x70;
 210                                 cntl_b |= 0x20;
 211                         }
 212
 213                         todc_write_val(todc_info->control_b, cntl_b);
 214                 }
 215                 else if (todc_info->rtc_type == TODC_TYPE_DS1501) {
 216                         u_char  month;
 217
 218                         todc_info->enable_read = TODC_DS1501_CNTL_B_TE;
 219                         todc_info->enable_write = TODC_DS1501_CNTL_B_TE;
 220
 221                         month = todc_read_val(todc_info->month);
 222
 223                         if ((month & 0x80) == 0x80) {
 224                                 printk(KERN_INFO "TODC %s %s\n",
 225                                         "real-time-clock was stopped.",
 226                                         "Now starting...");
 227                                 month &= ~0x80;
 228                                 todc_write_val(todc_info->month, month);
 229                         }
 230
 231                         cntl_b &= ~TODC_DS1501_CNTL_B_TE;
 232                         todc_write_val(todc_info->control_b, cntl_b);
 233                 }
 234                 else { /* must be a m48txx type */
 235                         u_char  cntl_a;
 236
 237                         todc_info->enable_read = TODC_MK48TXX_CNTL_A_R;
 238                         todc_info->enable_write = TODC_MK48TXX_CNTL_A_W;
 239
 240                         cntl_a = todc_read_val(todc_info->control_a);
 241
 242                         /* Check & clear STOP bit in control B register */
 243                         if (cntl_b & TODC_MK48TXX_DAY_CB) {
 244                                 printk(KERN_INFO "TODC %s %s\n",
 245                                         "real-time-clock was stopped.",
 246                                         "Now starting...");
 247
 248                                 cntl_a |= todc_info->enable_write;
 249                                 cntl_b &= ~TODC_MK48TXX_DAY_CB;/* Start Oscil */
 250
 251                                 todc_write_val(todc_info->control_a, cntl_a);
 252                                 todc_write_val(todc_info->control_b, cntl_b);
 253                         }
 254
 255                         /* Make sure READ & WRITE bits are cleared. */
 256                         cntl_a &= ~(todc_info->enable_write |
 257                                     todc_info->enable_read);
 258                         todc_write_val(todc_info->control_a, cntl_a);
 259                 }
 260
 261                 not_initialized = 0;
 262         }
 263
 264
 265         return 0;
 266 }
 267
 268 /*
 269  * There is some ugly stuff in that there are assumptions that for a mc146818,
 270  * the todc_info->control_a has the offset of the mc146818 Register B reg and
 271  * that the register'ss 'SET' bit is the same as the m48txx's write enable
 272  * bit in the control register of the m48txx (i.e., 0x80).
 273  *
 274  * It was done to make the code look simpler.
 275  */
 276 ulong
 277 todc_get_rtc_time(void)
 278 {
 279         uint    year, mon, day, hour, min, sec;
 280         uint    limit, i;
 281         u_char  save_control, uip;
 282
 283         spin_lock(&rtc_lock);
 284         save_control = todc_read_val(todc_info->control_a);
 285
 286         if (todc_info->rtc_type != TODC_TYPE_MC146818) {
 287                 limit = 1;
 288
 289                 switch (todc_info->rtc_type) {
 290                         case TODC_TYPE_DS1557:
 291                         case TODC_TYPE_DS1743:
 292                         case TODC_TYPE_DS1746:  /* XXXX BAD HACK -> FIX */
 293                         case TODC_TYPE_DS1747:
 294                                 break;
 295                         default:
 296                                 todc_write_val(todc_info->control_a,
 297                                        (save_control | todc_info->enable_read));
 298                 }
 299         }
 300         else {
 301                 limit = 100000000;
 302         }
 303
 304         for (i=0; i<limit; i++) {
 305                 if (todc_info->rtc_type == TODC_TYPE_MC146818) {
 306                         uip = todc_read_val(todc_info->RTC_FREQ_SELECT);
 307                 }
 308
 309                 sec = todc_read_val(todc_info->seconds) & 0x7f;
 310                 min = todc_read_val(todc_info->minutes) & 0x7f;
 311                 hour = todc_read_val(todc_info->hours) & 0x3f;
 312                 day = todc_read_val(todc_info->day_of_month) & 0x3f;
 313                 mon = todc_read_val(todc_info->month) & 0x1f;
 314                 year = todc_read_val(todc_info->year) & 0xff;
 315
 316                 if (todc_info->rtc_type == TODC_TYPE_MC146818) {
 317                         uip |= todc_read_val(todc_info->RTC_FREQ_SELECT);
 318                         if ((uip & RTC_UIP) == 0) break;
 319                 }
 320         }
 321
 322         if (todc_info->rtc_type != TODC_TYPE_MC146818) {
 323                 switch (todc_info->rtc_type) {
 324                         case TODC_TYPE_DS1557:
 325                         case TODC_TYPE_DS1743:
 326                         case TODC_TYPE_DS1746:  /* XXXX BAD HACK -> FIX */
 327                         case TODC_TYPE_DS1747:
 328                                 break;
 329                         default:
 330                                 save_control &= ~(todc_info->enable_read);
 331                                 todc_write_val(todc_info->control_a,
 332                                                        save_control);
 333                 }
 334         }
 335         spin_unlock(&rtc_lock);
 336
 337         if ((todc_info->rtc_type != TODC_TYPE_MC146818) ||
 338             ((save_control & RTC_DM_BINARY) == 0) ||
 339             RTC_ALWAYS_BCD) {
 340
 341                 BCD_TO_BIN(sec);
 342                 BCD_TO_BIN(min);
 343                 BCD_TO_BIN(hour);
 344                 BCD_TO_BIN(day);
 345                 BCD_TO_BIN(mon);
 346                 BCD_TO_BIN(year);
 347         }
 348
 349         year = year + 1900;
 350         if (year < 1970) {
 351                 year += 100;
 352         }
 353
 354         return mktime(year, mon, day, hour, min, sec);
 355 }
 356
 357 int
 358 todc_set_rtc_time(unsigned long nowtime)
 359 {
 360         struct rtc_time tm;
 361         u_char          save_control, save_freq_select;
 362
 363         spin_lock(&rtc_lock);
 364         to_tm(nowtime, &tm);
 365
 366         save_control = todc_read_val(todc_info->control_a);
 367
 368         /* Assuming MK48T59_RTC_CA_WRITE & RTC_SET are equal */
 369         todc_write_val(todc_info->control_a,
 370                                (save_control | todc_info->enable_write));
 371         save_control &= ~(todc_info->enable_write); /* in case it was set */
 372
 373         if (todc_info->rtc_type == TODC_TYPE_MC146818) {
 374                 save_freq_select = todc_read_val(todc_info->RTC_FREQ_SELECT);
 375                 todc_write_val(todc_info->RTC_FREQ_SELECT,
 376                                        save_freq_select | RTC_DIV_RESET2);
 377         }
 378
 379
 380         tm.tm_year = (tm.tm_year - 1900) % 100;
 381
 382         if ((todc_info->rtc_type != TODC_TYPE_MC146818) ||
 383             ((save_control & RTC_DM_BINARY) == 0) ||
 384             RTC_ALWAYS_BCD) {
 385
 386                 BIN_TO_BCD(tm.tm_sec);
 387                 BIN_TO_BCD(tm.tm_min);
 388                 BIN_TO_BCD(tm.tm_hour);
 389                 BIN_TO_BCD(tm.tm_mon);
 390                 BIN_TO_BCD(tm.tm_mday);
 391                 BIN_TO_BCD(tm.tm_year);
 392         }
 393
 394         todc_write_val(todc_info->seconds,      tm.tm_sec);
 395         todc_write_val(todc_info->minutes,      tm.tm_min);
 396         todc_write_val(todc_info->hours,        tm.tm_hour);
 397         todc_write_val(todc_info->month,        tm.tm_mon);
 398         todc_write_val(todc_info->day_of_month, tm.tm_mday);
 399         todc_write_val(todc_info->year,         tm.tm_year);
 400
 401         todc_write_val(todc_info->control_a, save_control);
 402
 403         if (todc_info->rtc_type == TODC_TYPE_MC146818) {
 404                 todc_write_val(todc_info->RTC_FREQ_SELECT, save_freq_select);
 405         }
 406         spin_unlock(&rtc_lock);
 407
 408         return 0;
 409 }
 410
 411 /*
 412  * Manipulates read bit to reliably read seconds at a high rate.
 413  */
 414 static unsigned char __init todc_read_timereg(int addr)
 415 {
 416         unsigned char save_control, val;
 417
 418         switch (todc_info->rtc_type) {
 419                 case TODC_TYPE_DS1557:
 420                 case TODC_TYPE_DS1746:  /* XXXX BAD HACK -> FIX */
 421                 case TODC_TYPE_DS1747:
 422                 case TODC_TYPE_MC146818:
 423                         break;
 424                 default:
 425                         save_control = todc_read_val(todc_info->control_a);
 426                         todc_write_val(todc_info->control_a,
 427                                        (save_control | todc_info->enable_read));
 428         }
 429         val = todc_read_val(addr);
 430
 431         switch (todc_info->rtc_type) {
 432                 case TODC_TYPE_DS1557:
 433                 case TODC_TYPE_DS1746:  /* XXXX BAD HACK -> FIX */
 434                 case TODC_TYPE_DS1747:
 435                 case TODC_TYPE_MC146818:
 436                         break;
 437                 default:
 438                         save_control &= ~(todc_info->enable_read);
 439                         todc_write_val(todc_info->control_a, save_control);
 440         }
 441
 442         return val;
 443 }
 444
 445 /*
 446  * This was taken from prep_setup.c
 447  * Use the NVRAM RTC to time a second to calibrate the decrementer.
 448  */
 449 void __init
 450 todc_calibrate_decr(void)
 451 {
 452         ulong   freq;
 453         ulong   tbl, tbu;
 454         long    i, loop_count;
 455         u_char  sec;
 456
 457         todc_time_init();
 458
 459         /*
 460          * Actually this is bad for precision, we should have a loop in
 461          * which we only read the seconds counter. todc_read_val writes
 462          * the address bytes on every call and this takes a lot of time.
 463          * Perhaps an nvram_wait_change method returning a time
 464          * stamp with a loop count as parameter would be the solution.
 465          */
 466         /*
 467          * Need to make sure the tbl doesn't roll over so if tbu increments
 468          * during this test, we need to do it again.
 469          */
 470         loop_count = 0;
 471
 472         sec = todc_read_timereg(todc_info->seconds) & 0x7f;
 473
 474         do {
 475                 tbu = get_tbu();
 476
 477                 for (i = 0 ; i < 10000000 ; i++) {/* may take up to 1 second */
 478                    tbl = get_tbl();
 479
 480                    if ((todc_read_timereg(todc_info->seconds) & 0x7f) != sec) {
 481                       break;
 482                    }
 483                 }
 484
 485                 sec = todc_read_timereg(todc_info->seconds) & 0x7f;
 486
 487                 for (i = 0 ; i < 10000000 ; i++) { /* Should take 1 second */
 488                    freq = get_tbl();
 489
 490                    if ((todc_read_timereg(todc_info->seconds) & 0x7f) != sec) {
 491                       break;
 492                    }
 493                 }
 494
 495                 freq -= tbl;
 496         } while ((get_tbu() != tbu) && (++loop_count < 2));
 497
 498         printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
 499                freq/1000000, freq%1000000);
 500
 501         tb_ticks_per_jiffy = freq / HZ;
 502         tb_to_us = mulhwu_scale_factor(freq, 1000000);
 503
 504         return;
 505 }