arch/ppc/platforms/chrp_pci.c

   1 /*
   2  * BK Id: SCCS/s.chrp_pci.c 1.39 01/11/03 17:52:07 benh
   3  */
   4 /*
   5  * CHRP pci routines.
   6  */
   7
   8 #include <linux/config.h>
   9 #include <linux/kernel.h>
  10 #include <linux/pci.h>
  11 #include <linux/delay.h>
  12 #include <linux/string.h>
  13 #include <linux/init.h>
  14 #include <linux/ide.h>
  15 #include <linux/bootmem.h>
  16
  17 #include <asm/io.h>
  18 #include <asm/pgtable.h>
  19 #include <asm/irq.h>
  20 #include <asm/hydra.h>
  21 #include <asm/prom.h>
  22 #include <asm/gg2.h>
  23 #include <asm/machdep.h>
  24 #include <asm/sections.h>
  25 #include <asm/pci-bridge.h>
  26 #include <asm/open_pic.h>
  27
  28 /* LongTrail */
  29 unsigned long gg2_pci_config_base __chrpdata;
  30
  31 #define pci_config_addr(dev, offset) \
  32 (gg2_pci_config_base | ((dev->bus->number)<<16) | ((dev->devfn)<<8) | (offset))
  33
  34 volatile struct Hydra *Hydra __chrpdata = NULL;
  35
  36 /* BriQ */
  37 extern int chrp_is_briq;
  38
  39 /*
  40  * The VLSI Golden Gate II has only 512K of PCI configuration space, so we
  41  * limit the bus number to 3 bits
  42  */
  43
  44 #define cfg_read(val, addr, type, op)   *val = op((type)(addr))
  45 #define cfg_write(val, addr, type, op)  op((type *)(addr), (val))
  46
  47 #define cfg_read_bad(val, size)         *val = bad_##size;
  48 #define cfg_write_bad(val, size)
  49
  50 #define bad_byte        0xff
  51 #define bad_word        0xffff
  52 #define bad_dword       0xffffffffU
  53
  54 #define GG2_PCI_OP(rw, size, type, op)                                      \
  55 int __chrp gg2_##rw##_config_##size(struct pci_dev *dev, int off, type val) \
  56 {                                                                           \
  57         if (dev->bus->number > 7) {                                         \
  58                 cfg_##rw##_bad(val, size)                                   \
  59                 return PCIBIOS_DEVICE_NOT_FOUND;                            \
  60         }                                                                   \
  61         cfg_##rw(val, pci_config_addr(dev, off), type, op);                 \
  62         return PCIBIOS_SUCCESSFUL;                                          \
  63 }
  64
  65 GG2_PCI_OP(read, byte, u8 *, in_8)
  66 GG2_PCI_OP(read, word, u16 *, in_le16)
  67 GG2_PCI_OP(read, dword, u32 *, in_le32)
  68 GG2_PCI_OP(write, byte, u8, out_8)
  69 GG2_PCI_OP(write, word, u16, out_le16)
  70 GG2_PCI_OP(write, dword, u32, out_le32)
  71
  72 static struct pci_ops gg2_pci_ops __chrpdata =
  73 {
  74         gg2_read_config_byte,
  75         gg2_read_config_word,
  76         gg2_read_config_dword,
  77         gg2_write_config_byte,
  78         gg2_write_config_word,
  79         gg2_write_config_dword
  80 };
  81
  82 /*
  83  * Access functions for PCI config space on IBM "python" host bridges.
  84  */
  85 #define PYTHON_CFA(b, d, o)     (0x80 | ((b) << 8) | ((d) << 16) \
  86                                  | (((o) & ~3) << 24))
  87
  88 #define PYTHON_PCI_OP(rw, size, type, op, mask)                              \
  89 int __chrp                                                                   \
  90 python_##rw##_config_##size(struct pci_dev *dev, int offset, type val)       \
  91 {                                                                            \
  92         struct pci_controller *hose = dev->sysdata;                          \
  93                                                                              \
  94         out_be32(hose->cfg_addr,                                             \
  95                  PYTHON_CFA(dev->bus->number, dev->devfn, offset));          \
  96         cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);           \
  97         return PCIBIOS_SUCCESSFUL;                                           \
  98 }
  99
 100 PYTHON_PCI_OP(read, byte, u8 *, in_8, 3)
 101 PYTHON_PCI_OP(read, word, u16 *, in_le16, 2)
 102 PYTHON_PCI_OP(read, dword, u32 *, in_le32, 0)
 103 PYTHON_PCI_OP(write, byte, u8, out_8, 3)
 104 PYTHON_PCI_OP(write, word, u16, out_le16, 2)
 105 PYTHON_PCI_OP(write, dword, u32, out_le32, 0)
 106
 107 static struct pci_ops python_pci_ops __chrpdata =
 108 {
 109         python_read_config_byte,
 110         python_read_config_word,
 111         python_read_config_dword,
 112         python_write_config_byte,
 113         python_write_config_word,
 114         python_write_config_dword
 115 };
 116
 117 /*
 118  * Access functions for PCI config space using RTAS calls.
 119  */
 120 #define RTAS_PCI_READ_OP(size, type, nbytes)                              \
 121 int __chrp                                                                \
 122 rtas_read_config_##size(struct pci_dev *dev, int offset, type val)        \
 123 {                                                                         \
 124         unsigned long addr = (offset & 0xff) | ((dev->devfn & 0xff) << 8) \
 125                 | ((dev->bus->number & 0xff) << 16);                      \
 126         unsigned long ret = ~0UL;                                         \
 127         int rval;                                                         \
 128                                                                           \
 129         rval = call_rtas("read-pci-config", 2, 2, &ret, addr, nbytes);    \
 130         *val = ret;                                                       \
 131         return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;        \
 132 }
 133
 134 #define RTAS_PCI_WRITE_OP(size, type, nbytes)                             \
 135 int __chrp                                                                \
 136 rtas_write_config_##size(struct pci_dev *dev, int offset, type val)       \
 137 {                                                                         \
 138         unsigned long addr = (offset & 0xff) | ((dev->devfn & 0xff) << 8) \
 139                 | ((dev->bus->number & 0xff) << 16);                      \
 140         int rval;                                                         \
 141                                                                           \
 142         rval = call_rtas("write-pci-config", 3, 1, NULL,                  \
 143                          addr, nbytes, (ulong)val);                       \
 144         return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;        \
 145 }
 146
 147 RTAS_PCI_READ_OP(byte, u8 *, 1)
 148 RTAS_PCI_READ_OP(word, u16 *, 2)
 149 RTAS_PCI_READ_OP(dword, u32 *, 4)
 150 RTAS_PCI_WRITE_OP(byte, u8, 1)
 151 RTAS_PCI_WRITE_OP(word, u16, 2)
 152 RTAS_PCI_WRITE_OP(dword, u32, 4)
 153
 154 static struct pci_ops rtas_pci_ops __chrpdata =
 155 {
 156         rtas_read_config_byte,
 157         rtas_read_config_word,
 158         rtas_read_config_dword,
 159         rtas_write_config_byte,
 160         rtas_write_config_word,
 161         rtas_write_config_dword
 162 };
 163
 164 int __init
 165 hydra_init(void)
 166 {
 167         struct device_node *np;
 168
 169         np = find_devices("mac-io");
 170         if (np == NULL || np->n_addrs == 0)
 171                 return 0;
 172         Hydra = ioremap(np->addrs[0].address, np->addrs[0].size);
 173         printk("Hydra Mac I/O at %x\n", np->addrs[0].address);
 174         printk("Hydra Feature_Control was %x",
 175                in_le32(&Hydra->Feature_Control));
 176         out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
 177                                            HYDRA_FC_SCSI_CELL_EN |
 178                                            HYDRA_FC_SCCA_ENABLE |
 179                                            HYDRA_FC_SCCB_ENABLE |
 180                                            HYDRA_FC_ARB_BYPASS |
 181                                            HYDRA_FC_MPIC_ENABLE |
 182                                            HYDRA_FC_SLOW_SCC_PCLK |
 183                                            HYDRA_FC_MPIC_IS_MASTER));
 184         printk(", now %x\n", in_le32(&Hydra->Feature_Control));
 185         return 1;
 186 }
 187
 188 void __init
 189 chrp_pcibios_fixup(void)
 190 {
 191         struct pci_dev *dev;
 192         struct device_node *np;
 193
 194         /* PCI interrupts are controlled by the OpenPIC */
 195         pci_for_each_dev(dev) {
 196                 np = pci_device_to_OF_node(dev);
 197                 if ((np != 0) && (np->n_intrs > 0) && (np->intrs[0].line != 0))
 198                         dev->irq = np->intrs[0].line;
 199                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 200         }
 201 }
 202
 203 /* W83C553 IDE Interrupt Routing Control Register */
 204 #define W83C553_IDEIRCR                0x43
 205
 206 /* SL82C105 IDE Control/Status Register */
 207 #define SL82C105_IDECSR                0x40
 208
 209 static void __init
 210 longtrail_pcibios_fixup(void)
 211 {
 212        struct pci_dev *w83c553, *sl82c105;
 213        u8 progif;
 214
 215        chrp_pcibios_fixup();
 216
 217        /*
 218         *  Open Firmware may have left the SL82C105 IDE interface in the
 219         *  W83C553 PCI/ISA bridge in legacy mode
 220         */
 221        if ((w83c553 = pci_find_device(PCI_VENDOR_ID_WINBOND,
 222                                       PCI_DEVICE_ID_WINBOND_83C553, 0)) &&
 223            (sl82c105 = pci_find_device(PCI_VENDOR_ID_WINBOND,
 224                                        PCI_DEVICE_ID_WINBOND_82C105,
 225                                        w83c553)) &&
 226            (sl82c105->class & 5) != 5) {
 227                printk("W83C553: Switching SL82C105 IDE to PCI native mode\n");
 228                /* Enable W83C553 legacy interrupt internal routing to INTC#, */
 229                /* which is connected to HYDRA_INT_EXT5 */
 230                pci_write_config_byte(w83c553, W83C553_IDEIRCR, 0x00);
 231                /* Enable SL82C105 PCI native IDE mode */
 232                pci_read_config_byte(sl82c105, PCI_CLASS_PROG, &progif);
 233                pci_write_config_byte(sl82c105, PCI_CLASS_PROG, progif | 0x05);
 234                sl82c105->class |= 0x05;
 235                /* Enable SL82C105 legacy interrupts & both channels */
 236                pci_write_config_word(sl82c105, SL82C105_IDECSR, 0x0833);
 237        }
 238 }
 239
 240 static void __init
 241 briq_pcibios_fixup(void)
 242 {
 243        struct pci_dev *w83c553, *sl82c105;
 244        u8 progif;
 245
 246        chrp_pcibios_fixup();
 247
 248        /*
 249         *  Open Firmware may have left the SL82C105 IDE interface in the
 250         *  W83C553 PCI/ISA bridge in legacy mode
 251         */
 252        if ((w83c553 = pci_find_device(PCI_VENDOR_ID_WINBOND,
 253                                       PCI_DEVICE_ID_WINBOND_83C553, 0)) &&
 254            (sl82c105 = pci_find_device(PCI_VENDOR_ID_WINBOND,
 255                                        PCI_DEVICE_ID_WINBOND_82C105,
 256                                        w83c553)) &&
 257            (sl82c105->class & 5) != 5) {
 258                printk("W83C553: Switching SL82C105 IDE to PCI native mode\n");
 259                /* Enable SL82C105 PCI native IDE mode */
 260                pci_read_config_byte(sl82c105, PCI_CLASS_PROG, &progif);
 261                pci_write_config_byte(sl82c105, PCI_CLASS_PROG, progif | 0x05);
 262                sl82c105->class |= 0x05;
 263                /* Disable SL82C105 second port */
 264                pci_write_config_word(sl82c105, SL82C105_IDECSR, 0x0003);
 265        }
 266 }
 267
 268 #define PRG_CL_RESET_VALID 0x00010000
 269
 270 static void __init
 271 setup_python(struct pci_controller *hose, struct device_node *dev)
 272 {
 273         u32 *reg, val;
 274         volatile unsigned char *cfg;
 275
 276         hose->ops = &python_pci_ops;
 277         cfg = ioremap(dev->addrs[0].address + 0xf8000, 0x20);
 278         hose->cfg_addr = (volatile unsigned int *) cfg;
 279         hose->cfg_data = cfg + 0x10;
 280
 281         /* Clear the magic go-slow bit */
 282         reg = (u32 *) ioremap(dev->addrs[0].address + 0xf6000, 0x40);
 283         val = in_be32(&reg[12]);
 284         if (val & PRG_CL_RESET_VALID) {
 285                 out_be32(&reg[12], val & ~PRG_CL_RESET_VALID);
 286                 in_be32(&reg[12]);
 287         }
 288         iounmap(reg);
 289 }
 290
 291 void __init
 292 chrp_find_bridges(void)
 293 {
 294         struct device_node *dev;
 295         int *bus_range;
 296         int len, index = -1;
 297         struct pci_controller *hose;
 298         unsigned int *dma;
 299         char *model, *machine;
 300         int is_longtrail = 0, is_mot = 0;
 301         struct device_node *root = find_path_device("/");
 302
 303         /*
 304          * The PCI host bridge nodes on some machines don't have
 305          * properties to adequately identify them, so we have to
 306          * look at what sort of machine this is as well.
 307          */
 308         machine = get_property(root, "model", NULL);
 309         if (machine != NULL) {
 310                 is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
 311                 is_mot = strncmp(machine, "MOT", 3) == 0;
 312         }
 313         for (dev = root->child; dev != NULL; dev = dev->sibling) {
 314                 if (dev->type == NULL || strcmp(dev->type, "pci") != 0)
 315                         continue;
 316                 ++index;
 317                 /* The GG2 bridge on the LongTrail doesn't have an address */
 318                 if (dev->n_addrs < 1 && !is_longtrail) {
 319                         printk(KERN_WARNING "Can't use %s: no address\n",
 320                                dev->full_name);
 321                         continue;
 322                 }
 323                 bus_range = (int *) get_property(dev, "bus-range", &len);
 324                 if (bus_range == NULL || len < 2 * sizeof(int)) {
 325                         printk(KERN_WARNING "Can't get bus-range for %s\n",
 326                                 dev->full_name);
 327                         continue;
 328                 }
 329                 if (bus_range[1] == bus_range[0])
 330                         printk(KERN_INFO "PCI bus %d", bus_range[0]);
 331                 else
 332                         printk(KERN_INFO "PCI buses %d..%d",
 333                                bus_range[0], bus_range[1]);
 334                 printk(" controlled by %s", dev->type);
 335                 if (dev->n_addrs > 0)
 336                         printk(" at %x", dev->addrs[0].address);
 337                 printk("\n");
 338
 339                 hose = pcibios_alloc_controller();
 340                 if (!hose) {
 341                         printk("Can't allocate PCI controller structure for %s\n",
 342                                 dev->full_name);
 343                         continue;
 344                 }
 345                 hose->arch_data = dev;
 346                 hose->first_busno = bus_range[0];
 347                 hose->last_busno = bus_range[1];
 348
 349                 model = get_property(dev, "model", NULL);
 350                 if (model == NULL)
 351                         model = "<none>";
 352                 if (device_is_compatible(dev, "IBM,python")) {
 353                         setup_python(hose, dev);
 354                 } else if (is_mot
 355                            || strncmp(model, "Motorola, Grackle", 17) == 0) {
 356                         setup_grackle(hose);
 357                 } else if (is_longtrail) {
 358                         hose->ops = &gg2_pci_ops;
 359                         gg2_pci_config_base = (unsigned long)
 360                                 ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
 361                 } else if (!strncmp(model, "IBM,CPC710", 10)) {
 362                         setup_indirect_pci(hose,
 363                                 dev->addrs[0].address + 0x000f8000,
 364                                 dev->addrs[0].address + 0x000f8010);
 365                         if (index == 0) {
 366                                 dma = (unsigned int *)
 367                                         get_property(dev, "system-dma-base", &len);
 368                                 if (dma && len >= sizeof(*dma)) {
 369                                         dma = (unsigned int *)(((unsigned long)dma) +
 370                                                 len - sizeof(*dma));
 371                                         pci_dram_offset = *dma;
 372                                 }
 373                         }
 374                 } else {
 375                         printk("No methods for %s (model %s), using RTAS\n",
 376                                dev->full_name, model);
 377                         hose->ops = &rtas_pci_ops;
 378                 }
 379
 380                 pci_process_bridge_OF_ranges(hose, dev, index == 0);
 381
 382                 /* check the first bridge for a property that we can
 383                    use to set pci_dram_offset */
 384                 dma = (unsigned int *)
 385                         get_property(dev, "ibm,dma-ranges", &len);
 386                 if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
 387                         pci_dram_offset = dma[2] - dma[3];
 388                         printk("pci_dram_offset = %lx\n", pci_dram_offset);
 389                 }
 390         }
 391
 392        if (is_longtrail)
 393                ppc_md.pcibios_fixup = longtrail_pcibios_fixup;
 394        else if (chrp_is_briq)
 395                ppc_md.pcibios_fixup = briq_pcibios_fixup;
 396        else
 397                ppc_md.pcibios_fixup = chrp_pcibios_fixup;
 398 }