2 * arch/ppc/platforms/ebony.c
4 * Ebony board specific routines
6 * Matt Porter <mporter@mvista.com>
8 * Copyright 2002-2003 MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/config.h>
17 #include <linux/stddef.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/reboot.h>
22 #include <linux/pci.h>
23 #include <linux/kdev_t.h>
24 #include <linux/types.h>
25 #include <linux/major.h>
26 #include <linux/blk.h>
27 #include <linux/console.h>
28 #include <linux/delay.h>
29 #include <linux/ide.h>
30 #include <linux/irq.h>
31 #include <linux/seq_file.h>
32 #include <linux/tty.h>
33 #include <linux/serial.h>
35 #include <asm/system.h>
36 #include <asm/pgtable.h>
40 #include <asm/machdep.h>
41 #include <asm/pci-bridge.h>
44 #include <asm/bootinfo.h>
45 #include <asm/ppc4xx_pic.h>
47 #include <kernel/ibm440gp_common.h>
49 extern void abort(void);
50 extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
51 extern int pckbd_getkeycode(unsigned int scancode);
52 extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
54 extern void gen550_progress(char *, unsigned short);
55 extern void gen550_init(int, struct serial_struct *);
58 * Ebony IRQ triggering/polarity settings
60 static u_char ebony_IRQ_initsenses[] __initdata = {
61 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 0: UART 0 */
62 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 1: UART 1 */
63 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 2: IIC 0 */
64 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 3: IIC 1 */
65 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 4: PCI Inb Mess */
66 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 5: PCI Cmd Wrt */
67 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 6: PCI PM */
68 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 7: PCI MSI 0 */
69 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 8: PCI MSI 1 */
70 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 9: PCI MSI 2 */
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 10: MAL TX EOB */
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 11: MAL RX EOB */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 12: DMA Chan 0 */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 13: DMA Chan 1 */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 14: DMA Chan 2 */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 15: DMA Chan 3 */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 16: Reserved */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 17: Reserved */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 18: GPT Timer 0 */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 19: GPT Timer 1 */
81 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 20: GPT Timer 2 */
82 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 21: GPT Timer 3 */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 22: GPT Timer 4 */
84 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 23: Ext Int 0 */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 24: Ext Int 1 */
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 25: Ext Int 2 */
87 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 26: Ext Int 3 */
88 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 27: Ext Int 4 */
89 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* 28: Ext Int 5 */
90 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 29: Ext Int 6 */
91 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 30: UIC1 NC Int */
92 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 31: UIC1 Crit Int */
93 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 32: MAL SERR */
94 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 33: MAL TXDE */
95 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 34: MAL RXDE */
96 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 35: ECC Unc Err */
97 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 36: ECC Corr Err */
98 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 37: Ext Bus Ctrl */
99 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 38: Ext Bus Mstr */
100 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 39: OPB->PLB */
101 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 40: PCI MSI 3 */
102 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 41: PCI MSI 4 */
103 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 42: PCI MSI 5 */
104 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 43: PCI MSI 6 */
105 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 44: PCI MSI 7 */
106 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 45: PCI MSI 8 */
107 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 46: PCI MSI 9 */
108 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 47: PCI MSI 10 */
109 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 48: PCI MSI 11 */
110 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 49: PLB Perf Mon */
111 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 50: Ext Int 7 */
112 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 51: Ext Int 8 */
113 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 52: Ext Int 9 */
114 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 53: Ext Int 10 */
115 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 54: Ext Int 11 */
116 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 55: Ext Int 12 */
117 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 56: Ser ROM Err */
118 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 57: Reserved */
119 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 58: Reserved */
120 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 59: PCI Async Err */
121 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 60: EMAC 0 */
122 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 61: EMAC 0 WOL */
123 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 62: EMAC 1 */
124 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 63: EMAC 1 WOL */
127 /* Global Variables */
128 unsigned char __res[sizeof (bd_t)];
131 ebony_calibrate_decr(void)
136 * Determine system clock speed
138 * If we are on Rev. B silicon, then use
139 * default external system clock. If we are
140 * on Rev. C silicon then errata forces us to
141 * use the internal clock.
143 switch (PVR_REV(mfspr(PVR))) {
144 case PVR_REV(PVR_440GP_RB):
145 freq = EBONY_440GP_RB_SYSCLK;
147 case PVR_REV(PVR_440GP_RC1):
149 freq = EBONY_440GP_RC_SYSCLK;
153 tb_ticks_per_jiffy = freq / HZ;
154 tb_to_us = mulhwu_scale_factor(freq, 1000000);
156 /* Set the time base to zero */
160 /* Clear any pending timer interrupts */
161 mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
163 /* Enable decrementer interrupt */
164 mtspr(SPRN_TCR, TCR_DIE);
168 ebony_show_cpuinfo(struct seq_file *m)
170 seq_printf(m, "vendor\t\t: IBM\n");
171 seq_printf(m, "machine\t\t: Ebony\n");
177 ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
179 static char pci_irq_table[][4] =
181 * PCI IDSEL/INTPIN->INTLINE
185 { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */
186 { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */
187 { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */
188 { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */
191 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
192 return PCI_IRQ_TABLE_LOOKUP;
195 #define PCIX_READW(offset) \
196 (readw((u32)pcix_reg_base+offset))
198 #define PCIX_WRITEW(value, offset) \
199 (writew(value, (u32)pcix_reg_base+offset))
201 #define PCIX_WRITEL(value, offset) \
202 (writel(value, (u32)pcix_reg_base+offset))
205 * FIXME: This is only here to "make it work". This will move
206 * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
207 * configuration library. -Matt
210 ebony_setup_pcix(void)
214 pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX0_REG_SIZE);
216 /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
217 PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
219 /* Disable all windows */
220 PCIX_WRITEL(0, PCIX0_POM0SA);
221 PCIX_WRITEL(0, PCIX0_POM1SA);
222 PCIX_WRITEL(0, PCIX0_POM2SA);
223 PCIX_WRITEL(0, PCIX0_PIM0SA);
224 PCIX_WRITEL(0, PCIX0_PIM1SA);
225 PCIX_WRITEL(0, PCIX0_PIM2SA);
227 /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
228 PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
229 PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
230 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
231 PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
232 PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
234 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
235 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
236 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
237 PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
243 ebony_setup_hose(void)
245 struct pci_controller *hose;
247 /* Configure windows on the PCI-X host bridge */
250 hose = pcibios_alloc_controller();
255 hose->first_busno = 0;
256 hose->last_busno = 0xff;
258 hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;
260 pci_init_resource(&hose->io_resource,
266 pci_init_resource(&hose->mem_resources[0],
272 hose->io_space.start = EBONY_PCI_LOWER_IO;
273 hose->io_space.end = EBONY_PCI_UPPER_IO;
274 hose->mem_space.start = EBONY_PCI_LOWER_MEM;
275 hose->mem_space.end = EBONY_PCI_UPPER_MEM;
277 (unsigned long)ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
278 hose->io_base_virt = (void *)isa_io_base;
280 setup_indirect_pci(hose,
281 EBONY_PCI_CFGA_PLB32,
282 EBONY_PCI_CFGD_PLB32);
283 hose->set_cfg_type = 1;
285 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
287 ppc_md.pci_swizzle = common_swizzle;
288 ppc_md.pci_map_irq = ebony_map_irq;
294 ebony_early_serial_map(void)
296 struct serial_struct serial_req;
298 /* Setup ioremapped serial port access */
299 memset(&serial_req, 0, sizeof(serial_req));
301 serial_req.baud_base = BASE_BAUD;
304 serial_req.flags = ASYNC_BOOT_AUTOCONF;
305 serial_req.io_type = SERIAL_IO_MEM;
306 serial_req.iomem_base = ioremap64(PPC440GP_UART0_ADDR, 8);
307 serial_req.iomem_reg_shift = 0;
309 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
310 /* Configure debug serial access */
311 gen550_init(0, &serial_req);
314 if (early_serial_setup(&serial_req) != 0) {
315 printk("Early serial init of port 0 failed\n");
318 /* Assume early_serial_setup() doesn't modify serial_req */
322 serial_req.iomem_base = ioremap64(PPC440GP_UART1_ADDR, 8);
324 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
325 /* Configure debug serial access */
326 gen550_init(1, &serial_req);
329 if (early_serial_setup(&serial_req) != 0) {
330 printk("Early serial init of port 1 failed\n");
335 ebony_setup_arch(void)
337 unsigned char * vpd_base;
338 struct ibm44x_clocks clocks;
339 bd_t *bip = (bd_t *) __res;
341 #if !defined(CONFIG_BDI_SWITCH)
343 * The Abatron BDI JTAG debugger does not tolerate others
344 * mucking with the debug registers.
346 mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
349 /* Retrieve MAC addresses */
350 vpd_base = ioremap64(EBONY_VPD_BASE, EBONY_VPD_SIZE);
351 memcpy(bip->bi_enetaddr[0],EBONY_NA0_ADDR(vpd_base),6);
352 memcpy(bip->bi_enetaddr[1],EBONY_NA1_ADDR(vpd_base),6);
355 * Determine various clocks.
356 * To be completely correct we should get SysClk
357 * from FPGA, because it can be changed by on-board switches
360 ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200);
361 bip->bi_opb_busfreq = clocks.opb;
363 /* Use IIC in standard (100 kHz) mode */
364 bip->bi_iic_fast[0] = bip->bi_iic_fast[1] = 0;
366 /* Setup TODC access */
367 TODC_INIT(TODC_TYPE_DS1743,
370 ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE),
373 /* init to some ~sane value until calibrate_delay() runs */
374 loops_per_jiffy = 50000000/HZ;
376 /* Setup PCI host bridge */
379 #ifdef CONFIG_BLK_DEV_INITRD
381 ROOT_DEV = to_kdev_t(0x0100); /* /dev/ram */
384 #ifdef CONFIG_ROOT_NFS
385 ROOT_DEV = to_kdev_t(0x00ff); /* /dev/nfs */
387 ROOT_DEV = to_kdev_t(0x0301); /* /dev/hda1 */
391 conswitchp = &dummy_con;
394 ebony_early_serial_map();
396 ibm4xxPIC_InitSenses = ebony_IRQ_initsenses;
397 ibm4xxPIC_NumInitSenses = sizeof(ebony_IRQ_initsenses);
399 /* Identify the system */
400 printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n");
404 ebony_restart(char *cmd)
411 ebony_power_off(void)
425 * Read the 440GP memory controller to get size of system memory.
427 static unsigned long __init
428 ebony_find_end_of_memory(void)
438 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B0CR);
441 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B1CR);
444 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B2CR);
447 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B3CR);
451 bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
453 if (!(bank_config & SDRAM_CONFIG_BANK_ENABLE))
455 switch (SDRAM_CONFIG_BANK_SIZE(bank_config))
457 case SDRAM_CONFIG_SIZE_8M:
458 mem_size += PPC44x_MEM_SIZE_8M;
460 case SDRAM_CONFIG_SIZE_16M:
461 mem_size += PPC44x_MEM_SIZE_16M;
463 case SDRAM_CONFIG_SIZE_32M:
464 mem_size += PPC44x_MEM_SIZE_32M;
466 case SDRAM_CONFIG_SIZE_64M:
467 mem_size += PPC44x_MEM_SIZE_64M;
469 case SDRAM_CONFIG_SIZE_128M:
470 mem_size += PPC44x_MEM_SIZE_128M;
472 case SDRAM_CONFIG_SIZE_256M:
473 mem_size += PPC44x_MEM_SIZE_256M;
475 case SDRAM_CONFIG_SIZE_512M:
476 mem_size += PPC44x_MEM_SIZE_512M;
490 for (i = 0; i < NR_IRQS; i++)
491 irq_desc[i].handler = ppc4xx_pic;
495 platform_init(unsigned long r3, unsigned long r4,
496 unsigned long r5, unsigned long r6, unsigned long r7)
498 parse_bootinfo(find_bootinfo());
500 ppc_md.setup_arch = ebony_setup_arch;
501 ppc_md.show_cpuinfo = ebony_show_cpuinfo;
502 ppc_md.init_IRQ = ebony_init_irq;
503 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
505 ppc_md.find_end_of_memory = ebony_find_end_of_memory;
507 ppc_md.restart = ebony_restart;
508 ppc_md.power_off = ebony_power_off;
509 ppc_md.halt = ebony_halt;
511 ppc_md.calibrate_decr = ebony_calibrate_decr;
512 ppc_md.time_init = todc_time_init;
513 ppc_md.set_rtc_time = todc_set_rtc_time;
514 ppc_md.get_rtc_time = todc_get_rtc_time;
516 ppc_md.nvram_read_val = todc_direct_read_val;
517 ppc_md.nvram_write_val = todc_direct_write_val;
518 #if defined(CONFIG_VT)
519 ppc_md.kbd_setkeycode = pckbd_setkeycode;
520 ppc_md.kbd_getkeycode = pckbd_getkeycode;
521 ppc_md.kbd_translate = pckbd_translate;
522 ppc_md.kbd_unexpected_up = pckbd_unexpected_up;
523 ppc_md.kbd_leds = pckbd_leds;
524 ppc_md.kbd_init_hw = 0;
527 #ifdef CONFIG_SERIAL_TEXT_DEBUG
528 ppc_md.progress = gen550_progress;
529 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
531 ppc_md.early_serial_map = ebony_early_serial_map;