2 * arch/ppc/platforms/ev64260_setup.c
4 * Board setup routines for the Marvell/Galileo EV-64260-BP Evaluation Board.
6 * Author: Mark A. Greer <mgreer@mvista.com>
8 * Copyright 2001 MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
17 * The EV-64260-BP port is the result of hard work from many people from
18 * many companies. In particular, employees of Marvell/Galileo, Mission
19 * Critical Linux, Xyterra, and MontaVista Software were heavily involved.
21 * Note: I have not been able to get *all* PCI slots to work reliably
22 * at 66 MHz. I recommend setting jumpers J15 & J16 to short pins 1&2
23 * so that 33 MHz is used. --MAG
25 #include <linux/config.h>
27 #include <linux/delay.h>
28 #include <linux/pci.h>
29 #include <linux/ide.h>
30 #include <linux/irq.h>
33 #include <linux/seq_file.h>
35 #if !defined(CONFIG_GT64260_CONSOLE)
36 #include <linux/serial.h>
39 #include <asm/bootinfo.h>
40 #include <asm/machdep.h>
41 #include <asm/gt64260.h>
42 #include <asm/ppcboot.h>
46 #include <platforms/ev64260.h>
48 #define BOARD_VENDOR "Marvell/Galileo"
49 #define BOARD_MACHINE "EV-64260-BP"
51 /* Set IDE controllers into Native mode? */
52 #define SET_PCI_IDE_NATIVE
54 ulong ev64260_mem_size = 0;
56 int ppcboot_bd_valid=0;
59 static const unsigned int cpu_7xx[16] = { /* 7xx & 74xx (but not 745x) */
60 18, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
62 static const unsigned int cpu_745x[2][16] = { /* PLL_EXT 0 & 1 */
63 { 1, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0 },
64 { 0, 30, 0, 2, 0, 26, 0, 18, 0, 22, 20, 24, 28, 32, 0, 0 }
71 ev64260_get_bus_speed(void)
75 if (ppcboot_bd_valid) {
76 speed = ppcboot_bd.bi_busfreq;
78 else switch (PVR_VER(mfspr(PVR))) {
79 case PVR_VER(PVR_750):
82 case PVR_VER(PVR_7450):
86 printk("Bus speed unknown for this processor module\n");
87 printk("Processor PVR_VER(pvr): 0x%x\n",
96 ev64260_get_cpu_speed(void)
98 unsigned long pvr, hid1, pll_ext;
100 pvr = PVR_VER(mfspr(PVR));
102 if (pvr != PVR_VER(PVR_7450)) {
103 hid1 = mfspr(HID1) >> 28;
104 return ev64260_get_bus_speed() * cpu_7xx[hid1]/2;
107 hid1 = (mfspr(HID1) & 0x0001e000) >> 13;
108 pll_ext = 0; /* No way to read; must get from schematic */
109 return ev64260_get_bus_speed() * cpu_745x[pll_ext][hid1]/2;
114 ev64260_find_end_of_memory(void)
116 if(!ppcboot_bd_valid) {
117 return gt64260_get_mem_size();
119 return ppcboot_bd.bi_memsize;
122 #ifdef SET_PCI_IDE_NATIVE
124 set_pci_native_mode(void)
128 /* Better way of doing this ??? */
129 pci_for_each_dev(dev) {
130 int class = dev->class >> 8;
132 /* enable pci native mode */
133 if (class == PCI_CLASS_STORAGE_IDE) {
136 pci_read_config_byte(dev, 0x9, ®);
138 printk("PCI: Enabling PCI IDE native mode on %s\n", dev->slot_name);
139 pci_write_config_byte(dev, 0x9, 0x8f);
141 /* let the pci code set this device up after we change it */
142 pci_setup_device(dev);
143 } else if (reg != 0x8f) {
144 printk("PCI: IDE chip in unknown mode 0x%02x on %s", reg, dev->slot_name);
152 ev64260_pci_fixups(void)
154 #ifdef SET_PCI_IDE_NATIVE
155 set_pci_native_mode();
161 * Marvell/Galileo EV-64260-BP Evaluation Board PCI interrupt routing.
162 * Note: By playing with J8 and JP1-4, you can get 2 IRQ's from the first
163 * PCI bus (in which cast, INTPIN B would be EV64260_PCI_1_IRQ).
164 * This is the most IRQs you can get from one bus with this board, though.
167 ev64260_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
169 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
171 if (hose->index == 0) {
172 static char pci_irq_table[][4] =
174 * PCI IDSEL/INTPIN->INTLINE
178 {EV64260_PCI_0_IRQ,0,0,0}, /* IDSEL 7 - PCI bus 0 */
179 {EV64260_PCI_0_IRQ,0,0,0}, /* IDSEL 8 - PCI bus 0 */
182 const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
183 return PCI_IRQ_TABLE_LOOKUP;
186 static char pci_irq_table[][4] =
188 * PCI IDSEL/INTPIN->INTLINE
192 { EV64260_PCI_1_IRQ,0,0,0}, /* IDSEL 7 - PCI bus 1 */
193 { EV64260_PCI_1_IRQ,0,0,0}, /* IDSEL 8 - PCI bus 1 */
196 const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
197 return PCI_IRQ_TABLE_LOOKUP;
202 ev64260_setup_peripherals(void)
204 gt64260_cpu_boot_set_window(EV64260_EMB_FLASH_BASE,
205 EV64260_EMB_FLASH_SIZE);
208 * Set up windows to SRAM, RTC/TODC and DUART on device module
211 gt64260_cpu_cs_set_window(0, EV64260_EXT_SRAM_BASE,
212 EV64260_EXT_SRAM_SIZE);
213 gt64260_cpu_cs_set_window(1, EV64260_TODC_BASE, EV64260_TODC_SIZE);
214 gt64260_cpu_cs_set_window(2, EV64260_UART_BASE, EV64260_UART_SIZE);
215 gt64260_cpu_cs_set_window(3, EV64260_EXT_FLASH_BASE,
216 EV64260_EXT_FLASH_SIZE);
218 TODC_INIT(TODC_TYPE_DS1501, 0, 0,
219 ioremap(EV64260_TODC_BASE, EV64260_TODC_SIZE), 8);
221 gt_clr_bits(GT64260_CPU_CONFIG, ((1<<28) | (1<<29)));
222 gt_set_bits(GT64260_CPU_CONFIG, (1<<27));
224 gt_set_bits(GT64260_PCI_0_SLAVE_PCI_DECODE_CNTL, ((1<<0) | (1<<3)));
225 gt_set_bits(GT64260_PCI_1_SLAVE_PCI_DECODE_CNTL, ((1<<0) | (1<<3)));
228 * Enabling of PCI internal-vs-external arbitration
229 * is a platform- and errata-dependent decision.
231 if( gt64260_revision == GT64260 ) {
233 gt_clr_bits(GT64260_PCI_0_ARBITER_CNTL, (1<<31));
234 gt_clr_bits(GT64260_PCI_1_ARBITER_CNTL, (1<<31));
235 } else if( gt64260_revision == GT64260A ) {
236 gt_set_bits(GT64260_PCI_0_ARBITER_CNTL, (1<<31));
237 gt_set_bits(GT64260_PCI_1_ARBITER_CNTL, (1<<31));
240 gt_set_bits(GT64260_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */
243 * The EV-64260-BP uses several Multi-Purpose Pins (MPP) on the 64260
244 * bridge as interrupt inputs (via the General Purpose Ports (GPP)
245 * register). Need to route the MPP inputs to the GPP and set the
246 * polarity correctly.
248 * In MPP Control 2 Register
249 * MPP 21 -> GPP 21 (DUART channel A intr) bits 20-23 -> 0
250 * MPP 22 -> GPP 22 (DUART channel B intr) bits 24-27 -> 0
252 gt_clr_bits(GT64260_MPP_CNTL_2, (0xf<<20) | (0xf<<24) );
255 * In MPP Control 3 Register
256 * MPP 26 -> GPP 26 (RTC INT) bits 8-11 -> 0
257 * MPP 27 -> GPP 27 (PCI 0 INTA) bits 12-15 -> 0
258 * MPP 29 -> GPP 29 (PCI 1 INTA) bits 20-23 -> 0
260 gt_clr_bits(GT64260_MPP_CNTL_3, (0xf<<8) | (0xf<<12) | (0xf<<20) );
262 #define GPP_EXTERNAL_INTERRUPTS \
263 ((1<<21) | (1<<22) | (1<<26) | (1<<27) | (1<<29))
264 /* DUART & PCI interrupts are inputs */
265 gt_clr_bits(GT64260_GPP_IO_CNTL, GPP_EXTERNAL_INTERRUPTS);
266 /* DUART & PCI interrupts are active low */
267 gt_set_bits(GT64260_GPP_LEVEL_CNTL, GPP_EXTERNAL_INTERRUPTS);
269 /* Clear any pending interrupts for these inputs and enable them. */
270 gt_write(GT64260_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS);
271 gt_set_bits(GT64260_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS);
274 * Set MPSC Multiplex RMII
275 * NOTE: ethernet driver modifies bit 0 and 1
277 gt_write(GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
283 ev64260_setup_bridge(void)
285 gt64260_bridge_info_t info;
290 GT64260_BRIDGE_INFO_DEFAULT(&info, ev64260_find_end_of_memory());
293 * Assume that GT64260_CPU_SCS_DECODE_WINDOWS,
294 * GT64260_CPU_SNOOP_WINDOWS, GT64260_PCI_SCS_WINDOWS, and
295 * GT64260_PCI_SNOOP_WINDOWS are all the equal.
296 * Also assume that GT64260_CPU_PROT_WINDOWS >=
297 * GT64260_CPU_SCS_DECODE_WINDOWS and
298 * GT64260_PCI_ACC_CNTL_WINDOWS >= GT64260_PCI_SCS_WINDOWS.
300 for (i=0; i<GT64260_CPU_SCS_DECODE_WINDOWS; i++) {
301 info.cpu_prot_options[i] = 0;
302 info.cpu_snoop_options[i] = GT64260_CPU_SNOOP_WB;
303 info.pci_0_acc_cntl_options[i] =
304 /* Breaks PCI (especially slot 4)
305 GT64260_PCI_ACC_CNTL_PREFETCHEN |
307 GT64260_PCI_ACC_CNTL_DREADEN |
308 GT64260_PCI_ACC_CNTL_RDPREFETCH |
309 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
310 GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
311 GT64260_PCI_ACC_CNTL_SWAP_NONE |
312 GT64260_PCI_ACC_CNTL_MBURST_4_WORDS;
313 info.pci_0_snoop_options[i] = GT64260_PCI_SNOOP_WB;
314 info.pci_1_acc_cntl_options[i] =
315 /* Breaks PCI (especially slot 4)
316 GT64260_PCI_ACC_CNTL_PREFETCHEN |
318 GT64260_PCI_ACC_CNTL_DREADEN |
319 GT64260_PCI_ACC_CNTL_RDPREFETCH |
320 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
321 GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
322 GT64260_PCI_ACC_CNTL_SWAP_NONE |
323 GT64260_PCI_ACC_CNTL_MBURST_4_WORDS;
324 info.pci_1_snoop_options[i] = GT64260_PCI_SNOOP_WB;
327 info.pci_0_latency = 0x8;
328 info.pci_1_latency = 0x8;
330 info.hose_a = pcibios_alloc_controller();
333 ppc_md.progress("ev64260_setup_bridge: hose_a failed", 0);
334 printk("ev64260_setup_bridge: can't set up first hose\n");
338 info.hose_b = pcibios_alloc_controller();
341 ppc_md.progress("ev64260_setup_bridge: hose_b failed", 0);
342 printk("ev64260_setup_bridge: can't set up second hose\n");
346 info.phys_base_addr = gt64260_base;
348 /* Map in the bridge's registers */
349 gt64260_base = (u32)ioremap(gt64260_base, GT64260_INTERNAL_SPACE_SIZE);
351 /* Lookup PCI host bridges */
352 if (gt64260_find_bridges(&info, ev64260_map_irq)) {
353 printk("Bridge initialization failed.\n");
354 iounmap((void *)gt64260_base);
358 * Dave Wilhardt found that bit 4 in the PCI Command registers must
359 * be set if you are using cache coherency.
361 * Note: he also said that bit 4 must be on in all PCI devices but
362 * that has not been implemented yet.
364 save_exclude = gt64260_pci_exclude_bridge;
365 gt64260_pci_exclude_bridge = FALSE;
367 early_read_config_dword(info.hose_a,
368 info.hose_a->first_busno,
373 early_write_config_dword(info.hose_a,
374 info.hose_a->first_busno,
379 early_read_config_dword(info.hose_b,
380 info.hose_b->first_busno,
385 early_write_config_dword(info.hose_b,
386 info.hose_b->first_busno,
391 gt64260_pci_exclude_bridge = save_exclude;
395 #define IS_PVR_750CX(p) ( \
396 PVR_REV((p) & 0xFFF0) == 0x0100 \
397 || PVR_REV((p) & 0xFF00) == 0x2200 \
398 || PVR_REV((p) & 0xFF00) == 0x3300 \
402 ev64260_setup_arch(void)
405 #if !defined(CONFIG_GT64260_CONSOLE)
406 struct serial_struct serial_req;
409 if ( ppc_md.progress )
410 ppc_md.progress("ev64260_setup_arch: enter", 0);
412 loops_per_jiffy = ev64260_get_cpu_speed() / HZ;
414 #ifdef CONFIG_BLK_DEV_INITRD
416 ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
419 #ifdef CONFIG_ROOT_NFS
420 ROOT_DEV = to_kdev_t(0x00FF); /* /dev/nfs pseudo device */
422 ROOT_DEV = to_kdev_t(0x0802); /* /dev/sda2 SCSI disk */
425 if ( ppc_md.progress )
426 ppc_md.progress("ev64260_setup_arch: Enabling L2 cache", 0);
428 /* Enable L2 and L3 caches (if 745x) */
433 #if 0 /* Not enabling L3 for now */ /* Add PVR_7450 too */
434 if (PVR_VER(mfspr(PVR)) == PVR_VER(PVR_7450)) {
441 if ( ppc_md.progress )
442 ppc_md.progress("ev64260_setup_arch: Initializing bridge", 0);
444 ev64260_setup_bridge(); /* set up PCI bridge(s) */
445 ev64260_setup_peripherals(); /* set up chip selects/GPP/MPP etc */
447 if ( ppc_md.progress )
448 ppc_md.progress("ev64260_setup_arch: bridge init complete", 0);
450 #ifdef CONFIG_DUMMY_CONSOLE
451 conswitchp = &dummy_con;
453 #if !defined(CONFIG_GT64260_CONSOLE)
454 memset(&serial_req, 0, sizeof(serial_req));
456 serial_req.baud_base = BASE_BAUD;
458 serial_req.irq = EV64260_UART_0_IRQ;
459 serial_req.flags = STD_COM_FLAGS;
460 serial_req.io_type = SERIAL_IO_MEM;
461 serial_req.iomem_base = ioremap(EV64260_SERIAL_0, EV64260_UART_SIZE);
462 serial_req.iomem_reg_shift = 2;
464 if (early_serial_setup(&serial_req) != 0) {
465 printk("Early serial init of port 0 failed\n");
468 /* Assume early_serial_setup() doesn't modify serial_req */
471 serial_req.irq = EV64260_UART_1_IRQ;
472 serial_req.iomem_base = ioremap(EV64260_SERIAL_1, EV64260_UART_SIZE);
475 printk(BOARD_VENDOR " " BOARD_MACHINE "\n");
476 printk("EV-64260-BP port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n");
478 if ( ppc_md.progress )
479 ppc_md.progress("ev64260_setup_arch: exit", 0);
485 ev64260_reset_board(void *addr)
489 /* disable and invalidate the L2 cache */
493 /* flush and disable L1 I/D cache */
507 /* unmap any other random cs's that might overlap with bootcs */
508 gt64260_cpu_cs_set_window(0,0,0);
509 gt64260_cpu_cs_set_window(1,0,0);
510 gt64260_cpu_cs_set_window(2,0,0);
511 gt64260_cpu_cs_set_window(3,0,0);
513 /* map bootrom back in to gt @ reset defaults */
514 gt64260_cpu_boot_set_window(0xff800000, 8*1024*1024);
516 /* move gt reg base back to default, setup default pci0 swapping
518 gt_write(GT64260_INTERNAL_SPACE_DECODE,
519 (1<<24) | GT64260_INTERNAL_SPACE_DEFAULT_ADDR>>20);
521 /* NOTE: FROM NOW ON no more GT_REGS accesses.. 0x1 is not mapped
522 * via BAT or MMU, and MSR IR/DR is ON */
524 /* BROKEN... IR/DR is still on !! won't work!! */
525 /* Set exception prefix high - to the firmware */
526 _nmask_and_or_msr(0, MSR_IP);
528 out_8((u_char *)EV64260_BOARD_MODRST_REG, 0x01);
530 /* SRR0 has system reset vector, SRR1 has default MSR value */
531 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
532 /* NOTE: assumes reset vector is at 0xfff00100 */
544 ev64260_restart(char *cmd)
546 volatile ulong i = 10000000;
548 ev64260_reset_board((void *)0xfff00100);
551 panic("restart failed\n");
563 ev64260_power_off(void)
570 ev64260_show_cpuinfo(struct seq_file *m)
575 seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
576 seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
578 seq_printf(m, "PVID\t\t: 0x%x, vendor: %s\n",
580 ((pvid & (1<<15)) || IS_PVR_750CX(pvid))
581 ? "IBM" : "Motorola" );
582 seq_printf(m, "cpu MHz\t\t: %d\n", ev64260_get_cpu_speed()/1000/1000);
583 seq_printf(m, "bus MHz\t\t: %d\n", ev64260_get_bus_speed()/1000/1000);
588 /* DS1501 RTC has too much variation to use RTC for calibration */
590 ev64260_calibrate_decr(void)
594 freq = ev64260_get_bus_speed()/4;
596 printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
597 freq/1000000, freq%1000000);
599 tb_ticks_per_jiffy = freq / HZ;
600 tb_to_us = mulhwu_scale_factor(freq, 1000000);
605 #ifdef CONFIG_USE_PPCBOOT
606 static void parse_ppcbootinfo(unsigned long r3,
607 unsigned long r4, unsigned long r5,
608 unsigned long r6, unsigned long r7)
611 char *cmdline_start=NULL;
615 if((r3 & 0xf0000000) == 0) r3 += KERNELBASE;
616 if((r3 & 0xf0000000) == KERNELBASE) {
619 /* hack for ppcboot loaders that report freqs in Mhz */
620 if(bd->bi_intfreq<1000000) bd->bi_intfreq*=1000000;
621 if(bd->bi_busfreq<1000000) bd->bi_busfreq*=1000000;
623 memcpy(&ppcboot_bd,bd,sizeof(ppcboot_bd));
628 #ifdef CONFIG_BLK_DEV_INITRD
629 if(r4 && r5 && r5>r4) {
630 if((r4 & 0xf0000000) == 0) r4 += KERNELBASE;
631 if((r5 & 0xf0000000) == 0) r5 += KERNELBASE;
632 if((r4 & 0xf0000000) == KERNELBASE) {
635 initrd_below_start_ok = 1;
638 #endif /* CONFIG_BLK_DEV_INITRD */
640 if(r6 && r7 && r7>r6) {
641 if((r6 & 0xf0000000) == 0) r6 += KERNELBASE;
642 if((r7 & 0xf0000000) == 0) r7 += KERNELBASE;
643 if((r6 & 0xf0000000) == KERNELBASE) {
644 cmdline_start=(void *)r6;
646 strncpy(cmd_line,cmdline_start,cmdline_len);
650 if(ppcboot_bd_valid) {
651 printk("found bd_t @%p\n", bd);
652 printk("memstart=%08lx\n", bd->bi_memstart);
653 printk("memsize=%08lx\n", bd->bi_memsize);
654 printk("enetaddr=%02x%02x%02x%02x%02x%02x\n",
662 printk("intfreq=%ld\n", bd->bi_intfreq);
663 printk("busfreq=%ld\n", bd->bi_busfreq);
664 printk("baudrate=%ld\n", bd->bi_baudrate);
667 #ifdef CONFIG_BLK_DEV_INITRD
669 printk("found initrd @%lx-%lx\n", initrd_start, initrd_end);
671 #endif /* CONFIG_BLK_DEV_INITRD */
673 if(cmdline_start && cmdline_len) {
674 printk("found cmdline: '%s'\n", cmd_line);
677 #endif /* USE PPC_BOOT */
679 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
681 ev64260_ide_check_region(ide_ioreg_t from, unsigned int extent)
683 return check_region(from, extent);
687 ev64260_ide_request_region(ide_ioreg_t from,
691 request_region(from, extent, name);
696 ev64260_ide_release_region(ide_ioreg_t from,
699 release_region(from, extent);
704 ev64260_ide_pci_init_hwif_ports(hw_regs_t *hw, ide_ioreg_t data_port,
705 ide_ioreg_t ctrl_port, int *irq)
711 //printk("regs %d to %d @ 0x%x\n", IDE_DATA_OFFSET, IDE_STATUS_OFFSET, data_port);
712 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
713 hw->io_ports[i] = data_port;
717 //printk("ctrl %d @ 0x%x\n", IDE_CONTROL_OFFSET, ctrl_port);
718 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
721 pci_for_each_dev(dev) {
722 if (((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) ||
723 ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)) {
736 #if defined(CONFIG_SERIAL_TEXT_DEBUG)
737 #if !defined(CONFIG_GT64260_CONSOLE)
738 #include <linux/serialP.h>
739 #include <linux/serial_reg.h>
740 #include <asm/serial.h>
742 static struct serial_state rs_table[RS_TABLE_SIZE] = {
743 SERIAL_PORT_DFNS /* Defined in <asm/serial.h> */
747 ev64260_16550_progress(char *s, unsigned short hex)
750 volatile unsigned long com_port;
753 com_port = rs_table[0].port;
754 shift = rs_table[0].iomem_reg_shift;
756 while ((c = *s++) != 0) {
757 while ((*((volatile unsigned char *)com_port +
758 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
760 *(volatile unsigned char *)com_port = c;
763 while ((*((volatile unsigned char *)com_port +
764 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
766 *(volatile unsigned char *)com_port = '\r';
770 /* Move to next line on */
771 while ((*((volatile unsigned char *)com_port +
772 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
774 *(volatile unsigned char *)com_port = '\n';
775 while ((*((volatile unsigned char *)com_port +
776 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
778 *(volatile unsigned char *)com_port = '\r';
782 #endif /* !CONFIG_GT64260_CONSOLE */
783 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
785 #if !defined(CONFIG_USE_PPCBOOT) || defined(CONFIG_SERIAL_TEXT_DEBUG)
787 * Set BAT 3 to map 0xf0000000 to end of physical memory space.
789 static __inline__ void
790 ev64260_set_bat(void)
792 unsigned long bat3u, bat3l;
793 static int mapping_set = 0;
799 "ori %1,%0,0x002a\n\t"
800 "ori %0,%0,0x1ffe\n\t"
805 : "=r" (bat3u), "=r" (bat3l));
814 #ifdef CONFIG_SERIAL_TEXT_DEBUG
818 io_block_mapping(0xf8000000, 0xf8000000, 0x08000000, _PAGE_IO);
823 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
824 unsigned long r6, unsigned long r7)
826 extern char cmd_line[];
829 #ifdef CONFIG_BLK_DEV_INITRD
830 initrd_start=initrd_end=0;
831 initrd_below_start_ok=0;
832 #endif /* CONFIG_BLK_DEV_INITRD */
835 memset(&ppcboot_bd,0,sizeof(ppcboot_bd));
837 #ifdef CONFIG_USE_PPCBOOT
838 parse_ppcbootinfo(r3, r4, r5, r6, r7);
840 parse_bootinfo(find_bootinfo());
844 isa_io_base = GT64260_PCI_0_IO_START_PROC;
845 pci_dram_offset = GT64260_PCI_0_MEM_START_PROC;
847 ppc_md.setup_arch = ev64260_setup_arch;
848 ppc_md.show_cpuinfo = ev64260_show_cpuinfo;
849 ppc_md.irq_cannonicalize = NULL;
850 ppc_md.init_IRQ = gt64260_init_irq;
851 ppc_md.get_irq = gt64260_get_irq;
853 ppc_md.pcibios_fixup = ev64260_pci_fixups;
855 ppc_md.restart = ev64260_restart;
856 ppc_md.power_off = ev64260_power_off;
857 ppc_md.halt = ev64260_halt;
859 ppc_md.find_end_of_memory = ev64260_find_end_of_memory;
861 #ifdef CONFIG_SERIAL_TEXT_DEBUG
862 ppc_md.setup_io_mappings = ev64260_map_io;
867 ppc_md.time_init = todc_time_init;
868 ppc_md.set_rtc_time = todc_set_rtc_time;
869 ppc_md.get_rtc_time = todc_get_rtc_time;
871 ppc_md.nvram_read_val = todc_direct_read_val;
872 ppc_md.nvram_write_val = todc_direct_write_val;
874 ppc_md.calibrate_decr = ev64260_calibrate_decr;
875 #ifdef CONFIG_GT64260_NEW_BASE
876 gt64260_base = CONFIG_GT64260_NEW_REG_BASE;
878 gt64260_base = CONFIG_GT64260_ORIG_REG_BASE;
881 #if !defined(CONFIG_USE_PPCBOOT) || defined(CONFIG_SERIAL_TEXT_DEBUG)
883 * If we're not using ppcboot as the firmware, then we need to map
884 * in the mem ctlr's regs so we can determine the amount of memory
886 * Also, if progress msgs are being used, have to map in either the
887 * UART's regs or the MPSC's regs.
888 * All of this is done by ev64260_set_bat() and ev64260_map_io().
890 /* Sanity check so ev64260_set_bat(), etc. work */
891 if (gt64260_base < 0xf8000000) {
892 printk("Bridge's Base Address (0x%x) should be >= 0xf8000000\n",
898 #ifdef CONFIG_SERIAL_TEXT_DEBUG
899 #ifdef CONFIG_GT64260_CONSOLE
900 ppc_md.progress = gt64260_mpsc_progress; /* embedded UART */
902 ppc_md.progress = ev64260_16550_progress; /* Dev module DUART */
904 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
906 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
907 ppc_ide_md.ide_check_region = ev64260_ide_check_region;
908 ppc_ide_md.ide_request_region = ev64260_ide_request_region;
909 ppc_ide_md.ide_release_region = ev64260_ide_release_region;
910 ppc_ide_md.ide_init_hwif = ev64260_ide_pci_init_hwif_ports;