arch/ppc/platforms/k2_pci.c

   1 /*
   2  * arch/ppc/platforms/k2_pci.c
   3  *
   4  * PCI support for SBS K2
   5  *
   6  * Author: Matt Porter <mporter@mvista.com>
   7  *
   8  * Copyright 2001 MontaVista Software Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/slab.h>
  20
  21 #include <asm/byteorder.h>
  22 #include <asm/io.h>
  23 #include <asm/uaccess.h>
  24 #include <asm/machdep.h>
  25 #include <asm/pci-bridge.h>
  26
  27 #include "cpc710.h"
  28 #include "k2.h"
  29
  30 #undef DEBUG
  31 #ifdef DEBUG
  32 #define DBG(x...) printk(x)
  33 #else
  34 #define DBG(x...)
  35 #endif /* DEBUG */
  36
  37 static inline int __init
  38 k2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  39 {
  40         struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
  41         /*
  42          * Check our hose index.  If we are zero then we are on the
  43          * local PCI hose, otherwise we are on the cPCI hose.
  44          */
  45         if (!hose->index)
  46         {
  47                 static char pci_irq_table[][4] =
  48                         /*
  49                          *      PCI IDSEL/INTPIN->INTLINE
  50                          *      A       B       C       D
  51                          */
  52                 {
  53                         {1,     0,      0,      0},     /* Ethernet */
  54                         {5,     5,      5,      5},     /* PMC Site 1 */
  55                         {6,     6,      6,      6},     /* PMC Site 2 */
  56                         {0,     0,      0,      0},     /* unused */
  57                         {0,     0,      0,      0},     /* unused */
  58                         {0,     0,      0,      0},     /* PCI-ISA Bridge */
  59                         {0,     0,      0,      0},     /* unused */
  60                         {0,     0,      0,      0},     /* unused */
  61                         {0,     0,      0,      0},     /* unused */
  62                         {0,     0,      0,      0},     /* unused */
  63                         {0,     0,      0,      0},     /* unused */
  64                         {0,     0,      0,      0},     /* unused */
  65                         {0,     0,      0,      0},     /* unused */
  66                         {0,     0,      0,      0},     /* unused */
  67                         {15,    0,      0,      0},     /* M5229 IDE */
  68                 };
  69                 const long min_idsel = 3, max_idsel = 17, irqs_per_slot = 4;
  70                 return PCI_IRQ_TABLE_LOOKUP;
  71         }
  72         else
  73         {
  74                 static char pci_irq_table[][4] =
  75                 /*
  76                  *      PCI IDSEL/INTPIN->INTLINE
  77                  *      A       B       C       D
  78                  */
  79                 {
  80                         {10,    11,     12,     9},     /* cPCI slot 8 */
  81                         {11,    12,     9,      10},    /* cPCI slot 7 */
  82                         {12,    9,      10,     11},    /* cPCI slot 6 */
  83                         {9,     10,     11,     12},    /* cPCI slot 5 */
  84                         {10,    11,     12,     9},     /* cPCI slot 4 */
  85                         {11,    12,     9,      10},    /* cPCI slot 3 */
  86                         {12,    9,      10,     11},    /* cPCI slot 2 */
  87                 };
  88                 const long min_idsel = 15, max_idsel = 21, irqs_per_slot = 4;
  89                 return PCI_IRQ_TABLE_LOOKUP;
  90         }
  91 }
  92
  93 void k2_pcibios_fixup(void)
  94 {
  95 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
  96         struct pci_dev *ide_dev;
  97
  98         /*
  99          * Enable DMA support on hdc
 100          */
 101         ide_dev = pci_find_device(PCI_VENDOR_ID_AL,
 102                         PCI_DEVICE_ID_AL_M5229,
 103                         NULL);
 104
 105         if (ide_dev) {
 106
 107                 unsigned long ide_dma_base;
 108
 109                 ide_dma_base = pci_resource_start(ide_dev, 4);
 110                 outb(0x00, ide_dma_base+0x2);
 111                 outb(0x20, ide_dma_base+0xa);
 112         }
 113 #endif
 114 }
 115
 116 void k2_setup_hoses(void)
 117 {
 118         struct pci_controller *hose_a, *hose_b;
 119
 120         /*
 121          * Reconfigure CPC710 memory map so
 122          * we have some more PCI memory space.
 123          */
 124
 125         /* Set FPHB mode */
 126         __raw_writel(0x808000e0, PGCHP);        /* Set FPHB mode */
 127
 128         /* PCI32 mappings */
 129         __raw_writel(0x00000000, K2_PCI32_BAR+PIBAR);   /* PCI I/O base */
 130         __raw_writel(0x00000000, K2_PCI32_BAR+PMBAR);   /* PCI Mem base */
 131         __raw_writel(0xf0000000, K2_PCI32_BAR+MSIZE);   /* 256MB */
 132         __raw_writel(0xfff00000, K2_PCI32_BAR+IOSIZE);  /* 1MB */
 133         __raw_writel(0xc0000000, K2_PCI32_BAR+SMBAR);   /* Base@0xc0000000 */
 134         __raw_writel(0x80000000, K2_PCI32_BAR+SIBAR);   /* Base@0x80000000 */
 135         __raw_writel(0x000000c0, K2_PCI32_BAR+PSSIZE);  /* 1GB space */
 136         __raw_writel(0x000000c0, K2_PCI32_BAR+PPSIZE);  /* 1GB space */
 137         __raw_writel(0x00000000, K2_PCI32_BAR+BARPS);   /* Base@0x00000000 */
 138         __raw_writel(0x00000000, K2_PCI32_BAR+BARPP);   /* Base@0x00000000 */
 139         __raw_writel(0x00000080, K2_PCI32_BAR+PSBAR);   /* Base@0x80 */
 140         __raw_writel(0x00000000, K2_PCI32_BAR+PPBAR);
 141
 142         __raw_writel(0xc0000000, K2_PCI32_BAR+BPMDLK);
 143         __raw_writel(0xd0000000, K2_PCI32_BAR+TPMDLK);
 144         __raw_writel(0x80000000, K2_PCI32_BAR+BIODLK);
 145         __raw_writel(0x80100000, K2_PCI32_BAR+TIODLK);
 146         __raw_writel(0xe0008000, K2_PCI32_BAR+DLKCTRL);
 147         __raw_writel(0xffffffff, K2_PCI32_BAR+DLKDEV);
 148
 149         /* PCI64 mappings */
 150         __raw_writel(0x00100000, K2_PCI64_BAR+PIBAR);   /* PCI I/O base */
 151         __raw_writel(0x10000000, K2_PCI64_BAR+PMBAR);   /* PCI Mem base */
 152         __raw_writel(0xf0000000, K2_PCI64_BAR+MSIZE);   /* 256MB */
 153         __raw_writel(0xfff00000, K2_PCI64_BAR+IOSIZE);  /* 1MB */
 154         __raw_writel(0xd0000000, K2_PCI64_BAR+SMBAR);   /* Base@0xd0000000 */
 155         __raw_writel(0x80100000, K2_PCI64_BAR+SIBAR);   /* Base@0x80100000 */
 156         __raw_writel(0x000000c0, K2_PCI64_BAR+PSSIZE);  /* 1GB space */
 157         __raw_writel(0x000000c0, K2_PCI64_BAR+PPSIZE);  /* 1GB space */
 158         __raw_writel(0x00000000, K2_PCI64_BAR+BARPS);   /* Base@0x00000000 */
 159         __raw_writel(0x00000000, K2_PCI64_BAR+BARPP);   /* Base@0x00000000 */
 160
 161         /* Setup PCI32 hose */
 162         hose_a = pcibios_alloc_controller();
 163         if (!hose_a)
 164                 return;
 165
 166         hose_a->first_busno = 0;
 167         hose_a->last_busno = 0xff;
 168         hose_a->pci_mem_offset = K2_PCI32_MEM_BASE;
 169
 170         pci_init_resource(&hose_a->io_resource,
 171                         K2_PCI32_LOWER_IO,
 172                         K2_PCI32_UPPER_IO,
 173                         IORESOURCE_IO,
 174                         "PCI32 host bridge");
 175
 176         pci_init_resource(&hose_a->mem_resources[0],
 177                         K2_PCI32_LOWER_MEM + K2_PCI32_MEM_BASE,
 178                         K2_PCI32_UPPER_MEM + K2_PCI32_MEM_BASE,
 179                         IORESOURCE_MEM,
 180                         "PCI32 host bridge");
 181
 182         hose_a->io_space.start = K2_PCI32_LOWER_IO;
 183         hose_a->io_space.end = K2_PCI32_UPPER_IO;
 184         hose_a->mem_space.start = K2_PCI32_LOWER_MEM;
 185         hose_a->mem_space.end = K2_PCI32_UPPER_MEM;
 186         hose_a->io_base_virt = (void *)K2_ISA_IO_BASE;
 187
 188         setup_indirect_pci(hose_a, K2_PCI32_CONFIG_ADDR, K2_PCI32_CONFIG_DATA);
 189
 190         /* Initialize PCI32 bus registers */
 191         early_write_config_byte(hose_a,
 192                         hose_a->first_busno,
 193                         PCI_DEVFN(0, 0),
 194                         CPC710_BUS_NUMBER,
 195                         hose_a->first_busno);
 196
 197         early_write_config_byte(hose_a,
 198                         hose_a->first_busno,
 199                         PCI_DEVFN(0, 0),
 200                         CPC710_SUB_BUS_NUMBER,
 201                         hose_a->last_busno);
 202
 203         /* Enable PCI interrupt polling */
 204         early_write_config_byte(hose_a,
 205                         hose_a->first_busno,
 206                         PCI_DEVFN(8, 0),
 207                         0x45,
 208                         0x80);
 209
 210         /* Route polled PCI interrupts */
 211         early_write_config_byte(hose_a,
 212                         hose_a->first_busno,
 213                         PCI_DEVFN(8, 0),
 214                         0x48,
 215                         0x58);
 216
 217         early_write_config_byte(hose_a,
 218                         hose_a->first_busno,
 219                         PCI_DEVFN(8, 0),
 220                         0x49,
 221                         0x07);
 222
 223         early_write_config_byte(hose_a,
 224                         hose_a->first_busno,
 225                         PCI_DEVFN(8, 0),
 226                         0x4a,
 227                         0x31);
 228
 229         early_write_config_byte(hose_a,
 230                         hose_a->first_busno,
 231                         PCI_DEVFN(8, 0),
 232                         0x4b,
 233                         0xb9);
 234
 235         /* route secondary IDE channel interrupt to IRQ 15 */
 236         early_write_config_byte(hose_a,
 237                         hose_a->first_busno,
 238                         PCI_DEVFN(8, 0),
 239                         0x75,
 240                         0x0f);
 241
 242         /* enable IDE controller IDSEL */
 243         early_write_config_byte(hose_a,
 244                         hose_a->first_busno,
 245                         PCI_DEVFN(8, 0),
 246                         0x58,
 247                         0x48);
 248
 249         /* Enable IDE function */
 250         early_write_config_byte(hose_a,
 251                         hose_a->first_busno,
 252                         PCI_DEVFN(17, 0),
 253                         0x50,
 254                         0x03);
 255
 256         /* Set M5229 IDE controller to native mode */
 257         early_write_config_byte(hose_a,
 258                         hose_a->first_busno,
 259                         PCI_DEVFN(17, 0),
 260                         PCI_CLASS_PROG,
 261                         0xdf);
 262
 263         hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
 264
 265         /* Write out correct max subordinate bus number for hose A */
 266         early_write_config_byte(hose_a,
 267                         hose_a->first_busno,
 268                         PCI_DEVFN(0, 0),
 269                         CPC710_SUB_BUS_NUMBER,
 270                         hose_a->last_busno);
 271
 272         /* Only setup PCI64 hose if we are in the system slot */
 273         if (!(readb(K2_MISC_REG) & K2_SYS_SLOT_MASK))
 274         {
 275                 /* Setup PCI64 hose */
 276                 hose_b = pcibios_alloc_controller();
 277                 if (!hose_b)
 278                         return;
 279
 280                 hose_b->first_busno = hose_a->last_busno + 1;
 281                 hose_b->last_busno = 0xff;
 282
 283                 /* Reminder: quit changing the following, it is correct. */
 284                 hose_b->pci_mem_offset = K2_PCI32_MEM_BASE;
 285
 286                 pci_init_resource(&hose_b->io_resource,
 287                                 K2_PCI64_LOWER_IO,
 288                                 K2_PCI64_UPPER_IO,
 289                                 IORESOURCE_IO,
 290                                 "PCI64 host bridge");
 291
 292                 pci_init_resource(&hose_b->mem_resources[0],
 293                                 K2_PCI64_LOWER_MEM + K2_PCI32_MEM_BASE,
 294                                 K2_PCI64_UPPER_MEM + K2_PCI32_MEM_BASE,
 295                                 IORESOURCE_MEM,
 296                                 "PCI64 host bridge");
 297
 298                 hose_b->io_space.start = K2_PCI64_LOWER_IO;
 299                 hose_b->io_space.end = K2_PCI64_UPPER_IO;
 300                 hose_b->mem_space.start = K2_PCI64_LOWER_MEM;
 301                 hose_b->mem_space.end = K2_PCI64_UPPER_MEM;
 302                 hose_b->io_base_virt = (void *)K2_ISA_IO_BASE;
 303
 304                 setup_indirect_pci(hose_b,
 305                                 K2_PCI64_CONFIG_ADDR,
 306                                 K2_PCI64_CONFIG_DATA);
 307
 308                 /* Initialize PCI64 bus registers */
 309                 early_write_config_byte(hose_b,
 310                                 0,
 311                                 PCI_DEVFN(0, 0),
 312                                 CPC710_SUB_BUS_NUMBER,
 313                                 0xff);
 314
 315                 early_write_config_byte(hose_b,
 316                                 0,
 317                                 PCI_DEVFN(0, 0),
 318                                 CPC710_BUS_NUMBER,
 319                                 hose_b->first_busno);
 320
 321                 hose_b->last_busno = pciauto_bus_scan(hose_b,
 322                                 hose_b->first_busno);
 323
 324                 /* Write out correct max subordinate bus number for hose B */
 325                 early_write_config_byte(hose_b,
 326                                 hose_b->first_busno,
 327                                 PCI_DEVFN(0, 0),
 328                                 CPC710_SUB_BUS_NUMBER,
 329                                 hose_b->last_busno);
 330
 331                 /* Configure PCI64 PSBAR */
 332                 early_write_config_dword(hose_b,
 333                                 hose_b->first_busno,
 334                                 PCI_DEVFN(0, 0),
 335                                 PCI_BASE_ADDRESS_0,
 336                                 K2_PCI64_SYS_MEM_BASE);
 337         }
 338
 339         /* Configure i8259 level/edge settings */
 340         outb(0x62, 0x4d0);
 341         outb(0xde, 0x4d1);
 342
 343 #ifdef CONFIG_CPC710_DATA_GATHERING
 344         {
 345                 unsigned int tmp;
 346                 tmp = __raw_readl(ABCNTL);
 347                 /* Enable data gathering on both PCI interfaces */
 348                 __raw_writel(tmp | 0x05000000, ABCNTL);
 349         }
 350 #endif
 351
 352         ppc_md.pcibios_fixup = k2_pcibios_fixup;
 353         ppc_md.pci_swizzle = common_swizzle;
 354         ppc_md.pci_map_irq = k2_map_irq;
 355 }