arch/ppc/platforms/mcpn765_setup.c

   1 /*
   2  * arch/ppc/platforms/mcpn765_setup.c
   3  *
   4  * Board setup routines for the Motorola MCG MCPN765 cPCI Board.
   5  *
   6  * Author: Mark A. Greer
   7  *         mgreer@mvista.com
   8  *
   9  * Copyright 2001 MontaVista Software Inc.
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  */
  16
  17 /*
  18  * This file adds support for the Motorola MCG MCPN765.
  19  */
  20 #include <linux/config.h>
  21 #include <linux/stddef.h>
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/errno.h>
  25 #include <linux/reboot.h>
  26 #include <linux/pci.h>
  27 #include <linux/kdev_t.h>
  28 #include <linux/major.h>
  29 #include <linux/blk.h>
  30 #include <linux/console.h>
  31 #include <linux/delay.h>
  32 #include <linux/irq.h>
  33 #include <linux/ide.h>
  34 #include <linux/irq.h>
  35 #include <linux/seq_file.h>
  36
  37 #include <asm/system.h>
  38 #include <asm/pgtable.h>
  39 #include <asm/page.h>
  40 #include <asm/time.h>
  41 #include <asm/dma.h>
  42 #include <asm/io.h>
  43 #include <asm/machdep.h>
  44 #include <asm/prom.h>
  45 #include <asm/smp.h>
  46 #include <asm/open_pic.h>
  47 #include <asm/i8259.h>
  48 #include <asm/todc.h>
  49 #include <asm/pci-bridge.h>
  50 #include <asm/bootinfo.h>
  51 #include <asm/pplus.h>
  52
  53 #include "mcpn765.h"
  54
  55 static u_char mcpn765_openpic_initsenses[] __initdata = {
  56         (IRQ_SENSE_EDGE  | IRQ_POLARITY_POSITIVE),      /* 16: i8259 cascade */
  57         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 17: COM1,2,3,4 */
  58         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 18: Enet 1 (front) */
  59         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 19: HAWK WDT XXXX */
  60         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 20: 21554 bridge */
  61         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 21: cPCI INTA# */
  62         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 22: cPCI INTB# */
  63         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 23: cPCI INTC# */
  64         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 24: cPCI INTD# */
  65         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 25: PMC1 INTA#, PMC2 INTB# */
  66         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 26: PMC1 INTB#, PMC2 INTC# */
  67         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 27: PMC1 INTC#, PMC2 INTD# */
  68         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 28: PMC1 INTD#, PMC2 INTA# */
  69         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 29: Enet 2 (connected to J3) */
  70         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 30: Abort Switch */
  71         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 31: RTC Alarm */
  72 };
  73
  74 extern void mcpn765_set_VIA_IDE_native(void);
  75
  76 extern u_int openpic_irq(void);
  77 extern char cmd_line[];
  78
  79 int use_of_interrupt_tree = 0;
  80
  81 static void mcpn765_halt(void);
  82
  83 TODC_ALLOC();
  84
  85 static void __init
  86 mcpn765_setup_arch(void)
  87 {
  88         struct pci_controller *hose;
  89
  90         if ( ppc_md.progress )
  91                 ppc_md.progress("mcpn765_setup_arch: enter", 0);
  92
  93         loops_per_jiffy = 50000000 / HZ;
  94
  95 #ifdef CONFIG_BLK_DEV_INITRD
  96         if (initrd_start)
  97                 ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
  98         else
  99 #endif
 100 #ifdef  CONFIG_ROOT_NFS
 101                 ROOT_DEV = to_kdev_t(0x00FF);   /* /dev/nfs pseudo device */
 102 #else
 103                 ROOT_DEV = to_kdev_t(0x0802);   /* /dev/sda2 SCSI disk */
 104 #endif
 105
 106 #ifdef CONFIG_DUMMY_CONSOLE
 107         conswitchp = &dummy_con;
 108 #endif
 109
 110         if ( ppc_md.progress )
 111                 ppc_md.progress("mcpn765_setup_arch: find_bridges", 0);
 112
 113         /* Lookup PCI host bridges */
 114         mcpn765_find_bridges();
 115
 116         hose = pci_bus_to_hose(0);
 117         isa_io_base = (ulong)hose->io_base_virt;
 118
 119         TODC_INIT(TODC_TYPE_MK48T37,
 120                   (MCPN765_PHYS_NVRAM_AS0 - isa_io_base),
 121                   (MCPN765_PHYS_NVRAM_AS1 - isa_io_base),
 122                   (MCPN765_PHYS_NVRAM_DATA - isa_io_base),
 123                   8);
 124
 125         OpenPIC_InitSenses = mcpn765_openpic_initsenses;
 126         OpenPIC_NumInitSenses = sizeof(mcpn765_openpic_initsenses);
 127
 128         printk(KERN_INFO "Motorola MCG MCPN765 cPCI Non-System Board\n");
 129         printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
 130
 131         if ( ppc_md.progress )
 132                 ppc_md.progress("mcpn765_setup_arch: exit", 0);
 133
 134         return;
 135 }
 136
 137 /*
 138  * Initialize the VIA 82c586b.
 139  */
 140 static void __init
 141 mcpn765_setup_via_82c586b(void)
 142 {
 143         struct pci_dev  *dev;
 144         u_char          c;
 145
 146         if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
 147                                    PCI_DEVICE_ID_VIA_82C586_0,
 148                                    NULL)) == NULL) {
 149                 printk("No VIA ISA bridge found\n");
 150                 mcpn765_halt();
 151                 /* NOTREACHED */
 152         }
 153
 154         /*
 155          * If the firmware left the EISA 4d0/4d1 ports enabled, make sure
 156          * IRQ 14 is set for edge.
 157          */
 158         pci_read_config_byte(dev, 0x47, &c);
 159
 160         if (c & (1<<5)) {
 161                 c = inb(0x4d1);
 162                 c &= ~(1<<6);
 163                 outb(c, 0x4d1);
 164         }
 165
 166         /* Disable PNP IRQ routing since we use the Hawk's MPIC */
 167         pci_write_config_dword(dev, 0x54, 0);
 168         pci_write_config_byte(dev, 0x58, 0);
 169
 170         if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
 171                                    PCI_DEVICE_ID_VIA_82C586_1,
 172                                    NULL)) == NULL) {
 173                 printk(KERN_ERR "No VIA ISA bridge found\n");
 174                 mcpn765_halt();
 175                 /* NOTREACHED */
 176         }
 177
 178         /*
 179          * PPCBug doesn't set the enable bits for the IDE device.
 180          * Turn them on now.
 181          */
 182         pcibios_read_config_byte(dev->bus->number, dev->devfn, 0x40, &c);
 183         c |= 0x03;
 184         pcibios_write_config_byte(dev->bus->number, dev->devfn, 0x40, c);
 185
 186         return;
 187 }
 188
 189 static void __init
 190 mcpn765_init2(void)
 191 {
 192         /* Do MCPN765 board specific initialization.  */
 193         mcpn765_setup_via_82c586b();
 194
 195         request_region(0x00,0x20,"dma1");
 196         request_region(0x20,0x20,"pic1");
 197         request_region(0x40,0x20,"timer");
 198         request_region(0x80,0x10,"dma page reg");
 199         request_region(0xa0,0x20,"pic2");
 200         request_region(0xc0,0x20,"dma2");
 201
 202         return;
 203 }
 204
 205 /*
 206  * Interrupt setup and service.
 207  * Have MPIC on HAWK and cascaded 8259s on VIA 82586 cascaded to MPIC.
 208  */
 209 static void __init
 210 mcpn765_init_IRQ(void)
 211 {
 212         int i;
 213
 214         if ( ppc_md.progress )
 215                 ppc_md.progress("init_irq: enter", 0);
 216
 217         openpic_init(NUM_8259_INTERRUPTS);
 218         openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
 219                         &i8259_irq);
 220
 221         for(i=0; i < NUM_8259_INTERRUPTS; i++)
 222                 irq_desc[i].handler = &i8259_pic;
 223
 224         i8259_init(0);
 225
 226         if ( ppc_md.progress )
 227                 ppc_md.progress("init_irq: exit", 0);
 228 }
 229
 230 static u32
 231 mcpn765_irq_cannonicalize(u32 irq)
 232 {
 233         if (irq == 2)
 234                 return 9;
 235         else
 236                 return irq;
 237 }
 238
 239 static unsigned long __init
 240 mcpn765_find_end_of_memory(void)
 241 {
 242         return pplus_get_mem_size(MCPN765_HAWK_SMC_BASE);
 243 }
 244
 245 static void __init
 246 mcpn765_map_io(void)
 247 {
 248         io_block_mapping(0xfe800000, 0xfe800000, 0x00800000, _PAGE_IO);
 249 }
 250
 251 static void
 252 mcpn765_reset_board(void)
 253 {
 254         __cli();
 255
 256         /* set VIA IDE controller into native mode */
 257         mcpn765_set_VIA_IDE_native();
 258
 259         /* Set exception prefix high - to the firmware */
 260         _nmask_and_or_msr(0, MSR_IP);
 261
 262         out_8((u_char *)MCPN765_BOARD_MODRST_REG, 0x01);
 263
 264         return;
 265 }
 266
 267 static void
 268 mcpn765_restart(char *cmd)
 269 {
 270         volatile ulong  i = 10000000;
 271
 272         mcpn765_reset_board();
 273
 274         while (i-- > 0);
 275         panic("restart failed\n");
 276 }
 277
 278 static void
 279 mcpn765_power_off(void)
 280 {
 281         mcpn765_halt();
 282         /* NOTREACHED */
 283 }
 284
 285 static void
 286 mcpn765_halt(void)
 287 {
 288         __cli();
 289         while (1);
 290         /* NOTREACHED */
 291 }
 292
 293 static int
 294 mcpn765_show_cpuinfo(struct seq_file *m)
 295 {
 296         seq_printf(m, "vendor\t\t: Motorola MCG\n");
 297         seq_printf(m, "machine\t\t: MCPN765\n");
 298
 299         return 0;
 300 }
 301
 302 /*
 303  * Set BAT 3 to map 0xf0000000 to end of physical memory space.
 304  */
 305 static __inline__ void
 306 mcpn765_set_bat(void)
 307 {
 308         unsigned long   bat3u, bat3l;
 309
 310         __asm__ __volatile__(
 311                         " lis %0,0xf000\n       \
 312                         ori %1,%0,0x002a\n      \
 313                         ori %0,%0,0x1ffe\n      \
 314                         mtspr 0x21e,%0\n        \
 315                         mtspr 0x21f,%1\n        \
 316                         isync\n                 \
 317                         sync "
 318                         : "=r" (bat3u), "=r" (bat3l));
 319 }
 320
 321 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 322 #include <linux/serialP.h>
 323 #include <linux/serial_reg.h>
 324 #include <asm/serial.h>
 325
 326 static struct serial_state rs_table[RS_TABLE_SIZE] = {
 327         SERIAL_PORT_DFNS        /* Defined in <asm/serial.h> */
 328 };
 329
 330 static void
 331 mcpn765_progress(char *s, unsigned short hex)
 332 {
 333         volatile char c;
 334         volatile unsigned long com_port;
 335         u16 shift;
 336
 337         com_port = rs_table[0].port;
 338         shift = rs_table[0].iomem_reg_shift;
 339
 340         while ((c = *s++) != 0) {
 341                 while ((*((volatile unsigned char *)com_port +
 342                                 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
 343                                 ;
 344                 *(volatile unsigned char *)com_port = c;
 345
 346                 if (c == '\n') {
 347                         while ((*((volatile unsigned char *)com_port +
 348                                 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
 349                                         ;
 350                         *(volatile unsigned char *)com_port = '\r';
 351                 }
 352         }
 353 }
 354 #endif  /* CONFIG_SERIAL_TEXT_DEBUG */
 355
 356 void __init
 357 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 358                 unsigned long r6, unsigned long r7)
 359 {
 360         parse_bootinfo(find_bootinfo());
 361
 362         /* Map in board regs, etc. */
 363         mcpn765_set_bat();
 364
 365         isa_mem_base = MCPN765_ISA_MEM_BASE;
 366         pci_dram_offset = MCPN765_PCI_DRAM_OFFSET;
 367         ISA_DMA_THRESHOLD = 0x00ffffff;
 368         DMA_MODE_READ = 0x44;
 369         DMA_MODE_WRITE = 0x48;
 370
 371         ppc_md.setup_arch = mcpn765_setup_arch;
 372         ppc_md.show_cpuinfo = mcpn765_show_cpuinfo;
 373         ppc_md.irq_cannonicalize = mcpn765_irq_cannonicalize;
 374         ppc_md.init_IRQ = mcpn765_init_IRQ;
 375         ppc_md.get_irq = openpic_get_irq;
 376         ppc_md.init = mcpn765_init2;
 377
 378         ppc_md.restart = mcpn765_restart;
 379         ppc_md.power_off = mcpn765_power_off;
 380         ppc_md.halt = mcpn765_halt;
 381
 382         ppc_md.find_end_of_memory = mcpn765_find_end_of_memory;
 383         ppc_md.setup_io_mappings = mcpn765_map_io;
 384
 385         ppc_md.time_init = todc_time_init;
 386         ppc_md.set_rtc_time = todc_set_rtc_time;
 387         ppc_md.get_rtc_time = todc_get_rtc_time;
 388         ppc_md.calibrate_decr = todc_calibrate_decr;
 389
 390         ppc_md.nvram_read_val = todc_m48txx_read_val;
 391         ppc_md.nvram_write_val = todc_m48txx_write_val;
 392
 393 #ifdef  CONFIG_SERIAL_TEXT_DEBUG
 394         ppc_md.progress = mcpn765_progress;
 395 #endif
 396 }