2 * arch/ppc/platforms/menf1_setup.c
4 * Board setup routines for MEN F1
6 * Author: Matt Porter <mporter@mvista.com>
8 * Copyright 2001 MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/config.h>
17 #include <linux/stddef.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/reboot.h>
22 #include <linux/pci.h>
23 #include <linux/kdev_t.h>
24 #include <linux/types.h>
25 #include <linux/major.h>
26 #include <linux/blk.h>
27 #include <linux/console.h>
28 #include <linux/delay.h>
29 #include <linux/ide.h>
30 #include <linux/irq.h>
31 #include <linux/seq_file.h>
33 #include <asm/system.h>
34 #include <asm/pgtable.h>
38 #include <asm/machdep.h>
40 #include <asm/i8259.h>
41 #include <asm/mpc10x.h>
43 #include <asm/bootinfo.h>
47 extern void menf1_find_bridges(void);
48 extern unsigned long loops_per_jiffy;
50 /* Dummy variable to satisfy mpc10x_common.o */
54 menf1_show_cpuinfo(struct seq_file *m)
56 seq_printf(m, "machine\t\t: MEN F1\n");
62 menf1_setup_arch(void)
64 /* init to some ~sane value until calibrate_delay() runs */
65 loops_per_jiffy = 50000000/HZ;
67 /* Lookup PCI host bridges */
70 #ifdef CONFIG_BLK_DEV_INITRD
72 ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
75 #ifdef CONFIG_ROOT_NFS
76 ROOT_DEV = to_kdev_t(0x00ff); /* /dev/nfs pseudo device */
78 ROOT_DEV = to_kdev_t(0x0302); /* /dev/hda2 */
81 #ifdef CONFIG_DUMMY_CONSOLE
82 conswitchp = &dummy_con;
85 printk("MEN F1 port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n");
89 menf1_restart(char *cmd)
98 * Firmware doesn't like re-entry using Map B (CHRP), so make sure the
99 * PCI bridge is using MAP A (PReP).
102 pdev = pci_find_slot(0, PCI_DEVFN(0,0));
104 while(pdev == NULL); /* paranoia */
106 pci_read_config_dword(pdev, MPC10X_CFG_PICR1_REG, &picr1);
108 picr1 = (picr1 & ~MPC10X_CFG_PICR1_ADDR_MAP_MASK) |
109 MPC10X_CFG_PICR1_ADDR_MAP_A;
111 pci_write_config_dword(pdev, MPC10X_CFG_PICR1_REG, picr1);
113 asm volatile("sync");
115 /* SRR0 has system reset vector, SRR1 has default MSR value */
116 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
137 menf1_power_off(void)
147 for ( i = 0 ; i < NUM_8259_INTERRUPTS ; i++ )
148 irq_desc[i].handler = &i8259_pic;
153 * Set BAT 3 to map 0xF0000000.
155 static __inline__ void
158 static int mapping_set = 0;
163 /* wait for all outstanding memory accesses to complete */
167 mtspr(DBAT3U, 0xf0001ffe);
168 mtspr(DBAT3L, 0xf000002a);
170 /* wait for updates */
178 static unsigned long __init
179 menf1_find_end_of_memory(void)
181 /* Cover the I/O with a BAT */
184 /* Read the memory size from the MPC107 SMC */
185 return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
191 io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
194 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
197 menf1_ide_init_hwif_ports (hw_regs_t *hw, ide_ioreg_t data_port,
198 ide_ioreg_t ctrl_port, int *irq)
200 ide_ioreg_t reg = data_port;
203 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
204 hw->io_ports[i] = reg;
208 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
210 hw->io_ports[IDE_CONTROL_OFFSET] =
211 hw->io_ports[IDE_DATA_OFFSET] + 0x206;
218 menf1_ide_default_irq(ide_ioreg_t base)
220 if (base == MENF1_IDE0_BASE_ADDR)
222 else if (base == MENF1_IDE1_BASE_ADDR)
229 menf1_ide_default_io_base(int index)
232 return MENF1_IDE0_BASE_ADDR;
234 return MENF1_IDE1_BASE_ADDR;
243 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
244 unsigned long r6, unsigned long r7)
246 parse_bootinfo(find_bootinfo());
248 isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
249 isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
250 pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
252 ppc_md.setup_arch = menf1_setup_arch;
253 ppc_md.show_cpuinfo = menf1_show_cpuinfo;
254 ppc_md.init_IRQ = menf1_init_IRQ;
255 ppc_md.get_irq = i8259_irq;
257 ppc_md.find_end_of_memory = menf1_find_end_of_memory;
258 ppc_md.setup_io_mappings = menf1_map_io;
260 ppc_md.restart = menf1_restart;
261 ppc_md.power_off = menf1_power_off;
262 ppc_md.halt = menf1_halt;
264 TODC_INIT(TODC_TYPE_MK48T59,
270 ppc_md.time_init = todc_time_init;
271 ppc_md.get_rtc_time = todc_get_rtc_time;
272 ppc_md.set_rtc_time = todc_set_rtc_time;
273 ppc_md.calibrate_decr = todc_calibrate_decr;
275 ppc_md.nvram_read_val = todc_m48txx_read_val;
276 ppc_md.nvram_write_val = todc_m48txx_write_val;
278 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
279 ppc_ide_md.default_io_base = menf1_ide_default_io_base;
280 ppc_ide_md.default_irq = menf1_ide_default_irq;
281 ppc_ide_md.ide_init_hwif = menf1_ide_init_hwif_ports;