arch/ppc/platforms/pcore_setup.c

   1 /*
   2  * arch/ppc/platforms/pcore_setup.c
   3  *
   4  * Setup routines for Force PCORE boards
   5  *
   6  * Author: Matt Porter <mporter@mvista.com>
   7  *
   8  * Copyright 2001 MontaVista Software Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/stddef.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/errno.h>
  21 #include <linux/reboot.h>
  22 #include <linux/pci.h>
  23 #include <linux/kdev_t.h>
  24 #include <linux/types.h>
  25 #include <linux/major.h>
  26 #include <linux/blk.h>
  27 #include <linux/console.h>
  28 #include <linux/delay.h>
  29 #include <linux/irq.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/ide.h>
  32
  33 #include <asm/system.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/page.h>
  36 #include <asm/dma.h>
  37 #include <asm/io.h>
  38 #include <asm/machdep.h>
  39 #include <asm/time.h>
  40 #include <asm/i8259.h>
  41 #include <asm/mpc10x.h>
  42 #include <asm/todc.h>
  43 #include <asm/bootinfo.h>
  44
  45 #include "pcore.h"
  46
  47 extern int pcore_find_bridges(void);
  48 extern unsigned long loops_per_jiffy;
  49
  50 static int board_type;
  51
  52 /* Dummy variable to satisfy mpc10x_common.o */
  53 void *OpenPIC_Addr;
  54
  55 static int
  56 pcore_show_cpuinfo(struct seq_file *m)
  57 {
  58         seq_printf(m, "vendor\t\t: Force Computers\n");
  59
  60         if (board_type == PCORE_TYPE_6750)
  61                 seq_printf(m, "machine\t\t: PowerCore 6750\n");
  62         else /* PCORE_TYPE_680 */
  63                 seq_printf(m, "machine\t\t: PowerCore 680\n");
  64
  65         seq_printf(m, "L2\t\t: " );
  66         if (board_type == PCORE_TYPE_6750)
  67                 switch (readb(PCORE_DCCR_REG) & PCORE_DCCR_L2_MASK)
  68                 {
  69                         case PCORE_DCCR_L2_0KB:
  70                                 seq_printf(m, "nocache");
  71                                 break;
  72                         case PCORE_DCCR_L2_256KB:
  73                                 seq_printf(m, "256KB");
  74                                 break;
  75                         case PCORE_DCCR_L2_1MB:
  76                                 seq_printf(m, "1MB");
  77                                 break;
  78                         case PCORE_DCCR_L2_512KB:
  79                                 seq_printf(m, "512KB");
  80                                 break;
  81                         default:
  82                                 seq_printf(m, "error");
  83                                 break;
  84                 }
  85         else /* PCORE_TYPE_680 */
  86                 switch (readb(PCORE_DCCR_REG) & PCORE_DCCR_L2_MASK)
  87                 {
  88                         case PCORE_DCCR_L2_2MB:
  89                                 seq_printf(m, "2MB");
  90                                 break;
  91                         case PCORE_DCCR_L2_256KB:
  92                                 seq_printf(m, "reserved");
  93                                 break;
  94                         case PCORE_DCCR_L2_1MB:
  95                                 seq_printf(m, "1MB");
  96                                 break;
  97                         case PCORE_DCCR_L2_512KB:
  98                                 seq_printf(m, "512KB");
  99                                 break;
 100                         default:
 101                                 seq_printf(m, "error");
 102                                 break;
 103                 }
 104
 105         seq_printf(m, "\n");
 106
 107         return 0;
 108 }
 109
 110 static void __init
 111 pcore_setup_arch(void)
 112 {
 113         /* init to some ~sane value until calibrate_delay() runs */
 114         loops_per_jiffy = 50000000/HZ;
 115
 116         /* Lookup PCI host bridges */
 117         board_type = pcore_find_bridges();
 118
 119 #ifdef CONFIG_BLK_DEV_INITRD
 120         if (initrd_start)
 121                 ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0); /* /dev/ram */
 122         else
 123 #endif
 124 #ifdef CONFIG_ROOT_NFS
 125                 ROOT_DEV = to_kdev_t(0x00ff); /* /dev/nfs pseudo device */
 126 #else
 127                 ROOT_DEV = to_kdev_t(0x0802); /* /dev/sda2 */
 128 #endif
 129
 130 #ifdef CONFIG_DUMMY_CONSOLE
 131         conswitchp = &dummy_con;
 132 #endif
 133
 134                  printk("Force PCore port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n");
 135 }
 136
 137 static void
 138 pcore_restart(char *cmd)
 139 {
 140         __cli();
 141         /* Hard reset */
 142         writeb(0x11, 0xfe000332);
 143         while(1);
 144 }
 145
 146 static void
 147 pcore_halt(void)
 148 {
 149         __cli();
 150         /* Turn off user LEDs */
 151         writeb(0x00, 0xfe000300);
 152         while (1);
 153 }
 154
 155 static void
 156 pcore_power_off(void)
 157 {
 158         pcore_halt();
 159 }
 160
 161
 162 static void __init
 163 pcore_init_IRQ(void)
 164 {
 165         int i;
 166
 167         for (i = 0; i < 16; i++)
 168                 irq_desc[i].handler = &i8259_pic;
 169
 170         i8259_init(0);
 171 }
 172
 173 /*
 174  * Set BAT 3 to map 0xf0000000 to end of physical memory space.
 175  */
 176 static __inline__ void
 177 pcore_set_bat(void)
 178 {
 179         unsigned long   bat3u, bat3l;
 180         static int      mapping_set = 0;
 181
 182         if (!mapping_set) {
 183                 __asm__ __volatile__(
 184                                 " lis %0,0xf000\n \
 185                                 ori %1,%0,0x002a\n \
 186                                 ori %0,%0,0x1ffe\n \
 187                                 mtspr 0x21e,%0\n \
 188                                 mtspr 0x21f,%1\n \
 189                                 isync\n \
 190                                 sync "
 191                                 : "=r" (bat3u), "=r" (bat3l));
 192
 193                 mapping_set = 1;
 194         }
 195         return;
 196 }
 197
 198 static unsigned long __init
 199 pcore_find_end_of_memory(void)
 200 {
 201         /* Cover I/O space with a BAT */
 202         /* yuck, better hope your ram size is a power of 2  -- paulus */
 203         pcore_set_bat();
 204
 205         return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
 206 }
 207
 208 static void __init
 209 pcore_map_io(void)
 210 {
 211         io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
 212 }
 213
 214 TODC_ALLOC();
 215
 216 void __init
 217 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 218                 unsigned long r6, unsigned long r7)
 219 {
 220         parse_bootinfo(find_bootinfo());
 221
 222         isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
 223         isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
 224         pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
 225
 226         ppc_md.setup_arch       = pcore_setup_arch;
 227         ppc_md.show_cpuinfo     = pcore_show_cpuinfo;
 228         ppc_md.init_IRQ         = pcore_init_IRQ;
 229         ppc_md.get_irq          = i8259_irq;
 230
 231         ppc_md.find_end_of_memory = pcore_find_end_of_memory;
 232         ppc_md.setup_io_mappings = pcore_map_io;
 233
 234         ppc_md.restart          = pcore_restart;
 235         ppc_md.power_off        = pcore_power_off;
 236         ppc_md.halt             = pcore_halt;
 237
 238         TODC_INIT(TODC_TYPE_MK48T59,
 239                   PCORE_NVRAM_AS0,
 240                   PCORE_NVRAM_AS1,
 241                   PCORE_NVRAM_DATA,
 242                   8);
 243
 244         ppc_md.time_init        = todc_time_init;
 245         ppc_md.get_rtc_time     = todc_get_rtc_time;
 246         ppc_md.set_rtc_time     = todc_set_rtc_time;
 247         ppc_md.calibrate_decr   = todc_calibrate_decr;
 248
 249         ppc_md.nvram_read_val   = todc_m48txx_read_val;
 250         ppc_md.nvram_write_val  = todc_m48txx_write_val;
 251 }