arch/ppc/platforms/pmac_pic.c

   1 /*
   2  * BK Id: SCCS/s.pmac_pic.c 1.34 01/07/03 22:00:10 paulus
   3  */
   4 #include <linux/config.h>
   5 #include <linux/stddef.h>
   6 #include <linux/init.h>
   7 #include <linux/sched.h>
   8 #include <linux/signal.h>
   9 #include <linux/pci.h>
  10
  11 #include <asm/sections.h>
  12 #include <asm/io.h>
  13 #include <asm/smp.h>
  14 #include <asm/prom.h>
  15 #include <asm/pci-bridge.h>
  16 #include <asm/time.h>
  17 #include <asm/open_pic.h>
  18
  19 #include "pmac_pic.h"
  20
  21 struct pmac_irq_hw {
  22         unsigned int    event;
  23         unsigned int    enable;
  24         unsigned int    ack;
  25         unsigned int    level;
  26 };
  27
  28 /* Default addresses */
  29 static volatile struct pmac_irq_hw *pmac_irq_hw[4] __pmacdata = {
  30         (struct pmac_irq_hw *) 0xf3000020,
  31         (struct pmac_irq_hw *) 0xf3000010,
  32         (struct pmac_irq_hw *) 0xf4000020,
  33         (struct pmac_irq_hw *) 0xf4000010,
  34 };
  35
  36 #define GC_LEVEL_MASK           0x3ff00000
  37 #define OHARE_LEVEL_MASK        0x1ff00000
  38 #define HEATHROW_LEVEL_MASK     0x1ff00000
  39
  40 static int max_irqs __pmacdata;
  41 static int max_real_irqs __pmacdata;
  42 static u32 level_mask[4] __pmacdata;
  43
  44 static spinlock_t pmac_pic_lock __pmacdata = SPIN_LOCK_UNLOCKED;
  45
  46
  47 #define GATWICK_IRQ_POOL_SIZE        10
  48 static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE] __pmacdata;
  49
  50 /*
  51  * Mark an irq as "lost".  This is only used on the pmac
  52  * since it can lose interrupts (see pmac_set_irq_mask).
  53  * -- Cort
  54  */
  55 void __pmac
  56 __set_lost(unsigned long irq_nr, int nokick)
  57 {
  58         if (!test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
  59                 atomic_inc(&ppc_n_lost_interrupts);
  60                 if (!nokick)
  61                         set_dec(1);
  62         }
  63 }
  64
  65 static void __pmac
  66 pmac_mask_and_ack_irq(unsigned int irq_nr)
  67 {
  68         unsigned long bit = 1UL << (irq_nr & 0x1f);
  69         int i = irq_nr >> 5;
  70         unsigned long flags;
  71
  72         if ((unsigned)irq_nr >= max_irqs)
  73                 return;
  74
  75         clear_bit(irq_nr, ppc_cached_irq_mask);
  76         if (test_and_clear_bit(irq_nr, ppc_lost_interrupts))
  77                 atomic_dec(&ppc_n_lost_interrupts);
  78         spin_lock_irqsave(&pmac_pic_lock, flags);
  79         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
  80         out_le32(&pmac_irq_hw[i]->ack, bit);
  81         do {
  82                 /* make sure ack gets to controller before we enable
  83                    interrupts */
  84                 mb();
  85         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
  86                 != (ppc_cached_irq_mask[i] & bit));
  87         spin_unlock_irqrestore(&pmac_pic_lock, flags);
  88 }
  89
  90 static void __pmac pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
  91 {
  92         unsigned long bit = 1UL << (irq_nr & 0x1f);
  93         int i = irq_nr >> 5;
  94         unsigned long flags;
  95
  96         if ((unsigned)irq_nr >= max_irqs)
  97                 return;
  98
  99         spin_lock_irqsave(&pmac_pic_lock, flags);
 100         /* enable unmasked interrupts */
 101         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
 102
 103         do {
 104                 /* make sure mask gets to controller before we
 105                    return to user */
 106                 mb();
 107         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
 108                 != (ppc_cached_irq_mask[i] & bit));
 109
 110         /*
 111          * Unfortunately, setting the bit in the enable register
 112          * when the device interrupt is already on *doesn't* set
 113          * the bit in the flag register or request another interrupt.
 114          */
 115         if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
 116                 __set_lost((ulong)irq_nr, nokicklost);
 117         spin_unlock_irqrestore(&pmac_pic_lock, flags);
 118 }
 119
 120 static void __pmac pmac_mask_irq(unsigned int irq_nr)
 121 {
 122         clear_bit(irq_nr, ppc_cached_irq_mask);
 123         pmac_set_irq_mask(irq_nr, 0);
 124         mb();
 125 }
 126
 127 static void __pmac pmac_unmask_irq(unsigned int irq_nr)
 128 {
 129         set_bit(irq_nr, ppc_cached_irq_mask);
 130         pmac_set_irq_mask(irq_nr, 0);
 131 }
 132
 133 static void __pmac pmac_end_irq(unsigned int irq_nr)
 134 {
 135         if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
 136                 set_bit(irq_nr, ppc_cached_irq_mask);
 137                 pmac_set_irq_mask(irq_nr, 1);
 138         }
 139 }
 140
 141
 142 struct hw_interrupt_type pmac_pic = {
 143         " PMAC-PIC ",
 144         NULL,
 145         NULL,
 146         pmac_unmask_irq,
 147         pmac_mask_irq,
 148         pmac_mask_and_ack_irq,
 149         pmac_end_irq,
 150         NULL
 151 };
 152
 153 struct hw_interrupt_type gatwick_pic = {
 154         " GATWICK  ",
 155         NULL,
 156         NULL,
 157         pmac_unmask_irq,
 158         pmac_mask_irq,
 159         pmac_mask_and_ack_irq,
 160         pmac_end_irq,
 161         NULL
 162 };
 163
 164 static void gatwick_action(int cpl, void *dev_id, struct pt_regs *regs)
 165 {
 166         int irq, bits;
 167
 168         for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
 169                 int i = irq >> 5;
 170                 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
 171                 /* We must read level interrupts from the level register */
 172                 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
 173                 bits &= ppc_cached_irq_mask[i];
 174                 if (bits == 0)
 175                         continue;
 176                 irq += __ilog2(bits);
 177                 break;
 178         }
 179         /* The previous version of this code allowed for this case, we
 180          * don't.  Put this here to check for it.
 181          * -- Cort
 182          */
 183         if ( irq_desc[irq].handler != &gatwick_pic )
 184                 printk("gatwick irq not from gatwick pic\n");
 185         else
 186                 ppc_irq_dispatch_handler( regs, irq );
 187 }
 188
 189 int
 190 pmac_get_irq(struct pt_regs *regs)
 191 {
 192         int irq;
 193         unsigned long bits = 0;
 194
 195 #ifdef CONFIG_SMP
 196         void psurge_smp_message_recv(struct pt_regs *);
 197
 198         /* IPI's are a hack on the powersurge -- Cort */
 199         if ( smp_processor_id() != 0 ) {
 200                 psurge_smp_message_recv(regs);
 201                 return -2;      /* ignore, already handled */
 202         }
 203 #endif /* CONFIG_SMP */
 204         for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
 205                 int i = irq >> 5;
 206                 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
 207                 /* We must read level interrupts from the level register */
 208                 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
 209                 bits &= ppc_cached_irq_mask[i];
 210                 if (bits == 0)
 211                         continue;
 212                 irq += __ilog2(bits);
 213                 break;
 214         }
 215
 216         return irq;
 217 }
 218
 219 /* This routine will fix some missing interrupt values in the device tree
 220  * on the gatwick mac-io controller used by some PowerBooks
 221  */
 222 static void __init
 223 pmac_fix_gatwick_interrupts(struct device_node *gw, int irq_base)
 224 {
 225         struct device_node *node;
 226         int count;
 227
 228         memset(gatwick_int_pool, 0, sizeof(gatwick_int_pool));
 229         node = gw->child;
 230         count = 0;
 231         while(node)
 232         {
 233                 /* Fix SCC */
 234                 if (strcasecmp(node->name, "escc") == 0)
 235                         if (node->child) {
 236                                 if (node->child->n_intrs < 3) {
 237                                         node->child->intrs = &gatwick_int_pool[count];
 238                                         count += 3;
 239                                 }
 240                                 node->child->n_intrs = 3;
 241                                 node->child->intrs[0].line = 15+irq_base;
 242                                 node->child->intrs[1].line =  4+irq_base;
 243                                 node->child->intrs[2].line =  5+irq_base;
 244                                 printk(KERN_INFO "irq: fixed SCC on second controller (%d,%d,%d)\n",
 245                                         node->child->intrs[0].line,
 246                                         node->child->intrs[1].line,
 247                                         node->child->intrs[2].line);
 248                         }
 249                 /* Fix media-bay & left SWIM */
 250                 if (strcasecmp(node->name, "media-bay") == 0) {
 251                         struct device_node* ya_node;
 252
 253                         if (node->n_intrs == 0)
 254                                 node->intrs = &gatwick_int_pool[count++];
 255                         node->n_intrs = 1;
 256                         node->intrs[0].line = 29+irq_base;
 257                         printk(KERN_INFO "irq: fixed media-bay on second controller (%d)\n",
 258                                         node->intrs[0].line);
 259
 260                         ya_node = node->child;
 261                         while(ya_node)
 262                         {
 263                                 if (strcasecmp(ya_node->name, "floppy") == 0) {
 264                                         if (ya_node->n_intrs < 2) {
 265                                                 ya_node->intrs = &gatwick_int_pool[count];
 266                                                 count += 2;
 267                                         }
 268                                         ya_node->n_intrs = 2;
 269                                         ya_node->intrs[0].line = 19+irq_base;
 270                                         ya_node->intrs[1].line =  1+irq_base;
 271                                         printk(KERN_INFO "irq: fixed floppy on second controller (%d,%d)\n",
 272                                                 ya_node->intrs[0].line, ya_node->intrs[1].line);
 273                                 }
 274                                 if (strcasecmp(ya_node->name, "ata4") == 0) {
 275                                         if (ya_node->n_intrs < 2) {
 276                                                 ya_node->intrs = &gatwick_int_pool[count];
 277                                                 count += 2;
 278                                         }
 279                                         ya_node->n_intrs = 2;
 280                                         ya_node->intrs[0].line = 14+irq_base;
 281                                         ya_node->intrs[1].line =  3+irq_base;
 282                                         printk(KERN_INFO "irq: fixed ide on second controller (%d,%d)\n",
 283                                                 ya_node->intrs[0].line, ya_node->intrs[1].line);
 284                                 }
 285                                 ya_node = ya_node->sibling;
 286                         }
 287                 }
 288                 node = node->sibling;
 289         }
 290         if (count > 10) {
 291                 printk("WARNING !! Gatwick interrupt pool overflow\n");
 292                 printk("  GATWICK_IRQ_POOL_SIZE = %d\n", GATWICK_IRQ_POOL_SIZE);
 293                 printk("              requested = %d\n", count);
 294         }
 295 }
 296
 297 /*
 298  * The PowerBook 3400/2400/3500 can have a combo ethernet/modem
 299  * card which includes an ohare chip that acts as a second interrupt
 300  * controller.  If we find this second ohare, set it up and fix the
 301  * interrupt value in the device tree for the ethernet chip.
 302  */
 303 static int __init enable_second_ohare(void)
 304 {
 305         unsigned char bus, devfn;
 306         unsigned short cmd;
 307         unsigned long addr;
 308         struct device_node *irqctrler = find_devices("pci106b,7");
 309         struct device_node *ether;
 310
 311         if (irqctrler == NULL || irqctrler->n_addrs <= 0)
 312                 return -1;
 313         addr = (unsigned long) ioremap(irqctrler->addrs[0].address, 0x40);
 314         pmac_irq_hw[1] = (volatile struct pmac_irq_hw *)(addr + 0x20);
 315         max_irqs = 64;
 316         if (pci_device_from_OF_node(irqctrler, &bus, &devfn) == 0) {
 317                 struct pci_controller* hose = pci_find_hose_for_OF_device(irqctrler);
 318                 if (!hose)
 319                     printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
 320                 else {
 321                     early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
 322                     cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 323                     cmd &= ~PCI_COMMAND_IO;
 324                     early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
 325                 }
 326         }
 327
 328         /* Fix interrupt for the modem/ethernet combo controller. The number
 329            in the device tree (27) is bogus (correct for the ethernet-only
 330            board but not the combo ethernet/modem board).
 331            The real interrupt is 28 on the second controller -> 28+32 = 60.
 332         */
 333         ether = find_devices("pci1011,14");
 334         if (ether && ether->n_intrs > 0) {
 335                 ether->intrs[0].line = 60;
 336                 printk(KERN_INFO "irq: Fixed ethernet IRQ to %d\n",
 337                        ether->intrs[0].line);
 338         }
 339
 340         /* Return the interrupt number of the cascade */
 341         return irqctrler->intrs[0].line;
 342 }
 343
 344 void __init
 345 pmac_pic_init(void)
 346 {
 347         int i;
 348         struct device_node *irqctrler;
 349         unsigned long addr;
 350         int irq_cascade = -1;
 351
 352         /* We first try to detect Apple's new Core99 chipset, since mac-io
 353          * is quite different on those machines and contains an IBM MPIC2.
 354          */
 355         irqctrler = find_type_devices("open-pic");
 356         if (irqctrler != NULL)
 357         {
 358                 printk("PowerMac using OpenPIC irq controller\n");
 359                 if (irqctrler->n_addrs > 0)
 360                 {
 361                         unsigned char senses[NR_IRQS];
 362
 363                         prom_get_irq_senses(senses, 0, NR_IRQS);
 364                         OpenPIC_InitSenses = senses;
 365                         OpenPIC_NumInitSenses = NR_IRQS;
 366                         ppc_md.get_irq = openpic_get_irq;
 367                         OpenPIC_Addr = ioremap(irqctrler->addrs[0].address,
 368                                                irqctrler->addrs[0].size);
 369                         openpic_init(0);
 370 #ifdef CONFIG_XMON
 371                         {
 372                                 struct device_node* pswitch;
 373                                 int nmi_irq;
 374
 375                                 pswitch = find_devices("programmer-switch");
 376                                 if (pswitch && pswitch->n_intrs) {
 377                                         nmi_irq = pswitch->intrs[0].line;
 378                                         openpic_init_nmi_irq(nmi_irq);
 379                                         request_irq(nmi_irq, xmon_irq, 0,
 380                                                         "NMI - XMON", 0);
 381                                 }
 382                         }
 383 #endif  /* CONFIG_XMON */
 384                         return;
 385                 }
 386                 irqctrler = NULL;
 387         }
 388
 389         /* Get the level/edge settings, assume if it's not
 390          * a Grand Central nor an OHare, then it's an Heathrow
 391          * (or Paddington).
 392          */
 393         if (find_devices("gc"))
 394                 level_mask[0] = GC_LEVEL_MASK;
 395         else if (find_devices("ohare")) {
 396                 level_mask[0] = OHARE_LEVEL_MASK;
 397                 /* We might have a second cascaded ohare */
 398                 level_mask[1] = OHARE_LEVEL_MASK;
 399         } else {
 400                 level_mask[0] = HEATHROW_LEVEL_MASK;
 401                 level_mask[1] = 0;
 402                 /* We might have a second cascaded heathrow */
 403                 level_mask[2] = HEATHROW_LEVEL_MASK;
 404                 level_mask[3] = 0;
 405         }
 406
 407         /*
 408          * G3 powermacs and 1999 G3 PowerBooks have 64 interrupts,
 409          * 1998 G3 Series PowerBooks have 128,
 410          * other powermacs have 32.
 411          * The combo ethernet/modem card for the Powerstar powerbooks
 412          * (2400/3400/3500, ohare based) has a second ohare chip
 413          * effectively making a total of 64.
 414          */
 415         max_irqs = max_real_irqs = 32;
 416         irqctrler = find_devices("mac-io");
 417         if (irqctrler)
 418         {
 419                 max_real_irqs = 64;
 420                 if (irqctrler->next)
 421                         max_irqs = 128;
 422                 else
 423                         max_irqs = 64;
 424         }
 425         for ( i = 0; i < max_real_irqs ; i++ )
 426                 irq_desc[i].handler = &pmac_pic;
 427
 428         /* get addresses of first controller */
 429         if (irqctrler) {
 430                 if  (irqctrler->n_addrs > 0) {
 431                         addr = (unsigned long)
 432                                 ioremap(irqctrler->addrs[0].address, 0x40);
 433                         for (i = 0; i < 2; ++i)
 434                                 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
 435                                         (addr + (2 - i) * 0x10);
 436                 }
 437
 438                 /* get addresses of second controller */
 439                 irqctrler = irqctrler->next;
 440                 if (irqctrler && irqctrler->n_addrs > 0) {
 441                         addr = (unsigned long)
 442                                 ioremap(irqctrler->addrs[0].address, 0x40);
 443                         for (i = 2; i < 4; ++i)
 444                                 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
 445                                         (addr + (4 - i) * 0x10);
 446                         irq_cascade = irqctrler->intrs[0].line;
 447                         if (device_is_compatible(irqctrler, "gatwick"))
 448                                 pmac_fix_gatwick_interrupts(irqctrler, max_real_irqs);
 449                 }
 450         } else {
 451                 /* older powermacs have a GC (grand central) or ohare at
 452                    f3000000, with interrupt control registers at f3000020. */
 453                 addr = (unsigned long) ioremap(0xf3000000, 0x40);
 454                 pmac_irq_hw[0] = (volatile struct pmac_irq_hw *) (addr + 0x20);
 455         }
 456
 457         /* PowerBooks 3400 and 3500 can have a second controller in a second
 458            ohare chip, on the combo ethernet/modem card */
 459         if (machine_is_compatible("AAPL,3400/2400")
 460              || machine_is_compatible("AAPL,3500"))
 461                 irq_cascade = enable_second_ohare();
 462
 463         /* disable all interrupts in all controllers */
 464         for (i = 0; i * 32 < max_irqs; ++i)
 465                 out_le32(&pmac_irq_hw[i]->enable, 0);
 466         /* mark level interrupts */
 467         for (i = 0; i < max_irqs; i++)
 468                 if (level_mask[i >> 5] & (1UL << (i & 0x1f)))
 469                         irq_desc[i].status = IRQ_LEVEL;
 470
 471         /* get interrupt line of secondary interrupt controller */
 472         if (irq_cascade >= 0) {
 473                 printk(KERN_INFO "irq: secondary controller on irq %d\n",
 474                         (int)irq_cascade);
 475                 for ( i = max_real_irqs ; i < max_irqs ; i++ )
 476                         irq_desc[i].handler = &gatwick_pic;
 477                 request_irq( irq_cascade, gatwick_action, SA_INTERRUPT,
 478                              "cascade", 0 );
 479         }
 480         printk("System has %d possible interrupts\n", max_irqs);
 481         if (max_irqs != max_real_irqs)
 482                 printk(KERN_DEBUG "%d interrupts on main controller\n",
 483                         max_real_irqs);
 484
 485 #ifdef CONFIG_XMON
 486         request_irq(20, xmon_irq, 0, "NMI - XMON", 0);
 487 #endif  /* CONFIG_XMON */
 488 }
 489
 490 #ifdef CONFIG_PMAC_PBOOK
 491 /*
 492  * These procedures are used in implementing sleep on the powerbooks.
 493  * sleep_save_intrs() saves the states of all interrupt enables
 494  * and disables all interrupts except for the nominated one.
 495  * sleep_restore_intrs() restores the states of all interrupt enables.
 496  */
 497 unsigned int sleep_save_mask[2];
 498
 499 void __pmac
 500 pmac_sleep_save_intrs(int viaint)
 501 {
 502         sleep_save_mask[0] = ppc_cached_irq_mask[0];
 503         sleep_save_mask[1] = ppc_cached_irq_mask[1];
 504         ppc_cached_irq_mask[0] = 0;
 505         ppc_cached_irq_mask[1] = 0;
 506         if (viaint > 0)
 507                 set_bit(viaint, ppc_cached_irq_mask);
 508         out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
 509         if (max_real_irqs > 32)
 510                 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
 511         (void)in_le32(&pmac_irq_hw[0]->event);
 512         /* make sure mask gets to controller before we return to caller */
 513         mb();
 514         (void)in_le32(&pmac_irq_hw[0]->enable);
 515 }
 516
 517 void __pmac
 518 pmac_sleep_restore_intrs(void)
 519 {
 520         int i;
 521
 522         out_le32(&pmac_irq_hw[0]->enable, 0);
 523         if (max_real_irqs > 32)
 524                 out_le32(&pmac_irq_hw[1]->enable, 0);
 525         mb();
 526         for (i = 0; i < max_real_irqs; ++i)
 527                 if (test_bit(i, sleep_save_mask))
 528                         pmac_unmask_irq(i);
 529 }
 530 #endif /* CONFIG_PMAC_PBOOK */