4 * Copyright 2000-2002 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc.
6 * akuster@mvista.com <source@mvista.com>
8 * Module name: rainier.c
11 * Architecture- / platform-specific boot-time initialization code for
12 * IBM PowerPC 4xx based boards. Adapted from original
19 * 02/05/02 - initial work
21 * Please read the COPYING file for all license details.
23 #include <linux/config.h>
24 #include <linux/init.h>
25 #include <linux/smp.h>
26 #include <linux/threads.h>
27 #include <linux/param.h>
28 #include <linux/string.h>
29 #include <linux/blk.h>
30 #include <linux/pci.h>
31 #include <linux/rtc.h>
32 #include <linux/serial.h>
33 #include <asm/pc_serial.h>
35 #include <asm/system.h>
36 #include <asm/pci-bridge.h>
37 #include <asm/processor.h>
38 #include <asm/machdep.h>
43 #include <platforms/ibm_ocp.h>
48 #define DBG(x...) printk(x)
53 void *rainier_rtc_base;
54 unsigned int rainier_io_page;
57 *locate_rainier_io(void)
61 temp = in_le32((void*)PPC405_PCI_CONFIG_ADDR) & PCI_CONFIG_ADDR_MASK;
62 out_le32((void*)PPC405_PCI_CONFIG_ADDR,
63 temp | PCI_CONFIG_CYCLE_ENABLE |PCI_BASE_ADDRESS_2);
64 temp = in_le32((void*)PPC405_PCI_CONFIG_DATA);
66 if (temp == (PCI_BASE_ADDRESS_MEM_CARD2 | PCI_BASE_ADDRESS_MEM_PREFETCH))
67 return PPC_405RAINIER2_IO_PAGE;
69 return PPC_405RAINIER1_IO_PAGE;
73 ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
75 static char pci_irq_table[][4] =
77 * PCI IDSEL/INTPIN->INTLINE
81 {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */
82 {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */
83 {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */
84 {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */
87 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
88 return PCI_IRQ_TABLE_LOOKUP;
92 board_setup_arch(void)
94 struct serial_struct serialreq = {0};
96 serialreq.iomem_base = (void*)PPC405_UART0_IO_BASE;
97 serialreq.iomem_base += rainier_io_page;
98 serialreq.baud_base = BASE_BAUD;
99 serialreq.irq = PPC405_UART0_INT;
100 serialreq.flags = STD_COM_FLAGS;
101 serialreq.io_type = SERIAL_IO_MEM;
103 early_serial_setup(&serialreq);
105 /* RTC step for the rainier */
106 rainier_rtc_base = (void *) WALNUT_RTC_VADDR;
107 TODC_INIT(TODC_TYPE_DS1743, rainier_rtc_base, rainier_rtc_base,
108 rainier_rtc_base, 8);
112 bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
115 * Expected PCI mapping:
117 * PLB addr PCI memory addr
118 * --------------------- ---------------------
119 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
120 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
122 * PLB addr PCI io addr
123 * --------------------- ---------------------
124 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
126 * The following code is simplified by assuming that the bootrom
127 * has been well behaved in following this mapping.
133 printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
134 printk("PCI bridge regs before fixup \n");
135 for (i = 0; i <= 3; i++) {
136 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
137 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
138 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
139 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
141 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
142 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
143 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
144 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
148 /* Disable region first */
149 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
150 /* PLB starting addr, PCI: 0x80000000 */
151 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
152 /* PCI start addr, 0x80000000 */
153 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
154 /* 512MB range of PLB to PCI */
155 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
156 /* Enable no pre-fetch, enable region */
157 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
158 (PPC405_PCI_UPPER_MEM -
159 PPC405_PCI_MEM_BASE)) | 0x01));
161 /*region one used bu rainier*/
162 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
163 out_le32((void *) &(pcip->pmm[1].la), 0x80000000);
164 out_le32((void *) &(pcip->pmm[1].pcila), 0x80000000);
165 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
166 out_le32((void *) &(pcip->pmm[1].ma), 0xFFFF8001);
167 out_le32((void *) &(pcip->ptm1ms), 0x00000000);
169 /* Disable region two */
170 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
171 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
172 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
173 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
174 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
175 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
177 /* end work arround */
180 printk("PCI bridge regs after fixup \n");
181 for (i = 0; i <= 3; i++) {
182 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
183 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
184 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
185 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
187 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
188 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
189 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
190 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
196 board_io_mapping(void)
198 io_block_mapping(RAINIER_IO_PAGE_INTERPOSER_PADDR,
199 RAINIER_IO_PAGE_INTERPOSER_VADDR,PAGE_SIZE , _PAGE_IO);
201 io_block_mapping(RAINIER_IO_PAGE_PCI_PADDR,
202 RAINIER_IO_PAGE_PCI_VADDR,PAGE_SIZE , _PAGE_IO);
204 io_block_mapping(RAINIER_RTC_VADDR,
205 RAINIER_RTC_PADDR, RAINIER_RTC_SIZE, _PAGE_IO);
207 rainier_io_page = locate_rainier_io();
209 io_block_mapping(rainier_io_page ,
210 rainier_io_page , PAGE_SIZE, _PAGE_IO);
215 board_setup_irq(void)
222 ppc_md.time_init = m48t3x_time_init;
223 ppc_md.set_rtc_time = m48t3x_set_rtc_time;
224 ppc_md.get_rtc_time = m48t3x_get_rtc_time;
225 ppc_md.time_init = todc_time_init;
226 ppc_md.nvram_read_val = todc_direct_read_val;
227 ppc_md.nvram_write_val = todc_direct_write_val;