2 * arch/ppc/platforms/sandpoint.c
4 * Board setup routines for the Motorola SPS Sandpoint Test Platform.
6 * Author: Mark A. Greer
9 * 2000-2003 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
16 * This file adds support for the Motorola SPS Sandpoint Test Platform.
17 * These boards have a PPMC slot for the processor so any combination
18 * of cpu and host bridge can be attached. This port is for an 8240 PPMC
19 * module from Motorola SPS and other closely related cpu/host bridge
20 * combinations (e.g., 750/755/7400 with MPC107 host bridge).
21 * The sandpoint itself has a Windbond 83c553 (PCI-ISA bridge, 2 DMA ctlrs, 2
22 * cascaded 8259 interrupt ctlrs, 8254 Timer/Counter, and an IDE ctlr), a
23 * National 87308 (RTC, 2 UARTs, Keyboard & mouse ctlrs, and a floppy ctlr),
24 * and 4 PCI slots (only 2 of which are usable; the other 2 are keyed for 3.3V
27 * The firmware on the sandpoint is called DINK (not my acronym :). This port
28 * depends on DINK to do some basic initialization (e.g., initialize the memory
29 * ctlr) and to ensure that the processor is using MAP B (CHRP map).
31 * The switch settings for the Sandpoint board MUST be as follows:
37 * 'down' is in the direction from the PCI slots towards the PPMC slot;
38 * 'up' is in the direction from the PPMC slot towards the PCI slots.
39 * Be careful, the way the sandpoint board is installed in XT chasses will
40 * make the directions reversed.
42 * Since Motorola listened to our suggestions for improvement, we now have
43 * the Sandpoint X3 board. All of the PCI slots are available, it uses
44 * the serial interrupt interface (just a hardware thing we need to
45 * configure properly).
47 * Use the default X3 switch settings. The interrupts are then:
49 * 0 SIOINT (8259, active low)
54 * 7 Winbond INTC (IDE interrupt)
55 * 8 Winbond INTD (IDE interrupt)
57 * It is important to note that this code only supports the Sandpoint X3
58 * (all flavors) platform, and it does not support the X2 anymore. Code
59 * that at one time worked on the X2 can be found at:
60 * ftp://source.mvista.com/pub/linuxppc/obsolete/sandpoint/
62 #include <linux/config.h>
63 #include <linux/stddef.h>
64 #include <linux/kernel.h>
65 #include <linux/init.h>
66 #include <linux/errno.h>
67 #include <linux/reboot.h>
68 #include <linux/pci.h>
69 #include <linux/kdev_t.h>
70 #include <linux/major.h>
71 #include <linux/blk.h>
72 #include <linux/console.h>
73 #include <linux/delay.h>
74 #include <linux/irq.h>
75 #include <linux/ide.h>
76 #include <linux/irq.h>
77 #include <linux/seq_file.h>
78 #include <linux/serial.h>
80 #include <asm/system.h>
81 #include <asm/pgtable.h>
86 #include <asm/machdep.h>
89 #include <asm/keyboard.h>
91 #include <asm/open_pic.h>
92 #include <asm/i8259.h>
94 #include <asm/bootinfo.h>
95 #include <asm/mpc10x.h>
96 #include <asm/pci-bridge.h>
97 #include <asm/ppcboot.h>
99 #include "sandpoint_serial.h"
101 #include "sandpoint.h"
109 extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
110 extern int pckbd_getkeycode(unsigned int scancode);
111 extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
113 extern char pckbd_unexpected_up(unsigned char keycode);
114 extern void pckbd_leds(unsigned char leds);
115 extern void pckbd_init_hw(void);
116 extern unsigned char pckbd_sysrq_xlate[128];
119 extern void gen550_progress(char *, unsigned short);
120 extern void gen550_init(int, struct serial_struct *);
122 unsigned char __res[sizeof (bd_t)];
124 static void sandpoint_halt(void);
126 #ifdef CONFIG_SERIAL_TEXT_DEBUG
127 #include <linux/serial.h>
128 #include <linux/serialP.h>
129 #include <linux/serial_reg.h>
130 #include <asm/serial.h>
132 static struct serial_state rs_table[RS_TABLE_SIZE] = {
133 SERIAL_PORT_DFNS /* Defined in <asm/serial.h> */
139 * Define all of the IRQ senses and polarities. Taken from the
140 * Sandpoint X3 User's manual.
142 static u_char sandpoint_openpic_initsenses[] __initdata = {
145 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 0: SIOINT */
146 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 2: PCI Slot 1 */
147 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 3: PCI Slot 2 */
148 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 4: PCI Slot 3 */
149 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 5: PCI Slot 4 */
150 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 8: IDE (INT C) */
151 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE) /* 9: IDE (INT D) */
153 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 17, EPIC IRQ 1 - PCI1 - flash*/
154 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 18, EPIC IRQ 2 - LAN*/
155 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 19, EPIC IRQ 3 - Not used*/
156 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 20, EPIC IRQ 4 - Not used*/
162 * Motorola SPS Sandpoint interrupt routing.
165 sandpoint_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
167 static char pci_irq_table[][4] =
169 * PCI IDSEL/INTPIN->INTLINE
175 {16, 0, 0, 0}, /* IDSEL 11 - i8259 on Windbond */
176 { 0, 0, 0, 0}, /* IDSEL 12 - unused */
177 {17, 18, 19, 20}, /* IDSEL 13 - PCI slot 1 */
178 {18, 19, 20, 17}, /* IDSEL 14 - PCI slot 2 */
179 {19, 20, 17, 18}, /* IDSEL 15 - PCI slot 3 */
180 {20, 17, 18, 19}, /* IDSEL 16 - PCI slot 4 */
183 const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
186 { 0, 0, 0, 0 }, /* IDSEL 13 - mini-PCI */
187 { 1, -1, 2, 0 }, /* IDSEL 14 - NEC USB2.0 */
188 { 3, 0, 0, 0 }, /* IDSEL 15 - ADM983 */
192 const long min_idsel = 13, max_idsel = 16, irqs_per_slot = 4;
194 return PCI_IRQ_TABLE_LOOKUP;
199 sandpoint_setup_winbond_83553(struct pci_controller *hose)
204 * Route IDE interrupts directly to the 8259's IRQ 14 & 15.
205 * We can't route the IDE interrupt to PCI INTC# or INTD# because those
206 * woule interfere with the PMC's INTC# and INTD# lines.
211 devfn = PCI_DEVFN(11, 0);
213 /* IDE Interrupt Routing Control */
214 early_write_config_byte(hose, 0, devfn, 0x43, 0xef);
216 /* PCI Interrupt Routing Control */
217 early_write_config_word(hose, 0, devfn, 0x44, 0x0000);
219 /* Want ISA memory cycles to be forwarded to PCI bus.
220 * ISA-to-PCI Addr Decoder Control.
222 early_write_config_byte(hose, 0, devfn, 0x48, 0xf0);
224 /* Enable RTC and Keyboard address locations. */
225 early_write_config_byte(hose, 0, devfn, 0x4d, 0x00);
227 /* Enable Port 92. */
228 early_write_config_byte(hose, 0, devfn, 0x4e, 0x06);
233 devfn = PCI_DEVFN(11, 1);
235 /* Put IDE controller into native mode (via PIR). */
236 early_write_config_byte(hose, 0, devfn, 0x09, 0x8f);
238 /* Init IRQ routing, enable both ports, disable fast 16, via
239 * IDE Control/Status Register.
241 early_write_config_dword(hose, 0, devfn, 0x40, 0x00ff0011);
245 #ifndef CONFIG_SANDPOINT_X3
246 /* On the sandpoint X2, we must avoid sending configuration cycles to
247 * device #12 (IDSEL addr = AD12).
250 sandpoint_exclude_device(u_char bus, u_char devfn)
253 if ((bus == 0) && (PCI_SLOT(devfn) == SANDPOINT_HOST_BRIDGE_IDSEL))
254 return PCIBIOS_DEVICE_NOT_FOUND;
256 return PCIBIOS_SUCCESSFUL;
259 printk("REX_DBG_PCI: dev-fun is %X:%X.\n",PCI_SLOT(devfn), PCI_FUNC(devfn));
261 if ((bus == 0) && (PCI_SLOT(devfn) == SANDPOINT_HOST_BRIDGE_IDSEL))
263 return PCIBIOS_DEVICE_NOT_FOUND;
267 return PCIBIOS_SUCCESSFUL;
274 sandpoint_find_bridges(void)
276 struct pci_controller *hose;
278 hose = pcibios_alloc_controller();
283 hose->first_busno = 0;
284 hose->last_busno = 0xff;
288 if (mpc10x_bridge_init(hose,
290 MPC10X_MEM_MAP_B, MPC10X_MAPB_EUMB_BASE) == 0) {
292 if (mpc10x_bridge_init(hose,
297 /* Do early winbond init, then scan PCI bus */
298 //sandpoint_setup_winbond_83553(hose);
299 #ifndef CONFIG_SANDPOINT_X3
300 ppc_md.pci_exclude_device = sandpoint_exclude_device;
302 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
304 ppc_md.pcibios_fixup = NULL;
305 ppc_md.pcibios_fixup_bus = NULL;
306 ppc_md.pci_swizzle = common_swizzle;
307 ppc_md.pci_map_irq = sandpoint_map_irq;
310 ppc_md.progress("Bridge init failed", 0x100);
311 printk("Host bridge init failed\n");
319 sandpoint_early_serial_map(void)
321 struct serial_struct serial_req;
323 /* Setup serial port access */
324 memset(&serial_req, 0, sizeof (serial_req));
325 serial_req.baud_base = BASE_BAUD;
329 serial_req.flags = ASYNC_BOOT_AUTOCONF;
330 serial_req.io_type = SERIAL_IO_MEM;
331 serial_req.iomem_base = (u_char *) SANDPOINT_SERIAL_0;
332 serial_req.iomem_reg_shift = 0;
334 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
335 gen550_init(0, &serial_req);
338 if (early_serial_setup(&serial_req) != 0)
339 printk("Early serial init of port 0 failed\n");
341 /* Assume early_serial_setup() doesn't modify serial_req */
344 serial_req.irq = 3; /* XXXX */
345 serial_req.iomem_base = (u_char *) SANDPOINT_SERIAL_1;
347 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
348 gen550_init(1, &serial_req);
351 if (early_serial_setup(&serial_req) != 0)
352 printk("Early serial init of port 1 failed\n");
357 sandpoint_setup_arch(void)
359 loops_per_jiffy = 100000000 / HZ;
361 #ifdef CONFIG_BLK_DEV_INITRD
363 ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
366 #ifdef CONFIG_ROOT_NFS
367 ROOT_DEV = to_kdev_t(0x00FF); /* /dev/nfs pseudo device */
369 ROOT_DEV = to_kdev_t(0x0301); /* /dev/hda1 IDE disk */
372 /* Lookup PCI host bridges */
373 sandpoint_find_bridges();
376 sandpoint_early_serial_map();
379 #ifdef CONFIG_DUMMY_CONSOLE
380 conswitchp = &dummy_con;
383 printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n");
385 /* DINK32 12.3 and below do not correctly enable any caches.
386 * We will do this now with good known values. Future versions
387 * of DINK32 are supposed to get this correct.
389 if (cur_cpu_spec[0]->cpu_features & CPU_FTR_SPEC7450)
390 /* 745x is different. We only want to pass along enable. */
392 else if (cur_cpu_spec[0]->cpu_features & CPU_FTR_L2CR)
393 /* All modules have 1MB of L2. We also assume that an
394 * L2 divisor of 3 will work.
396 _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
397 | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);
399 /* Untested right now. */
400 if (cur_cpu_spec[0]->cpu_features & CPU_FTR_L3CR) {
402 _set_L3CR(0x8f032000);
407 #define SANDPOINT_87308_CFG_ADDR 0x15c
408 #define SANDPOINT_87308_CFG_DATA 0x15d
410 #define SANDPOINT_87308_CFG_INB(addr, byte) { \
411 outb((addr), SANDPOINT_87308_CFG_ADDR); \
412 (byte) = inb(SANDPOINT_87308_CFG_DATA); \
415 #define SANDPOINT_87308_CFG_OUTB(addr, byte) { \
416 outb((addr), SANDPOINT_87308_CFG_ADDR); \
417 outb((byte), SANDPOINT_87308_CFG_DATA); \
420 #define SANDPOINT_87308_SELECT_DEV(dev_num) { \
421 SANDPOINT_87308_CFG_OUTB(0x07, (dev_num)); \
424 #define SANDPOINT_87308_DEV_ENABLE(dev_num) { \
425 SANDPOINT_87308_SELECT_DEV(dev_num); \
426 SANDPOINT_87308_CFG_OUTB(0x30, 0x01); \
430 * Initialize the ISA devices on the Nat'l PC87308VUL SuperIO chip.
433 sandpoint_setup_natl_87308(void)
438 * Enable all the devices on the Super I/O chip.
440 SANDPOINT_87308_SELECT_DEV(0x00); /* Select kbd logical device */
441 SANDPOINT_87308_CFG_OUTB(0xf0, 0x00); /* Set KBC clock to 8 Mhz */
442 SANDPOINT_87308_DEV_ENABLE(0x00); /* Enable keyboard */
443 SANDPOINT_87308_DEV_ENABLE(0x01); /* Enable mouse */
444 SANDPOINT_87308_DEV_ENABLE(0x02); /* Enable rtc */
445 SANDPOINT_87308_DEV_ENABLE(0x03); /* Enable fdc (floppy) */
446 SANDPOINT_87308_DEV_ENABLE(0x04); /* Enable parallel */
447 SANDPOINT_87308_DEV_ENABLE(0x05); /* Enable UART 2 */
448 SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
449 SANDPOINT_87308_DEV_ENABLE(0x06); /* Enable UART 1 */
450 SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
452 /* Set up floppy in PS/2 mode */
453 outb(0x09, SIO_CONFIG_RA);
454 reg = inb(SIO_CONFIG_RD);
455 reg = (reg & 0x3F) | 0x40;
456 outb(reg, SIO_CONFIG_RD);
457 outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
463 * Fix IDE interrupts.
466 sandpoint_fix_winbond_83553(void)
468 /* Make all 8259 interrupt level sensitive */
477 sandpoint_init2(void)
479 /* Do Sandpoint board specific initialization. */
481 sandpoint_fix_winbond_83553();
482 sandpoint_setup_natl_87308();
484 request_region(0x00, 0x20, "dma1");
485 request_region(0x20, 0x20, "pic1");
486 request_region(0x40, 0x20, "timer");
487 request_region(0x80, 0x10, "dma page reg");
488 request_region(0xa0, 0x20, "pic2");
489 request_region(0xc0, 0x20, "dma2");
495 * Interrupt setup and service. The i8259 is cascaded from EPIC IRQ0,
496 * IRQ1-4 map to PCI slots 1-4, IDE is on EPIC 7 and 8.
499 sandpoint_init_IRQ(void)
503 OpenPIC_InitSenses = sandpoint_openpic_initsenses;
504 OpenPIC_NumInitSenses = sizeof (sandpoint_openpic_initsenses);
507 * We need to tell openpic_set_sources where things actually are.
508 * mpc10x_common will setup OpenPIC_Addr at ioremap(EUMB phys base +
509 * EPIC offset (0x40000)); The EPIC IRQ Register Address Map -
510 * Interrupt Source Configuration Registers gives these numbers
511 * as offsets starting at 0x50200, we need to adjust occordinly.
515 #ifdef CONFIG_SANDPOINT_X3
517 /* Map serial interrupt 0 */
518 openpic_set_sources(0, 1, OpenPIC_Addr + 0x10200);
519 /* Map serial interrupts 2-5 */
520 openpic_set_sources(1, 4, OpenPIC_Addr + 0x10240);
521 /* Map serial interrupts 8-9 */
522 openpic_set_sources(5, 2, OpenPIC_Addr + 0x10300);
523 /* Skip reserved space and map i2c and DMA Ch[01] */
524 openpic_set_sources(7, 3, OpenPIC_Addr + 0x11020);
525 /* Skip reserved space and map Message Unit Interrupt (I2O) */
526 openpic_set_sources(10, 1, OpenPIC_Addr + 0x110C0);
528 openpic_set_sources(0, 138, NULL);
530 /* Map EPIC IRQs 0-3 */
531 openpic_set_sources(0, 5, OpenPIC_Addr + 0x10200);
532 /* Skip reserved space and map i2c and DMA Ch[01] */
533 openpic_set_sources(113, 3, OpenPIC_Addr + 0x11020);
534 /* Skip reserved space and map Message Unit Interrupt (I2O) */
535 openpic_set_sources(118, 1, OpenPIC_Addr + 0x110C0);
537 openpic_set_sources(121, 1, OpenPIC_Addr + 0x11120); //ttyS0
539 openpic_set_sources(122, 1, OpenPIC_Addr + 0x11140); //ttyS1 jackl
543 #if 0//by Musenki, cause it will panic!
544 openpic_set_sources(0, 32, NULL);
545 openpic_set_sources(129, 3, NULL);//I2C
546 openpic_set_sources(134, 1, NULL);//Mesg
547 openpic_set_sources(137, 2, NULL);//DUART
549 //openpic_init(1, 0, 0, -1);
551 /* The cascade is either on EPIC IRQ 1 or 2 on an X2 or on X3 it's
554 //openpic_hookup_cascade(SANDPOINT_SIO_IRQ, "8259 cascade to EPIC",
558 * openpic_init() has set up irq_desc[0-23] to be openpic
559 * interrupts. We need to set irq_desc[0-15] to be 8259 interrupts.
560 * We then need to request and enable the 8259 irq.
562 //for (i = 0; i < NUM_8259_INTERRUPTS; i++)
563 // irq_desc[i].handler = &i8259_pic;
566 * The EPIC allows for a read in the range of 0xFEF00000 ->
567 * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
569 //i8259_init(0xfef00000);
574 * Because the Sandpoint X2 has the i8259 cascade sharing an IRQ with a
575 * PCI device, if we have a possible cascade IRQ we need to see if the
576 * i8259 has something pending. The only issue here is that the cascade
577 * IRQs will get a higher priority than an OpenPIC one, but this should be
581 sandpoint_get_irq(struct pt_regs *regs)
583 int irq, cascade_irq;
588 if ((irq != 127)&&(irq != 2)&&(irq!=121))
589 printk("sandpoint_get_irq: irq = %d\n", irq);
591 //if (irq == SANDPOINT_SIO_IRQ)
595 cascade_irq = i8259_irq(regs);
597 if (cascade_irq != -1) {
601 } else if (irq == OPENPIC_VEC_SPURIOUS)
609 sandpoint_irq_cannonicalize(u32 irq)
618 static unsigned long __init
619 sandpoint_find_end_of_memory(void)
621 bd_t *bp = (bd_t *) __res;
626 printk("Total memory %d MB.\n", bp->bi_memsize);
627 return bp->bi_memsize;
630 /* This might be fixed in DINK32 12.4, or we'll have another
631 * way to determine the correct memory size anyhow. */
632 /* return mpc10x_get_mem_size(MPC10X_MEM_MAP_B); */
633 return 32 * 1024 * 1024;
637 sandpoint_map_io(void)
639 io_block_mapping(0xfc000000, 0xfc000000, 0x04000000, _PAGE_IO);
641 //rs_table[0].iomem_base = ioremap_base - 0x100000 + 0x4500;
645 * Due to Sandpoint X2 errata, the Port 92 will not work.
648 sandpoint_restart(char *cmd)
651 //printk("Jumping to start address...\n");
656 /* Set exception prefix high - to the firmware */
657 _nmask_and_or_msr(0, MSR_IP);
659 /* Reset system via Port 92 */
664 /* Interrupts and MMU off */
665 __asm__ ("mtspr 81, 0");
667 /* Interrupts and MMU off */
668 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
671 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
673 * * Trying to execute the next instruction at a non-existing address
674 * * should cause a machine check, resulting in reset
677 ((void (*)(void)) addr) ();
678 for (;;) ; /* Spin until reset happens */
682 sandpoint_power_off(void)
685 for (;;) ; /* No way to shut power off with software */
692 sandpoint_power_off();
697 sandpoint_show_cpuinfo(struct seq_file *m)
699 seq_printf(m, "vendor\t\t: Motorola SPS\n");
700 seq_printf(m, "machine\t\t: Sandpoint\n");
705 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
709 static int sandpoint_ide_ports_known = 0;
710 static ide_ioreg_t sandpoint_ide_regbase[MAX_HWIFS];
711 static ide_ioreg_t sandpoint_ide_ctl_regbase[MAX_HWIFS];
712 static ide_ioreg_t sandpoint_idedma_regbase;
715 sandpoint_ide_probe(void)
717 struct pci_dev *pdev = pci_find_device(PCI_VENDOR_ID_WINBOND,
718 PCI_DEVICE_ID_WINBOND_82C105,
722 sandpoint_ide_regbase[0] = pdev->resource[0].start;
723 sandpoint_ide_regbase[1] = pdev->resource[2].start;
724 sandpoint_ide_ctl_regbase[0] = pdev->resource[1].start;
725 sandpoint_ide_ctl_regbase[1] = pdev->resource[3].start;
726 sandpoint_idedma_regbase = pdev->resource[4].start;
729 sandpoint_ide_ports_known = 1;
733 /* The Sandpoint X3 allows the IDE interrupt to be directly connected
734 * from the Windbond (PCI INTC or INTD) to the serial EPIC. Someday
735 * we should try this, but it was easier to use the existing 83c553
736 * initialization than change it to route the different interrupts :-).
740 #define SANDPOINT_IDE_INT0 23 /* EPIC 7 */
741 #define SANDPOINT_IDE_INT1 24 /* EPIC 8 */
743 #define SANDPOINT_IDE_INT0 14 /* 8259 Test */
744 #define SANDPOINT_IDE_INT1 15 /* 8259 Test */
747 sandpoint_ide_default_irq(ide_ioreg_t base)
749 if (sandpoint_ide_ports_known == 0)
750 sandpoint_ide_probe();
752 if (base == sandpoint_ide_regbase[0])
753 return SANDPOINT_IDE_INT0;
754 else if (base == sandpoint_ide_regbase[1])
755 return SANDPOINT_IDE_INT1;
761 sandpoint_ide_default_io_base(int index)
763 if (sandpoint_ide_ports_known == 0)
764 sandpoint_ide_probe();
766 return sandpoint_ide_regbase[index];
770 sandpoint_ide_init_hwif_ports(hw_regs_t * hw, ide_ioreg_t data_port,
771 ide_ioreg_t ctrl_port, int *irq)
773 ide_ioreg_t reg = data_port;
774 unsigned int alt_status_base;
777 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
778 hw->io_ports[i] = reg++;
780 if (data_port == sandpoint_ide_regbase[0]) {
781 alt_status_base = sandpoint_ide_ctl_regbase[0] + 2;
783 } else if (data_port == sandpoint_ide_regbase[1]) {
784 alt_status_base = sandpoint_ide_ctl_regbase[1] + 2;
792 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
794 hw->io_ports[IDE_CONTROL_OFFSET] = alt_status_base;
805 * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
807 static __inline__ void
808 sandpoint_set_bat(void)
813 mtspr(DBAT1U, 0xf8000ffe);
814 mtspr(DBAT1L, 0xf800002a);
816 unsigned long bat3u, bat3l;
818 __asm__ __volatile__(" lis %0,0xf800\n \
824 sync ":"=r"(bat3u), "=r"(bat3l));
826 unsigned long bat3u, bat3l;
828 __asm__ __volatile__(
836 : "=r" (bat3u), "=r" (bat3l));
841 #ifdef CONFIG_SERIAL_TEXT_DEBUG
842 #include <linux/serial.h>
843 #include <linux/serialP.h>
844 #include <linux/serial_reg.h>
845 #include <asm/serial.h>
848 volatile unsigned char *com_port;
849 volatile unsigned char *com_port_lsr;
852 serial_writechar(char c)
854 while ((*com_port_lsr & UART_LSR_THRE) == 0)
860 sandpoint_progress(char *s, unsigned short hex)
865 com_port = (volatile unsigned char *) rs_table[0].port;
866 //com_port = (volatile unsigned char *) rs_table[1].port; //jackl
867 com_port_lsr = com_port + UART_LSR;
869 while ((c = *s++) != 0)
872 /* Most messages don't have a newline in them */
873 serial_writechar('\n');
874 serial_writechar('\r');
876 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
878 void calibrate_decr() {
891 //REX: to avoid slow time!
893 tb_ticks_per_jiffy = freq / HZ / divisor;
894 tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
899 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
900 unsigned long r6, unsigned long r7)
902 parse_bootinfo(find_bootinfo());
904 /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
905 * are non-zero, then we should use the board info from the bd_t
906 * structure and the cmdline pointed to by r6 instead of the
907 * information from birecs, if any. Otherwise, use the information
908 * from birecs as discovered by the preceeding call to
909 * parse_bootinfo(). This rule should work with both PPCBoot, which
910 * uses a bd_t board info structure, and the kernel boot wrapper,
914 /* copy board info structure */
915 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
917 /* copy command line */
918 *(char *) (r7 + KERNELBASE) = 0;
919 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
921 #ifdef CONFIG_BLK_DEV_INITRD
922 /* take care of initrd if we have one */
924 initrd_start = r4 + KERNELBASE;
925 initrd_end = r5 + KERNELBASE;
927 #endif /* CONFIG_BLK_DEV_INITRD */
929 /* Map in board regs, etc. */
933 isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
934 isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
935 pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
936 ISA_DMA_THRESHOLD = 0x00ffffff;
937 DMA_MODE_READ = 0x44;
938 DMA_MODE_WRITE = 0x48;
940 ppc_md.setup_arch = sandpoint_setup_arch;
941 ppc_md.show_cpuinfo = sandpoint_show_cpuinfo;
942 //ppc_md.irq_cannonicalize = sandpoint_irq_cannonicalize;
943 ppc_md.init_IRQ = sandpoint_init_IRQ;
944 //ppc_md.get_irq = openpic_get_irq;
945 ppc_md.get_irq = sandpoint_get_irq;
946 ppc_md.init = sandpoint_init2;
948 ppc_md.restart = sandpoint_restart;
949 ppc_md.power_off = sandpoint_power_off;
950 ppc_md.halt = sandpoint_halt;
952 ppc_md.find_end_of_memory = sandpoint_find_end_of_memory;
953 ppc_md.setup_io_mappings = sandpoint_map_io;
954 ppc_md.calibrate_decr = calibrate_decr;
956 TODC_INIT(TODC_TYPE_PC97307, 0x70, 0x00, 0x71, 8);
957 ppc_md.time_init = todc_time_init;
958 ppc_md.set_rtc_time = todc_set_rtc_time;
959 ppc_md.get_rtc_time = todc_get_rtc_time;
960 ppc_md.calibrate_decr = todc_calibrate_decr;
962 ppc_md.nvram_read_val = todc_mc146818_read_val;
963 ppc_md.nvram_write_val = todc_mc146818_write_val;
967 #ifdef CONFIG_SERIAL_TEXT_DEBUG
968 //ppc_md.progress = gen550_progress;
969 ppc_md.progress = sandpoint_progress;
971 ppc_md.early_serial_map = sandpoint_early_serial_map;
975 ppc_md.kbd_setkeycode = pckbd_setkeycode;
976 ppc_md.kbd_getkeycode = pckbd_getkeycode;
977 ppc_md.kbd_translate = pckbd_translate;
978 ppc_md.kbd_unexpected_up = pckbd_unexpected_up;
979 ppc_md.kbd_leds = pckbd_leds;
980 ppc_md.kbd_init_hw = pckbd_init_hw;
981 #ifdef CONFIG_MAGIC_SYSRQ
982 ppc_md.ppc_kbd_sysrq_xlate = pckbd_sysrq_xlate;
987 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
988 ppc_ide_md.default_irq = sandpoint_ide_default_irq;
989 ppc_ide_md.default_io_base = sandpoint_ide_default_io_base;
990 ppc_ide_md.ide_init_hwif = sandpoint_ide_init_hwif_ports;