2 * arch/ppc/platforms/sandpoint.c
4 * Board setup routines for the Motorola SPS Sandpoint Test Platform.
6 * Author: Mark A. Greer
9 * 2000-2003 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
16 * This file adds support for the Motorola SPS Sandpoint Test Platform.
17 * These boards have a PPMC slot for the processor so any combination
18 * of cpu and host bridge can be attached. This port is for an 8240 PPMC
19 * module from Motorola SPS and other closely related cpu/host bridge
20 * combinations (e.g., 750/755/7400 with MPC107 host bridge).
21 * The sandpoint itself has a Windbond 83c553 (PCI-ISA bridge, 2 DMA ctlrs, 2
22 * cascaded 8259 interrupt ctlrs, 8254 Timer/Counter, and an IDE ctlr), a
23 * National 87308 (RTC, 2 UARTs, Keyboard & mouse ctlrs, and a floppy ctlr),
24 * and 4 PCI slots (only 2 of which are usable; the other 2 are keyed for 3.3V
27 * The firmware on the sandpoint is called DINK (not my acronym :). This port
28 * depends on DINK to do some basic initialization (e.g., initialize the memory
29 * ctlr) and to ensure that the processor is using MAP B (CHRP map).
31 * The switch settings for the Sandpoint board MUST be as follows:
37 * 'down' is in the direction from the PCI slots towards the PPMC slot;
38 * 'up' is in the direction from the PPMC slot towards the PCI slots.
39 * Be careful, the way the sandpoint board is installed in XT chasses will
40 * make the directions reversed.
42 * Since Motorola listened to our suggestions for improvement, we now have
43 * the Sandpoint X3 board. All of the PCI slots are available, it uses
44 * the serial interrupt interface (just a hardware thing we need to
45 * configure properly).
47 * Use the default X3 switch settings. The interrupts are then:
49 * 0 SIOINT (8259, active low)
54 * 7 Winbond INTC (IDE interrupt)
55 * 8 Winbond INTD (IDE interrupt)
57 * It is important to note that this code only supports the Sandpoint X3
58 * (all flavors) platform, and it does not support the X2 anymore. Code
59 * that at one time worked on the X2 can be found at:
60 * ftp://source.mvista.com/pub/linuxppc/obsolete/sandpoint/
62 #include <linux/config.h>
63 #include <linux/stddef.h>
64 #include <linux/kernel.h>
65 #include <linux/init.h>
66 #include <linux/errno.h>
67 #include <linux/reboot.h>
68 #include <linux/pci.h>
69 #include <linux/kdev_t.h>
70 #include <linux/major.h>
71 #include <linux/blk.h>
72 #include <linux/console.h>
73 #include <linux/delay.h>
74 #include <linux/irq.h>
75 #include <linux/ide.h>
76 #include <linux/irq.h>
77 #include <linux/seq_file.h>
78 #include <linux/serial.h>
80 #include <asm/system.h>
81 #include <asm/pgtable.h>
86 #include <asm/machdep.h>
89 #include <asm/keyboard.h>
91 #include <asm/open_pic.h>
92 #include <asm/i8259.h>
94 #include <asm/bootinfo.h>
95 #include <asm/mpc10x.h>
96 #include <asm/pci-bridge.h>
97 #include <asm/ppcboot.h>
99 #include "sandpoint_serial.h"
101 extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
102 extern int pckbd_getkeycode(unsigned int scancode);
103 extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
105 extern char pckbd_unexpected_up(unsigned char keycode);
106 extern void pckbd_leds(unsigned char leds);
107 extern void pckbd_init_hw(void);
108 extern unsigned char pckbd_sysrq_xlate[128];
110 extern void gen550_progress(char *, unsigned short);
111 extern void gen550_init(int, struct serial_struct *);
113 unsigned char __res[sizeof (bd_t)];
115 static void sandpoint_halt(void);
118 * Define all of the IRQ senses and polarities. Taken from the
119 * Sandpoint X3 User's manual.
121 static u_char sandpoint_openpic_initsenses[] __initdata = {
122 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 0: SIOINT */
123 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 2: PCI Slot 1 */
124 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 3: PCI Slot 2 */
125 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 4: PCI Slot 3 */
126 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 5: PCI Slot 4 */
127 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 8: IDE (INT C) */
128 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE) /* 9: IDE (INT D) */
132 * Motorola SPS Sandpoint interrupt routing.
135 sandpoint_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
137 static char pci_irq_table[][4] =
139 * PCI IDSEL/INTPIN->INTLINE
143 {16, 0, 0, 0}, /* IDSEL 11 - i8259 on Windbond */
144 { 0, 0, 0, 0}, /* IDSEL 12 - unused */
145 {17, 18, 19, 20}, /* IDSEL 13 - PCI slot 1 */
146 {18, 19, 20, 17}, /* IDSEL 14 - PCI slot 2 */
147 {19, 20, 17, 18}, /* IDSEL 15 - PCI slot 3 */
148 {20, 17, 18, 19}, /* IDSEL 16 - PCI slot 4 */
151 const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
152 return PCI_IRQ_TABLE_LOOKUP;
156 sandpoint_setup_winbond_83553(struct pci_controller *hose)
161 * Route IDE interrupts directly to the 8259's IRQ 14 & 15.
162 * We can't route the IDE interrupt to PCI INTC# or INTD# because those
163 * woule interfere with the PMC's INTC# and INTD# lines.
168 devfn = PCI_DEVFN(11, 0);
170 /* IDE Interrupt Routing Control */
171 early_write_config_byte(hose, 0, devfn, 0x43, 0xef);
173 /* PCI Interrupt Routing Control */
174 early_write_config_word(hose, 0, devfn, 0x44, 0x0000);
176 /* Want ISA memory cycles to be forwarded to PCI bus.
177 * ISA-to-PCI Addr Decoder Control.
179 early_write_config_byte(hose, 0, devfn, 0x48, 0xf0);
181 /* Enable RTC and Keyboard address locations. */
182 early_write_config_byte(hose, 0, devfn, 0x4d, 0x00);
184 /* Enable Port 92. */
185 early_write_config_byte(hose, 0, devfn, 0x4e, 0x06);
190 devfn = PCI_DEVFN(11, 1);
192 /* Put IDE controller into native mode (via PIR). */
193 early_write_config_byte(hose, 0, devfn, 0x09, 0x8f);
195 /* Init IRQ routing, enable both ports, disable fast 16, via
196 * IDE Control/Status Register.
198 early_write_config_dword(hose, 0, devfn, 0x40, 0x00ff0011);
202 sandpoint_find_bridges(void)
204 struct pci_controller *hose;
206 hose = pcibios_alloc_controller();
211 hose->first_busno = 0;
212 hose->last_busno = 0xff;
214 if (mpc10x_bridge_init(hose,
216 MPC10X_MEM_MAP_B, MPC10X_MAPB_EUMB_BASE) == 0) {
218 /* Do early winbond init, then scan PCI bus */
219 sandpoint_setup_winbond_83553(hose);
220 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
222 ppc_md.pcibios_fixup = NULL;
223 ppc_md.pcibios_fixup_bus = NULL;
224 ppc_md.pci_swizzle = common_swizzle;
225 ppc_md.pci_map_irq = sandpoint_map_irq;
228 ppc_md.progress("Bridge init failed", 0x100);
229 printk("Host bridge init failed\n");
237 sandpoint_early_serial_map(void)
239 struct serial_struct serial_req;
241 /* Setup serial port access */
242 memset(&serial_req, 0, sizeof (serial_req));
243 serial_req.baud_base = BASE_BAUD;
247 serial_req.flags = ASYNC_BOOT_AUTOCONF;
248 serial_req.io_type = SERIAL_IO_MEM;
249 serial_req.iomem_base = (u_char *) SANDPOINT_SERIAL_0;
250 serial_req.iomem_reg_shift = 0;
252 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
253 gen550_init(0, &serial_req);
256 if (early_serial_setup(&serial_req) != 0)
257 printk("Early serial init of port 0 failed\n");
259 /* Assume early_serial_setup() doesn't modify serial_req */
262 serial_req.irq = 3; /* XXXX */
263 serial_req.iomem_base = (u_char *) SANDPOINT_SERIAL_1;
265 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
266 gen550_init(1, &serial_req);
269 if (early_serial_setup(&serial_req) != 0)
270 printk("Early serial init of port 1 failed\n");
275 sandpoint_setup_arch(void)
277 loops_per_jiffy = 100000000 / HZ;
279 #ifdef CONFIG_BLK_DEV_INITRD
281 ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
284 #ifdef CONFIG_ROOT_NFS
285 ROOT_DEV = to_kdev_t(0x00FF); /* /dev/nfs pseudo device */
287 ROOT_DEV = to_kdev_t(0x0301); /* /dev/hda1 IDE disk */
290 /* Lookup PCI host bridges */
291 sandpoint_find_bridges();
294 sandpoint_early_serial_map();
297 #ifdef CONFIG_DUMMY_CONSOLE
298 conswitchp = &dummy_con;
301 printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n");
303 /* DINK32 12.3 and below do not correctly enable any caches.
304 * We will do this now with good known values. Future versions
305 * of DINK32 are supposed to get this correct.
307 if (cur_cpu_spec[0]->cpu_features & CPU_FTR_SPEC7450)
308 /* 745x is different. We only want to pass along enable. */
310 else if (cur_cpu_spec[0]->cpu_features & CPU_FTR_L2CR)
311 /* All modules have 1MB of L2. We also assume that an
312 * L2 divisor of 3 will work.
314 _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
315 | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);
317 /* Untested right now. */
318 if (cur_cpu_spec[0]->cpu_features & CPU_FTR_L3CR) {
320 _set_L3CR(0x8f032000);
325 #define SANDPOINT_87308_CFG_ADDR 0x15c
326 #define SANDPOINT_87308_CFG_DATA 0x15d
328 #define SANDPOINT_87308_CFG_INB(addr, byte) { \
329 outb((addr), SANDPOINT_87308_CFG_ADDR); \
330 (byte) = inb(SANDPOINT_87308_CFG_DATA); \
333 #define SANDPOINT_87308_CFG_OUTB(addr, byte) { \
334 outb((addr), SANDPOINT_87308_CFG_ADDR); \
335 outb((byte), SANDPOINT_87308_CFG_DATA); \
338 #define SANDPOINT_87308_SELECT_DEV(dev_num) { \
339 SANDPOINT_87308_CFG_OUTB(0x07, (dev_num)); \
342 #define SANDPOINT_87308_DEV_ENABLE(dev_num) { \
343 SANDPOINT_87308_SELECT_DEV(dev_num); \
344 SANDPOINT_87308_CFG_OUTB(0x30, 0x01); \
348 * Initialize the ISA devices on the Nat'l PC87308VUL SuperIO chip.
351 sandpoint_setup_natl_87308(void)
356 * Enable all the devices on the Super I/O chip.
358 SANDPOINT_87308_SELECT_DEV(0x00); /* Select kbd logical device */
359 SANDPOINT_87308_CFG_OUTB(0xf0, 0x00); /* Set KBC clock to 8 Mhz */
360 SANDPOINT_87308_DEV_ENABLE(0x00); /* Enable keyboard */
361 SANDPOINT_87308_DEV_ENABLE(0x01); /* Enable mouse */
362 SANDPOINT_87308_DEV_ENABLE(0x02); /* Enable rtc */
363 SANDPOINT_87308_DEV_ENABLE(0x03); /* Enable fdc (floppy) */
364 SANDPOINT_87308_DEV_ENABLE(0x04); /* Enable parallel */
365 SANDPOINT_87308_DEV_ENABLE(0x05); /* Enable UART 2 */
366 SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
367 SANDPOINT_87308_DEV_ENABLE(0x06); /* Enable UART 1 */
368 SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
370 /* Set up floppy in PS/2 mode */
371 outb(0x09, SIO_CONFIG_RA);
372 reg = inb(SIO_CONFIG_RD);
373 reg = (reg & 0x3F) | 0x40;
374 outb(reg, SIO_CONFIG_RD);
375 outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
381 * Fix IDE interrupts.
384 sandpoint_fix_winbond_83553(void)
386 /* Make all 8259 interrupt level sensitive */
394 sandpoint_init2(void)
396 /* Do Sandpoint board specific initialization. */
397 sandpoint_fix_winbond_83553();
398 sandpoint_setup_natl_87308();
400 request_region(0x00, 0x20, "dma1");
401 request_region(0x20, 0x20, "pic1");
402 request_region(0x40, 0x20, "timer");
403 request_region(0x80, 0x10, "dma page reg");
404 request_region(0xa0, 0x20, "pic2");
405 request_region(0xc0, 0x20, "dma2");
411 * Interrupt setup and service. The i8259 is cascaded from EPIC IRQ0,
412 * IRQ1-4 map to PCI slots 1-4, IDE is on EPIC 7 and 8.
415 sandpoint_init_IRQ(void)
419 OpenPIC_InitSenses = sandpoint_openpic_initsenses;
420 OpenPIC_NumInitSenses = sizeof (sandpoint_openpic_initsenses);
423 * We need to tell openpic_set_sources where things actually are.
424 * mpc10x_common will setup OpenPIC_Addr at ioremap(EUMB phys base +
425 * EPIC offset (0x40000)); The EPIC IRQ Register Address Map -
426 * Interrupt Source Configuration Registers gives these numbers
427 * as offsets starting at 0x50200, we need to adjust occordinly.
430 /* Map serial interrupt 0 */
431 openpic_set_sources(0, 1, OpenPIC_Addr + 0x10200);
432 /* Map serial interrupts 2-5 */
433 openpic_set_sources(1, 4, OpenPIC_Addr + 0x10240);
434 /* Map serial interrupts 8-9 */
435 openpic_set_sources(5, 2, OpenPIC_Addr + 0x10300);
436 /* Skip reserved space and map i2c and DMA Ch[01] */
437 openpic_set_sources(7, 3, OpenPIC_Addr + 0x11020);
438 /* Skip reserved space and map Message Unit Interrupt (I2O) */
439 openpic_set_sources(10, 1, OpenPIC_Addr + 0x110C0);
441 openpic_init(NUM_8259_INTERRUPTS);
442 /* The cascade is on EPIC IRQ 0 (Linux IRQ 16). */
443 openpic_hookup_cascade(16, "8259 cascade to EPIC", &i8259_irq);
446 * openpic_init() has set up irq_desc[0-23] to be openpic
447 * interrupts. We need to set irq_desc[0-15] to be 8259 interrupts.
448 * We then need to request and enable the 8259 irq.
450 for (i = 0; i < NUM_8259_INTERRUPTS; i++)
451 irq_desc[i].handler = &i8259_pic;
454 * The EPIC allows for a read in the range of 0xFEF00000 ->
455 * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
457 i8259_init(0xfef00000);
461 sandpoint_irq_cannonicalize(u32 irq)
469 static unsigned long __init
470 sandpoint_find_end_of_memory(void)
472 bd_t *bp = (bd_t *) __res;
475 return bp->bi_memsize;
477 /* This might be fixed in DINK32 12.4, or we'll have another
478 * way to determine the correct memory size anyhow. */
479 /* return mpc10x_get_mem_size(MPC10X_MEM_MAP_B); */
480 return 32 * 1024 * 1024;
484 sandpoint_map_io(void)
486 io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
490 sandpoint_restart(char *cmd)
494 /* Set exception prefix high - to the firmware */
495 _nmask_and_or_msr(0, MSR_IP);
497 /* Reset system via Port 92 */
500 for (;;) ; /* Spin until reset happens */
504 sandpoint_power_off(void)
507 for (;;) ; /* No way to shut power off with software */
514 sandpoint_power_off();
519 sandpoint_show_cpuinfo(struct seq_file *m)
521 seq_printf(m, "vendor\t\t: Motorola SPS\n");
522 seq_printf(m, "machine\t\t: Sandpoint\n");
527 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
531 static int sandpoint_ide_ports_known = 0;
532 static ide_ioreg_t sandpoint_ide_regbase[MAX_HWIFS];
533 static ide_ioreg_t sandpoint_ide_ctl_regbase[MAX_HWIFS];
534 static ide_ioreg_t sandpoint_idedma_regbase;
537 sandpoint_ide_probe(void)
539 struct pci_dev *pdev = pci_find_device(PCI_VENDOR_ID_WINBOND,
540 PCI_DEVICE_ID_WINBOND_82C105,
544 sandpoint_ide_regbase[0] = pdev->resource[0].start;
545 sandpoint_ide_regbase[1] = pdev->resource[2].start;
546 sandpoint_ide_ctl_regbase[0] = pdev->resource[1].start;
547 sandpoint_ide_ctl_regbase[1] = pdev->resource[3].start;
548 sandpoint_idedma_regbase = pdev->resource[4].start;
551 sandpoint_ide_ports_known = 1;
555 /* The Sandpoint X3 allows the IDE interrupt to be directly connected
556 * from the Windbond (PCI INTC or INTD) to the serial EPIC. Someday
557 * we should try this, but it was easier to use the existing 83c553
558 * initialization than change it to route the different interrupts :-).
562 #define SANDPOINT_IDE_INT0 23 /* EPIC 7 */
563 #define SANDPOINT_IDE_INT1 24 /* EPIC 8 */
565 #define SANDPOINT_IDE_INT0 14 /* 8259 Test */
566 #define SANDPOINT_IDE_INT1 15 /* 8259 Test */
569 sandpoint_ide_default_irq(ide_ioreg_t base)
571 if (sandpoint_ide_ports_known == 0)
572 sandpoint_ide_probe();
574 if (base == sandpoint_ide_regbase[0])
575 return SANDPOINT_IDE_INT0;
576 else if (base == sandpoint_ide_regbase[1])
577 return SANDPOINT_IDE_INT1;
583 sandpoint_ide_default_io_base(int index)
585 if (sandpoint_ide_ports_known == 0)
586 sandpoint_ide_probe();
588 return sandpoint_ide_regbase[index];
592 sandpoint_ide_init_hwif_ports(hw_regs_t * hw, ide_ioreg_t data_port,
593 ide_ioreg_t ctrl_port, int *irq)
595 ide_ioreg_t reg = data_port;
596 unsigned int alt_status_base;
599 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
600 hw->io_ports[i] = reg++;
602 if (data_port == sandpoint_ide_regbase[0]) {
603 alt_status_base = sandpoint_ide_ctl_regbase[0] + 2;
605 } else if (data_port == sandpoint_ide_regbase[1]) {
606 alt_status_base = sandpoint_ide_ctl_regbase[1] + 2;
614 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
616 hw->io_ports[IDE_CONTROL_OFFSET] = alt_status_base;
626 * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
628 static __inline__ void
629 sandpoint_set_bat(void)
633 mtspr(DBAT1U, 0xf8000ffe);
634 mtspr(DBAT1L, 0xf800002a);
637 unsigned long bat3u, bat3l;
639 __asm__ __volatile__(" lis %0,0xf800\n \
645 sync ":"=r"(bat3u), "=r"(bat3l));
652 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
653 unsigned long r6, unsigned long r7)
655 parse_bootinfo(find_bootinfo());
657 /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
658 * are non-zero, then we should use the board info from the bd_t
659 * structure and the cmdline pointed to by r6 instead of the
660 * information from birecs, if any. Otherwise, use the information
661 * from birecs as discovered by the preceeding call to
662 * parse_bootinfo(). This rule should work with both PPCBoot, which
663 * uses a bd_t board info structure, and the kernel boot wrapper,
667 /* copy board info structure */
668 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
670 /* copy command line */
671 *(char *) (r7 + KERNELBASE) = 0;
672 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
674 #ifdef CONFIG_BLK_DEV_INITRD
675 /* take care of initrd if we have one */
677 initrd_start = r4 + KERNELBASE;
678 initrd_end = r5 + KERNELBASE;
680 #endif /* CONFIG_BLK_DEV_INITRD */
682 /* Map in board regs, etc. */
685 isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
686 isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
687 pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
688 ISA_DMA_THRESHOLD = 0x00ffffff;
689 DMA_MODE_READ = 0x44;
690 DMA_MODE_WRITE = 0x48;
692 ppc_md.setup_arch = sandpoint_setup_arch;
693 ppc_md.show_cpuinfo = sandpoint_show_cpuinfo;
694 ppc_md.irq_cannonicalize = sandpoint_irq_cannonicalize;
695 ppc_md.init_IRQ = sandpoint_init_IRQ;
696 ppc_md.get_irq = openpic_get_irq;
697 ppc_md.init = sandpoint_init2;
699 ppc_md.restart = sandpoint_restart;
700 ppc_md.power_off = sandpoint_power_off;
701 ppc_md.halt = sandpoint_halt;
703 ppc_md.find_end_of_memory = sandpoint_find_end_of_memory;
704 ppc_md.setup_io_mappings = sandpoint_map_io;
706 TODC_INIT(TODC_TYPE_PC97307, 0x70, 0x00, 0x71, 8);
707 ppc_md.time_init = todc_time_init;
708 ppc_md.set_rtc_time = todc_set_rtc_time;
709 ppc_md.get_rtc_time = todc_get_rtc_time;
710 ppc_md.calibrate_decr = todc_calibrate_decr;
712 ppc_md.nvram_read_val = todc_mc146818_read_val;
713 ppc_md.nvram_write_val = todc_mc146818_write_val;
716 #ifdef CONFIG_SERIAL_TEXT_DEBUG
717 ppc_md.progress = gen550_progress;
719 ppc_md.early_serial_map = sandpoint_early_serial_map;
723 ppc_md.kbd_setkeycode = pckbd_setkeycode;
724 ppc_md.kbd_getkeycode = pckbd_getkeycode;
725 ppc_md.kbd_translate = pckbd_translate;
726 ppc_md.kbd_unexpected_up = pckbd_unexpected_up;
727 ppc_md.kbd_leds = pckbd_leds;
728 ppc_md.kbd_init_hw = pckbd_init_hw;
729 #ifdef CONFIG_MAGIC_SYSRQ
730 ppc_md.ppc_kbd_sysrq_xlate = pckbd_sysrq_xlate;
735 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
736 ppc_ide_md.default_irq = sandpoint_ide_default_irq;
737 ppc_ide_md.default_io_base = sandpoint_ide_default_io_base;
738 ppc_ide_md.ide_init_hwif = sandpoint_ide_init_hwif_ports;