2 * BK Id: SCCS/s.spd8xx.h 1.12 08/13/02 21:52:55 paulus
5 * Speech Design SPD8xxTS board specific definitions
7 * Copyright (c) 2000,2001 Wolfgang Denk (wd@denx.de)
11 #ifndef __ASM_SPD8XX_H__
12 #define __ASM_SPD8XX_H__
14 #include <linux/config.h>
16 #include <asm/ppcboot.h>
18 #define SPD_IMMR_BASE 0xFFF00000 /* phys. addr of IMMR */
19 #define SPD_IMAP_SIZE (64 * 1024) /* size of mapped area */
21 #define IMAP_ADDR SPD_IMMR_BASE /* physical base address of IMMR area */
22 #define IMAP_SIZE SPD_IMAP_SIZE /* mapped size of IMMR area */
24 #define PCMCIA_MEM_ADDR ((uint)0xFE100000)
25 #define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
27 #define IDE0_INTERRUPT 10 /* = IRQ5 */
28 #define IDE1_INTERRUPT 12 /* = IRQ6 */
29 #define CPM_INTERRUPT 13 /* = SIU_LEVEL6 (was: SIU_LEVEL2) */
31 /* override the default number of IDE hardware interfaces */
35 * Definitions for IDE0 Interface
37 #define IDE0_BASE_OFFSET 0x0000 /* Offset in PCMCIA memory */
38 #define IDE0_DATA_REG_OFFSET 0x0000
39 #define IDE0_ERROR_REG_OFFSET 0x0081
40 #define IDE0_NSECTOR_REG_OFFSET 0x0082
41 #define IDE0_SECTOR_REG_OFFSET 0x0083
42 #define IDE0_LCYL_REG_OFFSET 0x0084
43 #define IDE0_HCYL_REG_OFFSET 0x0085
44 #define IDE0_SELECT_REG_OFFSET 0x0086
45 #define IDE0_STATUS_REG_OFFSET 0x0087
46 #define IDE0_CONTROL_REG_OFFSET 0x0106
47 #define IDE0_IRQ_REG_OFFSET 0x000A /* not used */
50 * Definitions for IDE1 Interface
52 #define IDE1_BASE_OFFSET 0x0C00 /* Offset in PCMCIA memory */
53 #define IDE1_DATA_REG_OFFSET 0x0000
54 #define IDE1_ERROR_REG_OFFSET 0x0081
55 #define IDE1_NSECTOR_REG_OFFSET 0x0082
56 #define IDE1_SECTOR_REG_OFFSET 0x0083
57 #define IDE1_LCYL_REG_OFFSET 0x0084
58 #define IDE1_HCYL_REG_OFFSET 0x0085
59 #define IDE1_SELECT_REG_OFFSET 0x0086
60 #define IDE1_STATUS_REG_OFFSET 0x0087
61 #define IDE1_CONTROL_REG_OFFSET 0x0106
62 #define IDE1_IRQ_REG_OFFSET 0x000A /* not used */
64 /* We don't use the 8259.
66 #define NR_8259_INTS 0
68 #endif /* __ASM_SPD8XX_H__ */
69 #endif /* __KERNEL__ */