2 * arch/ppc64/kernel/cputable.c
4 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
6 * Modifications for ppc64:
7 * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
15 #include <linux/config.h>
16 #include <linux/string.h>
17 #include <linux/sched.h>
18 #include <linux/threads.h>
19 #include <linux/init.h>
20 #include <asm/cputable.h>
22 struct cpu_spec* cur_cpu_spec = NULL;
24 extern void __setup_cpu_power3(unsigned long offset, struct cpu_spec* spec);
25 extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec);
28 /* We only set the altivec features if the kernel was compiled with altivec
32 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
33 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
35 #define CPU_FTR_ALTIVEC_COMP 0
36 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0
39 struct cpu_spec cpu_specs[] = {
41 0xffff0000, 0x00400000, "Power3 (630)",
42 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
43 CPU_FTR_DABR | CPU_FTR_IABR,
50 0xffff0000, 0x00410000, "Power3 (630+)",
51 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
52 CPU_FTR_DABR | CPU_FTR_IABR,
59 0xffff0000, 0x00330000, "Northstar",
60 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
61 CPU_FTR_DABR | CPU_FTR_IABR,
68 0xffff0000, 0x00340000, "Pulsar",
69 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
70 CPU_FTR_DABR | CPU_FTR_IABR,
77 0xffff0000, 0x00360000, "I-star",
78 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
79 CPU_FTR_DABR | CPU_FTR_IABR,
86 0xffff0000, 0x00370000, "S-star",
87 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
88 CPU_FTR_DABR | CPU_FTR_IABR,
95 0xffff0000, 0x00350000, "Power4",
96 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
97 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_DABR,
104 0xffff0000, 0x00380000, "Power4+",
105 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
106 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_DABR,
113 0xffff0000, 0x00390000, "PPC970",
114 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
115 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP,
116 COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP,
122 0xffff0000, 0x003a0000, "Power5",
123 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
124 CPU_FTR_PPCAS_ARCH_V2,
130 { /* default match */
131 0x00000000, 0x00000000, "(Power4-Compatible)",
132 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
133 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_DABR,
141 firmware_feature_t firmware_features_table[FIRMWARE_MAX_FEATURES] = {
142 {FW_FEATURE_PFT, "hcall-pft"},
143 {FW_FEATURE_TCE, "hcall-tce"},
144 {FW_FEATURE_SPRG0, "hcall-sprg0"},
145 {FW_FEATURE_DABR, "hcall-dabr"},
146 {FW_FEATURE_COPY, "hcall-copy"},
147 {FW_FEATURE_ASR, "hcall-asr"},
148 {FW_FEATURE_DEBUG, "hcall-debug"},
149 {FW_FEATURE_PERF, "hcall-perf"},
150 {FW_FEATURE_DUMP, "hcall-dump"},
151 {FW_FEATURE_INTERRUPT, "hcall-interrupt"},
152 {FW_FEATURE_MIGRATE, "hcall-migrate"},
153 {FW_FEATURE_PERFMON, "hcall-perfmon"},
154 {FW_FEATURE_CRQ, "hcall-crq"},
155 {FW_FEATURE_VIO, "hcall-vio"},
156 {FW_FEATURE_RDMA, "hcall-rdma"},
157 {FW_FEATURE_LLAN, "hcall-lLAN"},
158 {FW_FEATURE_BULK, "hcall-bulk"},
159 {FW_FEATURE_XDABR, "hcall-xdabr"},
160 {FW_FEATURE_MULTITCE, "hcall-multi-tce"},
161 {FW_FEATURE_SPLPAR, "hcall-splpar"},