arch/ppc64/kernel/pSeries_pci.c

   1 /*
   2  * pSeries_pci.c
   3  *
   4  * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
   5  *
   6  * pSeries specific routines for PCI.
   7  *
   8  * Based on code from pci.c and chrp_pci.c
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/pci.h>
  27 #include <linux/delay.h>
  28 #include <linux/string.h>
  29 #include <linux/init.h>
  30 #include <linux/bootmem.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/irq.h>
  35 #include <asm/prom.h>
  36 #include <asm/machdep.h>
  37 #include <asm/init.h>
  38 #include <asm/pci-bridge.h>
  39 #include <asm/ppcdebug.h>
  40 #include <asm/naca.h>
  41 #include <asm/pci_dma.h>
  42
  43 #include "xics.h"
  44 #include "open_pic.h"
  45 #include "pci.h"
  46
  47 extern struct device_node *allnodes;
  48
  49 /*******************************************************************
  50  * Forward declares of prototypes.
  51  *******************************************************************/
  52 unsigned long find_and_init_phbs(void);
  53 struct pci_controller* alloc_phb(struct device_node *dev, char *model, unsigned int addr_size_words) ;
  54 void pSeries_pcibios_fixup(void);
  55 static int rtas_fake_read(struct device_node *dn, int offset, int nbytes, unsigned long *returnval);
  56
  57 /* RTAS tokens */
  58 static int read_pci_config;
  59 static int write_pci_config;
  60 static int ibm_read_pci_config;
  61 static int ibm_write_pci_config;
  62
  63 static int s7a_workaround;
  64
  65 /******************************************************************************
  66  *
  67  * pSeries I/O Operations to access the PCI configuration space.
  68  *
  69  *****************************************************************************/
  70 #define RTAS_PCI_READ_OP(size, type, nbytes) \
  71 int __chrp \
  72 rtas_read_config_##size(struct device_node *dn, int offset, type val) {  \
  73         unsigned long returnval = ~0L; \
  74         unsigned long buid; \
  75         unsigned int addr; \
  76         int ret; \
  77          \
  78         if (dn == NULL) { \
  79                 ret = -2; \
  80         } else if (dn->status) { \
  81                 ret = -1; \
  82         } else { \
  83                 addr = (dn->busno << 16) | (dn->devfn << 8) | offset; \
  84                 buid = dn->phb->buid; \
  85                 if (buid) { \
  86                         ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval, addr, buid >> 32, buid & 0xffffffff, nbytes); \
  87                         if (ret < 0 || (returnval == 0xffffffff)) \
  88                                ret = rtas_fake_read(dn, offset, nbytes, &returnval); \
  89                 } else { \
  90                         ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, nbytes); \
  91                 } \
  92         } \
  93         *val = returnval; \
  94         return ret; \
  95 } \
  96 int __chrp \
  97 rtas_pci_read_config_##size(struct pci_dev *dev, int offset, type val) {  \
  98         struct device_node *dn = pci_device_to_OF_node(dev); \
  99         int ret = rtas_read_config_##size(dn, offset, val); \
 100         /* udbg_printf("read bus=%x, devfn=%x, ret=%d phb=%lx, dn=%lx\n", dev->bus->number, dev->devfn, ret, dn ? dn->phb : 0, dn); */ \
 101         return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; \
 102 }
 103
 104 #define RTAS_PCI_WRITE_OP(size, type, nbytes) \
 105 int __chrp \
 106 rtas_write_config_##size(struct device_node *dn, int offset, type val) { \
 107         unsigned long buid; \
 108         unsigned int addr; \
 109         int ret; \
 110          \
 111         if (dn == NULL) { \
 112                 ret = -2; \
 113         } else if (dn->status) { \
 114                 ret = -1; \
 115         } else { \
 116                 buid = dn->phb->buid; \
 117                 addr = (dn->busno << 16) | (dn->devfn << 8) | offset; \
 118                 if (buid) { \
 119                         ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr, buid >> 32, buid & 0xffffffff, nbytes, (ulong) val); \
 120                 } else { \
 121                         ret = rtas_call(write_pci_config, 3, 1, NULL, addr, nbytes, (ulong)val); \
 122                 } \
 123         } \
 124         return ret; \
 125 } \
 126 int __chrp \
 127 rtas_pci_write_config_##size(struct pci_dev *dev, int offset, type val) { \
 128         struct device_node*  dn = pci_device_to_OF_node(dev); \
 129         int  ret = rtas_write_config_##size(dn, offset, val); \
 130         /* udbg_printf("write bus=%x, devfn=%x, ret=%d phb=%lx, dn=%lx\n", dev->bus->number, dev->devfn, ret, dn ? dn->phb : 0, dn); */ \
 131         return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; \
 132 }
 133
 134 RTAS_PCI_READ_OP(byte, u8 *, 1)
 135 RTAS_PCI_READ_OP(word, u16 *, 2)
 136 RTAS_PCI_READ_OP(dword, u32 *, 4)
 137 RTAS_PCI_WRITE_OP(byte, u8, 1)
 138 RTAS_PCI_WRITE_OP(word, u16, 2)
 139 RTAS_PCI_WRITE_OP(dword, u32, 4)
 140
 141 struct pci_ops rtas_pci_ops = {
 142         rtas_pci_read_config_byte,
 143         rtas_pci_read_config_word,
 144         rtas_pci_read_config_dword,
 145         rtas_pci_write_config_byte,
 146         rtas_pci_write_config_word,
 147         rtas_pci_write_config_dword,
 148 };
 149
 150 /*
 151  * Handle the case where rtas refuses to do a pci config read.
 152  * This currently only happens with some PHBs in which case we totally fake
 153  * out the values (and call it a speedwagaon -- something we could look up
 154  * in the device tree).
 155  */
 156 static int
 157 rtas_fake_read(struct device_node *dn, int offset, int nbytes, unsigned long *returnval)
 158 {
 159         char *device_type = (char *)get_property(dn, "device_type", 0);
 160         u32 *class_code = (u32 *)get_property(dn, "class-code", 0);
 161
 162         *returnval = ~0;        /* float by default */
 163
 164         /* udbg_printf("rtas_fake_read dn=%p, offset=0x%02x, nbytes=%d, device_type=%s\n", dn, offset, nbytes, device_type ? device_type : "<none>"); */
 165         if (device_type && strcmp(device_type, "pci") != 0)
 166                 return -3;      /* Not a phb or bridge */
 167
 168         /* NOTE: class_code != NULL => EADS pci bridge.  Else a PHB */
 169         if (nbytes == 1) {
 170                 if (offset == PCI_HEADER_TYPE)
 171                         *returnval = 0x80;      /* multifunction */
 172                 else if (offset == PCI_INTERRUPT_PIN || offset == PCI_INTERRUPT_LINE)
 173                         *returnval = 0;
 174         } else if (nbytes == 2) {
 175                 if (offset == PCI_SUBSYSTEM_VENDOR_ID || offset == PCI_SUBSYSTEM_ID)
 176                         *returnval = 0;
 177                 else if (offset == PCI_COMMAND)
 178                         *returnval = PCI_COMMAND_PARITY|PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY;
 179         } else if (nbytes == 4) {
 180                 if (offset == PCI_VENDOR_ID)
 181                         *returnval = 0x1014 | ((class_code ? 0x8b : 0x102) << 16); /* a phb */
 182                 else if (offset == PCI_REVISION_ID)
 183                         *returnval = (class_code ? PCI_CLASS_BRIDGE_PCI : PCI_CLASS_BRIDGE_HOST) << 16; /* revs are zero */
 184                 else if ((offset >= PCI_BASE_ADDRESS_0 && offset <= PCI_BASE_ADDRESS_5) || offset == PCI_ROM_ADDRESS)
 185                         *returnval = 0;
 186         }
 187
 188         /* printk("fake: %s nbytes=%d, offset=%lx ret=%lx\n", class_code ? "EADS" : "PHB", nbytes, offset, *returnval); */
 189         return 0;
 190 }
 191
 192 /******************************************************************
 193  * pci_read_irq_line
 194  *
 195  * Reads the Interrupt Pin to determine if interrupt is use by card.
 196  * If the interrupt is used, then gets the interrupt line from the
 197  * openfirmware and sets it in the pci_dev and pci_config line.
 198  *
 199  ******************************************************************/
 200 int
 201 pci_read_irq_line(struct pci_dev *Pci_Dev)
 202 {
 203         u8 InterruptPin;
 204         struct device_node *Node;
 205
 206         pci_read_config_byte(Pci_Dev, PCI_INTERRUPT_PIN, &InterruptPin);
 207         if (InterruptPin == 0) {
 208                 PPCDBG(PPCDBG_BUSWALK,"\tDevice: %s No Interrupt used by device.\n",Pci_Dev->slot_name);
 209                 return 0;
 210         }
 211         Node = pci_device_to_OF_node(Pci_Dev);
 212         if ( Node == NULL) {
 213                 PPCDBG(PPCDBG_BUSWALK,"\tDevice: %s Device Node not found.\n",Pci_Dev->slot_name);
 214                 return -1;
 215         }
 216         if (Node->n_intrs == 0)         {
 217                 PPCDBG(PPCDBG_BUSWALK,"\tDevice: %s No Device OF interrupts defined.\n",Pci_Dev->slot_name);
 218                 return -1;
 219         }
 220         Pci_Dev->irq = Node->intrs[0].line;
 221
 222         if (s7a_workaround) {
 223                 if (Pci_Dev->irq > 16)
 224                         Pci_Dev->irq -= 3;
 225         }
 226
 227         pci_write_config_byte(Pci_Dev, PCI_INTERRUPT_LINE, Pci_Dev->irq);
 228
 229         PPCDBG(PPCDBG_BUSWALK,"\tDevice: %s pci_dev->irq = 0x%02X\n",Pci_Dev->slot_name,Pci_Dev->irq);
 230         return 0;
 231 }
 232
 233 /******************************************************************
 234  * Find all PHBs in the system and initialize a set of data
 235  * structures to represent them.
 236  ******************************************************************/
 237 unsigned long __init
 238 find_and_init_phbs(void)
 239 {
 240         struct device_node *Pci_Node;
 241         struct pci_controller *phb;
 242         unsigned int root_addr_size_words = 0, this_addr_size_words = 0;
 243         unsigned int this_addr_count = 0, range_stride;
 244         unsigned int *ui_ptr = NULL, *ranges;
 245         char *model;
 246         struct pci_range64 range;
 247         struct resource *res;
 248         unsigned int memno, rlen, i, index;
 249         unsigned int *opprop;
 250         int has_isa = 0;
 251         PPCDBG(PPCDBG_PHBINIT, "find_and_init_phbs\n");
 252
 253         read_pci_config = rtas_token("read-pci-config");
 254         write_pci_config = rtas_token("write-pci-config");
 255         ibm_read_pci_config = rtas_token("ibm,read-pci-config");
 256         ibm_write_pci_config = rtas_token("ibm,write-pci-config");
 257
 258         if (naca->interrupt_controller == IC_OPEN_PIC) {
 259                 opprop = (unsigned int *)get_property(find_path_device("/"),
 260                                 "platform-open-pic", NULL);
 261         }
 262
 263         /* Get the root address word size. */
 264         ui_ptr = (unsigned int *) get_property(find_path_device("/"),
 265                                                "#size-cells", NULL);
 266         if (ui_ptr) {
 267                 root_addr_size_words = *ui_ptr;
 268         } else {
 269                 PPCDBG(PPCDBG_PHBINIT, "\tget #size-cells failed.\n");
 270                 return(-1);
 271         }
 272
 273         if (find_type_devices("isa")) {
 274                 has_isa = 1;
 275                 PPCDBG(PPCDBG_PHBINIT, "\tFound an ISA bus.\n");
 276         }
 277
 278         index = 0;
 279
 280         /******************************************************************
 281         * Find all PHB devices and create an object for them.
 282         ******************************************************************/
 283         for (Pci_Node = find_devices("pci"); Pci_Node != NULL; Pci_Node = Pci_Node->next) {
 284                 model = (char *) get_property(Pci_Node, "model", NULL);
 285                 if (model != NULL)  {
 286                         phb = alloc_phb(Pci_Node, model, root_addr_size_words);
 287                         if (phb == NULL) return(-1);
 288                 }
 289                 else {
 290                         continue;
 291                 }
 292
 293                 /* Get this node's address word size. */
 294                 ui_ptr = (unsigned int *) get_property(Pci_Node, "#size-cells", NULL);
 295                 if (ui_ptr)
 296                         this_addr_size_words = *ui_ptr;
 297                 else
 298                         this_addr_size_words = 1;
 299                 /* Get this node's address word count. */
 300                 ui_ptr = (unsigned int *) get_property(Pci_Node, "#address-cells", NULL);
 301                 if (ui_ptr)
 302                         this_addr_count = *ui_ptr;
 303                 else
 304                         this_addr_count = 3;
 305
 306                 range_stride = this_addr_count + root_addr_size_words + this_addr_size_words;
 307
 308                 memno = 0;
 309                 phb->io_base_phys = 0;
 310
 311                 ranges = (unsigned int *) get_property(Pci_Node, "ranges", &rlen);
 312                 PPCDBG(PPCDBG_PHBINIT, "\trange_stride = 0x%lx, rlen = 0x%x\n", range_stride, rlen);
 313
 314                 for (i = 0; i < (rlen/sizeof(*ranges)); i+=range_stride) {
 315                         /* Put the PCI addr part of the current element into a
 316                          * '64' struct.
 317                          */
 318                         range = *((struct pci_range64 *)(ranges + i));
 319
 320                         /* If this is a '32' element, map into a 64 struct. */
 321                         if ((range_stride * sizeof(int)) ==
 322                            sizeof(struct pci_range32)) {
 323                                 range.parent_addr =
 324                                         (unsigned long)(*(ranges + i + 3));
 325                                 range.size =
 326                                         (((unsigned long)(*(ranges + i + 4)))<<32) |
 327                                         (*(ranges + i + 5));
 328                         } else {
 329                                 range.parent_addr =
 330                                         (((unsigned long)(*(ranges + i + 3)))<<32) |
 331                                         (*(ranges + i + 4));
 332                                 range.size =
 333                                         (((unsigned long)(*(ranges + i + 5)))<<32) |
 334                                         (*(ranges + i + 6));
 335                         }
 336
 337                         PPCDBG(PPCDBG_PHBINIT, "\trange.parent_addr    = 0x%lx\n",
 338                                range.parent_addr);
 339                         PPCDBG(PPCDBG_PHBINIT, "\trange.child_addr.hi  = 0x%lx\n",
 340                                range.child_addr.a_hi);
 341                         PPCDBG(PPCDBG_PHBINIT, "\trange.child_addr.mid = 0x%lx\n",
 342                                range.child_addr.a_mid);
 343                         PPCDBG(PPCDBG_PHBINIT, "\trange.child_addr.lo  = 0x%lx\n",
 344                                range.child_addr.a_lo);
 345                         PPCDBG(PPCDBG_PHBINIT, "\trange.size           = 0x%lx\n",
 346                                range.size);
 347
 348                         res = NULL;
 349                         switch ((range.child_addr.a_hi >> 24) & 0x3) {
 350                         case 1:         /* I/O space */
 351                                 PPCDBG(PPCDBG_PHBINIT, "\tIO Space\n");
 352                                 phb->io_base_phys = range.parent_addr;
 353                                 res = &phb->io_resource;
 354                                 res->name = Pci_Node->full_name;
 355                                 res->flags = IORESOURCE_IO;
 356                                 phb->io_base_virt = __ioremap(phb->io_base_phys, range.size, _PAGE_NO_CACHE);
 357                                 if (!pci_io_base) {
 358                                         pci_io_base = (unsigned long)phb->io_base_virt;
 359                                         if (has_isa)
 360                                                 isa_io_base = pci_io_base;
 361                                 }
 362                                 res->start = ((((unsigned long) range.child_addr.a_mid) << 32) | (range.child_addr.a_lo));
 363                                 res->start += (unsigned long)phb->io_base_virt - pci_io_base;
 364                                 res->end =   res->start + range.size - 1;
 365                                 res->parent = NULL;
 366                                 res->sibling = NULL;
 367                                 res->child = NULL;
 368                                 phb->pci_io_offset = range.parent_addr -
 369                                         ((((unsigned long)
 370                                            range.child_addr.a_mid) << 32) |
 371                                          (range.child_addr.a_lo));
 372                                 PPCDBG(PPCDBG_PHBINIT, "\tpci_io_offset  = 0x%lx\n",
 373                                        phb->pci_io_offset);
 374                                 break;
 375                         case 2:         /* mem space */
 376                                 PPCDBG(PPCDBG_PHBINIT, "\tMem Space\n");
 377                                 phb->pci_mem_offset = range.parent_addr -
 378                                         ((((unsigned long)
 379                                            range.child_addr.a_mid) << 32) |
 380                                          (range.child_addr.a_lo));
 381                                 PPCDBG(PPCDBG_PHBINIT, "\tpci_mem_offset = 0x%lx\n",
 382                                        phb->pci_mem_offset);
 383                                 if (memno < sizeof(phb->mem_resources)/sizeof(phb->mem_resources[0])) {
 384                                         res = &(phb->mem_resources[memno]);
 385                                         ++memno;
 386                                         res->name = Pci_Node->full_name;
 387                                         res->flags = IORESOURCE_MEM;
 388                                         res->start = range.parent_addr;
 389                                         res->end =   range.parent_addr + range.size - 1;
 390                                         res->parent = NULL;
 391                                         res->sibling = NULL;
 392                                         res->child = NULL;
 393                                 }
 394                                 break;
 395                         }
 396                 }
 397                 PPCDBG(PPCDBG_PHBINIT, "\tphb->io_base_phys   = 0x%lx\n",
 398                        phb->io_base_phys);
 399                 PPCDBG(PPCDBG_PHBINIT, "\tphb->pci_mem_offset = 0x%lx\n",
 400                        phb->pci_mem_offset);
 401
 402                 if (naca->interrupt_controller == IC_OPEN_PIC) {
 403                         int addr = root_addr_size_words * (index + 2) - 1;
 404                         openpic_setup_ISU(index, opprop[addr]);
 405                 }
 406                 index++;
 407         }
 408         pci_devs_phb_init();
 409         return 0;        /*Success */
 410 }
 411
 412 /******************************************************************
 413  *
 414  * Allocate and partially initialize a structure to represent a PHB.
 415  *
 416  ******************************************************************/
 417 struct pci_controller *
 418 alloc_phb(struct device_node *dev, char *model, unsigned int addr_size_words)
 419 {
 420         struct pci_controller *phb;
 421         unsigned int *ui_ptr = NULL, len;
 422         struct reg_property64 reg_struct;
 423         struct property *of_prop;
 424         int *bus_range;
 425         int *buid_vals;
 426
 427         PPCDBG(PPCDBG_PHBINIT, "alloc_phb: %s\n", dev->full_name);
 428         PPCDBG(PPCDBG_PHBINIT, "\tdev             = 0x%lx\n", dev);
 429         PPCDBG(PPCDBG_PHBINIT, "\tmodel           = 0x%lx\n", model);
 430         PPCDBG(PPCDBG_PHBINIT, "\taddr_size_words = 0x%lx\n", addr_size_words);
 431
 432         /* Found a PHB, now figure out where his registers are mapped. */
 433         ui_ptr = (unsigned int *) get_property(dev, "reg", &len);
 434         if (ui_ptr == NULL) {
 435                 PPCDBG(PPCDBG_PHBINIT, "\tget reg failed.\n");
 436                 return(NULL);
 437         }
 438
 439         if (addr_size_words == 1) {
 440                 reg_struct.address = ((struct reg_property32 *)ui_ptr)->address;
 441                 reg_struct.size    = ((struct reg_property32 *)ui_ptr)->size;
 442         } else {
 443                 reg_struct = *((struct reg_property64 *)ui_ptr);
 444         }
 445
 446         PPCDBG(PPCDBG_PHBINIT, "\treg_struct.address = 0x%lx\n", reg_struct.address);
 447         PPCDBG(PPCDBG_PHBINIT, "\treg_struct.size    = 0x%lx\n", reg_struct.size);
 448
 449         /***************************************************************
 450         * Set chip specific data in the phb, including types &
 451         * register pointers.
 452         ***************************************************************/
 453
 454         /****************************************************************
 455         * Python
 456         ***************************************************************/
 457         if (strstr(model, "Python")) {
 458                 PPCDBG(PPCDBG_PHBINIT, "\tCreate python\n");
 459                 phb = pci_alloc_pci_controller("PHB PY",phb_type_python);
 460                 if (phb == NULL) return NULL;
 461
 462                 phb->cfg_addr = (volatile unsigned long *)
 463                         ioremap(reg_struct.address + 0xf8000, PAGE_SIZE);
 464                 PPCDBG(PPCDBG_PHBINIT, "\tcfg_addr_r = 0x%lx\n",
 465                        reg_struct.address + 0xf8000);
 466                 PPCDBG(PPCDBG_PHBINIT, "\tcfg_addr_v = 0x%lx\n",
 467                        phb->cfg_addr);
 468                 phb->cfg_data = (char*)(phb->cfg_addr + 0x02);
 469                 phb->phb_regs = (volatile unsigned long *)
 470                         ioremap(reg_struct.address + 0xf7000, PAGE_SIZE);
 471                 /* Python's register file is 1 MB in size. */
 472                 phb->chip_regs = ioremap(reg_struct.address & ~(0xfffffUL),
 473                                          0x100000);
 474
 475                 /*
 476                  * Firmware doesn't always clear this bit which is critical
 477                  * for good performance - Anton
 478                  */
 479                 {
 480                         volatile u32 *tmp, i;
 481
 482 #define PRG_CL_RESET_VALID 0x00010000
 483
 484                         tmp = (u32 *)((unsigned long)phb->chip_regs + 0xf6030);
 485
 486                         if (*tmp & PRG_CL_RESET_VALID) {
 487                                 printk("Python workaround: ");
 488                                 *tmp &= ~PRG_CL_RESET_VALID;
 489                                 /*
 490                                  * We must read it back for changes to
 491                                  * take effect
 492                                  */
 493                                 i = *tmp;
 494                                 printk("reg0: %x\n", i);
 495                         }
 496                 }
 497
 498         /***************************************************************
 499         * Speedwagon
 500         *   include Winnipeg as well for the time being.
 501         ***************************************************************/
 502         } else if ((strstr(model, "Speedwagon")) ||
 503                    (strstr(model, "Winnipeg"))) {
 504                 PPCDBG(PPCDBG_PHBINIT, "\tCreate speedwagon\n");
 505                 phb = pci_alloc_pci_controller("PHB SW",phb_type_speedwagon);
 506                 if (phb == NULL) return NULL;
 507
 508                 if (systemcfg->platform == PLATFORM_PSERIES) {
 509                         phb->cfg_addr = (volatile unsigned long *)
 510                           ioremap(reg_struct.address + 0x140, PAGE_SIZE);
 511                         phb->cfg_data = (char*)(phb->cfg_addr - 0x02); /* minus is correct */
 512                         phb->phb_regs = (volatile unsigned long *)
 513                           ioremap(reg_struct.address, PAGE_SIZE);
 514                         /* Speedwagon's register file is 1 MB in size. */
 515                         phb->chip_regs = ioremap(reg_struct.address & ~(0xfffffUL),
 516                                                  0x100000);
 517                         PPCDBG(PPCDBG_PHBINIT, "\tmapping chip_regs from 0x%lx -> 0x%lx\n",
 518                                reg_struct.address & 0xfffff, phb->chip_regs);
 519                 } else {
 520                         phb->cfg_addr = NULL;
 521                         phb->cfg_data = NULL;
 522                         phb->phb_regs = NULL;
 523                         phb->chip_regs = NULL;
 524                 }
 525
 526                 phb->local_number = ((reg_struct.address >> 12) & 0xf) - 0x8;
 527         /***************************************************************
 528         * Trying to build a known just gets the code in trouble.
 529         ***************************************************************/
 530         } else {
 531                 PPCDBG(PPCDBG_PHBINIT, "\tUnknown PHB Type!\n");
 532                 printk("PCI: Unknown Phb Type!\n");
 533                 return NULL;
 534         }
 535
 536         /* Add a linux,phbnum property to the device tree so user code
 537          * can translate bus numbers.
 538          */
 539         of_prop = (struct property *) alloc_bootmem(sizeof(struct property) +
 540                                                     sizeof(phb->global_number));
 541         if (of_prop) {
 542                 memset(of_prop, 0, sizeof(struct property));
 543                 of_prop->name = "linux,phbnum";
 544                 of_prop->length = sizeof(phb->global_number);
 545                 of_prop->value = (unsigned char *)&of_prop[1];
 546                 memcpy(of_prop->value, &phb->global_number,
 547                        sizeof(phb->global_number));
 548                 prom_add_property(dev, of_prop);
 549         }
 550
 551         bus_range = (int *) get_property(dev, "bus-range", &len);
 552         if (bus_range == NULL || len < 2 * sizeof(int)) {
 553                 PPCDBG(PPCDBG_PHBINIT, "Can't get bus-range for %s\n", dev->full_name);
 554                 kfree(phb);
 555                 return(NULL);
 556         }
 557
 558         /***************************************************************
 559         * Finished with the initialization
 560         ***************************************************************/
 561         phb->first_busno =  bus_range[0];
 562         phb->last_busno  =  bus_range[1];
 563
 564         phb->arch_data   = dev;
 565         phb->ops = &rtas_pci_ops;
 566
 567         buid_vals = (int *) get_property(dev, "ibm,fw-phb-id", &len);
 568
 569   if (buid_vals == NULL) {
 570                 phb->buid = 0;
 571         }
 572   else {
 573                 struct pci_bus check;
 574                 if (sizeof(check.number) == 1 || sizeof(check.primary) == 1 ||
 575                     sizeof(check.secondary) == 1 || sizeof(check.subordinate) == 1) {
 576                         udbg_printf("pSeries_pci:  this system has large bus numbers and the kernel was not\n"
 577                               "built with the patch that fixes include/linux/pci.h struct pci_bus so\n"
 578                               "number, primary, secondary and subordinate are ints.\n");
 579                         panic("pSeries_pci:  this system has large bus numbers and the kernel was not\n"
 580                               "built with the patch that fixes include/linux/pci.h struct pci_bus so\n"
 581                               "number, primary, secondary and subordinate are ints.\n");
 582     }
 583
 584     if (len < 2 * sizeof(int))
 585       phb->buid = (unsigned long)buid_vals[0];  // Support for new OF that only has 1 integer for buid.
 586     else
 587       phb->buid = (((unsigned long)buid_vals[0]) << 32UL) |
 588                   (((unsigned long)buid_vals[1]) & 0xffffffff);
 589
 590                 phb->first_busno += (phb->global_number << 8);
 591                 phb->last_busno += (phb->global_number << 8);
 592         }
 593
 594         /* Dump PHB information for Debug */
 595         PPCDBGCALL(PPCDBG_PHBINIT,dumpPci_Controller(phb) );
 596
 597         return phb;
 598 }
 599
 600 void
 601 fixup_resources(struct pci_dev *dev)
 602 {
 603         int i;
 604         struct pci_controller *phb = PCI_GET_PHB_PTR(dev);
 605         struct device_node *dn;
 606
 607         /* Add IBM loc code (slot) as a prefix to the device names for service */
 608         dn = pci_device_to_OF_node(dev);
 609         if (dn) {
 610                 char *loc_code = get_property(dn, "ibm,loc-code", 0);
 611                 if (loc_code) {
 612                         int loc_len = strlen(loc_code);
 613                         if (loc_len < sizeof(dev->name)) {
 614                                 memmove(dev->name+loc_len+1, dev->name, sizeof(dev->name)-loc_len-1);
 615                                 memcpy(dev->name, loc_code, loc_len);
 616                                 dev->name[loc_len] = ' ';
 617                                 dev->name[sizeof(dev->name)-1] = '\0';
 618                         }
 619                 }
 620         }
 621
 622         PPCDBG(PPCDBG_PHBINIT, "fixup_resources:\n");
 623         PPCDBG(PPCDBG_PHBINIT, "\tphb                 = 0x%016LX\n", phb);
 624         PPCDBG(PPCDBG_PHBINIT, "\tphb->pci_io_offset  = 0x%016LX\n", phb->pci_io_offset);
 625         PPCDBG(PPCDBG_PHBINIT, "\tphb->pci_mem_offset = 0x%016LX\n", phb->pci_mem_offset);
 626
 627         PPCDBG(PPCDBG_PHBINIT, "\tdev->name   = %s\n", dev->name);
 628         PPCDBG(PPCDBG_PHBINIT, "\tdev->vendor:device = 0x%04X : 0x%04X\n", dev->vendor, dev->device);
 629
 630         if (phb == NULL)
 631                 return;
 632
 633         for (i = 0; i <  DEVICE_COUNT_RESOURCE; ++i) {
 634                 PPCDBG(PPCDBG_PHBINIT, "\tdevice %x.%x[%d] (flags %x) [%lx..%lx]\n",
 635                             dev->bus->number, dev->devfn, i,
 636                             dev->resource[i].flags,
 637                             dev->resource[i].start,
 638                             dev->resource[i].end);
 639
 640                 if ((dev->resource[i].start == 0) && (dev->resource[i].end == 0)) {
 641                         continue;
 642                 }
 643
 644                 if (dev->resource[i].start > dev->resource[i].end) {
 645                         /* Bogus resource.  Just clear it out. */
 646                         dev->resource[i].start = dev->resource[i].end = 0;
 647                         continue;
 648                 }
 649
 650
 651                 if (dev->resource[i].flags & IORESOURCE_IO) {
 652                         unsigned long offset = (unsigned long)phb->io_base_virt - pci_io_base;
 653                         dev->resource[i].start += offset;
 654                         dev->resource[i].end += offset;
 655                         PPCDBG(PPCDBG_PHBINIT, "\t\t-> now [%lx .. %lx]\n",
 656                                dev->resource[i].start, dev->resource[i].end);
 657                 } else if (dev->resource[i].flags & IORESOURCE_MEM) {
 658                         if (dev->resource[i].start == 0) {
 659                                 /* Bogus.  Probably an unused bridge. */
 660                                 dev->resource[i].end = 0;
 661                         } else {
 662                                 dev->resource[i].start += phb->pci_mem_offset;
 663                                 dev->resource[i].end += phb->pci_mem_offset;
 664                         }
 665                         PPCDBG(PPCDBG_PHBINIT, "\t\t-> now [%lx..%lx]\n",
 666                                dev->resource[i].start, dev->resource[i].end);
 667
 668                 } else {
 669                         continue;
 670                 }
 671
 672                 /* zap the 2nd function of the winbond chip */
 673                 if (dev->resource[i].flags & IORESOURCE_IO
 674                     && dev->bus->number == 0 && dev->devfn == 0x81)
 675                         dev->resource[i].flags &= ~IORESOURCE_IO;
 676         }
 677 }
 678
 679 static void check_s7a(void)
 680 {
 681         struct device_node *root;
 682         char *model;
 683
 684         root = find_path_device("/");
 685         if (root) {
 686                 model = get_property(root, "model", NULL);
 687                 if (model && !strcmp(model, "IBM,7013-S7A"))
 688                         s7a_workaround = 1;
 689         }
 690 }
 691
 692 void __init
 693 pSeries_pcibios_fixup(void)
 694 {
 695         struct pci_dev *dev;
 696
 697         PPCDBG(PPCDBG_PHBINIT, "pSeries_pcibios_fixup: start\n");
 698         pci_assign_all_busses = 0;
 699
 700         check_s7a();
 701
 702         pci_for_each_dev(dev) {
 703                 pci_read_irq_line(dev);
 704                 PPCDBGCALL(PPCDBG_PHBINIT, dumpPci_Dev(dev) );
 705         }
 706
 707         if (naca->interrupt_controller == IC_PPC_XIC) {
 708                 xics_isa_init();
 709         }
 710 }
 711
 712 /***********************************************************************
 713  * pci_find_hose_for_OF_device
 714  *
 715  * This function finds the PHB that matching device_node in the
 716  * OpenFirmware by scanning all the pci_controllers.
 717  *
 718  ***********************************************************************/
 719 struct pci_controller*
 720 pci_find_hose_for_OF_device(struct device_node *node)
 721 {
 722         while (node) {
 723                 struct pci_controller *hose;
 724                 for (hose=hose_head;hose;hose=hose->next)
 725                         if (hose->arch_data == node)
 726                                 return hose;
 727                 node=node->parent;
 728         }
 729         return NULL;
 730 }
 731
 732 /***********************************************************************
 733  * ppc64_pcibios_init
 734  *
 735  * Chance to initialize and structures or variable before PCI Bus walk.
 736  *
 737  ***********************************************************************/
 738 void
 739 pSeries_pcibios_init(void)
 740 {
 741         PPCDBG(PPCDBG_PHBINIT, "\tppc64_pcibios_init Entry.\n");
 742
 743         if (get_property(find_path_device("/rtas"),"ibm,fw-phb-id",NULL) != NULL) {
 744                 PPCDBG(PPCDBG_PHBINIT, "\tFound: ibm,fw-phb-id\n");
 745                 Pci_Large_Bus_System = 1;
 746         }
 747 }
 748
 749 /*
 750  * This is called very early before the page table is setup.
 751  */
 752 void
 753 pSeries_pcibios_init_early(void)
 754 {
 755         ppc_md.pcibios_read_config_byte = rtas_read_config_byte;
 756         ppc_md.pcibios_read_config_word = rtas_read_config_word;
 757         ppc_md.pcibios_read_config_dword = rtas_read_config_dword;
 758         ppc_md.pcibios_write_config_byte = rtas_write_config_byte;
 759         ppc_md.pcibios_write_config_word = rtas_write_config_word;
 760         ppc_md.pcibios_write_config_dword = rtas_write_config_dword;
 761 }
 762 /************************************************************************/
 763 /* Get a char* of the device physical location(U0.3-P1-I8)              */
 764 /* See the Product Topology in the RS/6000 Architecture.                */
 765 /************************************************************************/
 766 int device_Location(struct pci_dev *PciDev, char *BufPtr)
 767 {
 768         struct device_node *DevNode = (struct device_node *)PciDev->sysdata;
 769         return sprintf(BufPtr,"PCI: Bus%3d, Device%3d, Vendor %04X, Location %-12s",
 770                        PciDev->bus->number,
 771                        PCI_SLOT(PciDev->devfn),
 772                        PciDev->vendor,
 773                        (char*)get_property(DevNode,"ibm,loc-code",0));
 774 }
 775 /************************************************************************/
 776 /* Set the slot reset line to the state passed in.                      */
 777 /* This is the platform specific for code for the pci_reset_device      */
 778 /* function.                                                            */
 779 /************************************************************************/
 780 int pci_set_reset(struct pci_dev *PciDev, int state)
 781 {
 782         return -1;
 783 }