arch/ppc64/kernel/pci.c

   1 /*
   2  * Port for PPC64 David Engebretsen, IBM Corp.
   3  *   Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
   4  *
   5  *      This program is free software; you can redistribute it and/or
   6  *      modify it under the terms of the GNU General Public License
   7  *      as published by the Free Software Foundation; either version
   8  *      2 of the License, or (at your option) any later version.
   9  */
  10
  11 #include <linux/config.h>
  12 #include <linux/kernel.h>
  13 #include <linux/pci.h>
  14 #include <linux/delay.h>
  15 #include <linux/string.h>
  16 #include <linux/init.h>
  17 #include <linux/capability.h>
  18 #include <linux/sched.h>
  19 #include <linux/errno.h>
  20 #include <linux/bootmem.h>
  21
  22 #include <asm/processor.h>
  23 #include <asm/io.h>
  24 #include <asm/prom.h>
  25 #include <asm/pci-bridge.h>
  26 #include <asm/byteorder.h>
  27 #include <asm/irq.h>
  28 #include <asm/uaccess.h>
  29 #include <asm/flight_recorder.h>
  30 #include <asm/ppcdebug.h>
  31 #include <asm/naca.h>
  32 #include <asm/pci_dma.h>
  33 #include <asm/machdep.h>
  34
  35 #include "pci.h"
  36
  37 /* pci_io_base -- the base address from which io bars are offsets.
  38  * This is the lowest I/O base address (so bar values are always positive),
  39  * and it *must* be the start of ISA space if an ISA bus exists because
  40  * ISA drivers use hard coded offsets.  If no ISA bus exists a dummy
  41  * page is mapped and isa_io_limit prevents access to it.
  42  */
  43 unsigned long isa_io_base     = 0;      /* NULL if no ISA bus */
  44 unsigned long pci_io_base     = 0;
  45 unsigned long isa_mem_base    = 0;
  46 unsigned long pci_dram_offset = 0;
  47
  48 /******************************************************************
  49  * Forward declare of prototypes
  50  ******************************************************************/
  51 static void pcibios_fixup_resources(struct pci_dev* dev);
  52 static void fixup_broken_pcnet32(struct pci_dev* dev);
  53 static void fixup_windbond_82c105(struct pci_dev* dev);
  54 void        fixup_resources(struct pci_dev* dev);
  55
  56 void   iSeries_pcibios_init(void);
  57 void   pSeries_pcibios_init(void);
  58
  59 int    pci_assign_all_busses = 0;
  60 struct pci_controller* hose_head;
  61 struct pci_controller** hose_tail = &hose_head;
  62
  63 LIST_HEAD(iSeries_Global_Device_List);
  64
  65 /*******************************************************************
  66  * Counters and control flags.
  67  *******************************************************************/
  68 long   Pci_Io_Read_Count  = 0;
  69 long   Pci_Io_Write_Count = 0;
  70 long   Pci_Cfg_Read_Count = 0;
  71 long   Pci_Cfg_Write_Count= 0;
  72 long   Pci_Error_Count    = 0;
  73
  74 int    Pci_Retry_Max      = 7;  /* Retry set to 7 times  */
  75 int    Pci_Error_Flag     = 1;  /* Set Retry Error on. */
  76 int    Pci_Trace_Flag     = 0;
  77
  78 /******************************************************************
  79  *
  80  ******************************************************************/
  81 int  global_phb_number    = 0;           /* Global phb counter    */
  82 int  Pci_Large_Bus_System = 0;
  83 int  Pci_Set_IOA_Address  = 0;
  84 int  Pci_Manage_Phb_Space = 0;
  85 struct pci_controller *phbtab[PCI_MAX_PHB];
  86
  87 static int pci_bus_count;
  88
  89 /* Cached ISA bridge dev. */
  90 struct pci_dev *ppc64_isabridge_dev = NULL;
  91
  92 struct pci_fixup pcibios_fixups[] = {
  93         { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_TRIDENT,  PCI_ANY_ID, fixup_broken_pcnet32 },
  94         { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_WINBOND,  PCI_DEVICE_ID_WINBOND_82C105, fixup_windbond_82c105 },
  95         { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources },
  96         { 0 }
  97 };
  98
  99 static void fixup_broken_pcnet32(struct pci_dev* dev)
 100 {
 101         if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
 102                 dev->vendor = PCI_VENDOR_ID_AMD;
 103                 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
 104                 pci_name_device(dev);
 105         }
 106 }
 107
 108 static void fixup_windbond_82c105(struct pci_dev* dev)
 109 {
 110         /* Assume the windbond 82c105 is the IDE controller on a
 111          * p610.  We should probably be more careful in case
 112          * someone tries to plug in a similar adapter.
 113          */
 114         unsigned int reg;
 115
 116         printk("Using INTC for W82c105 IDE controller.\n");
 117         pci_read_config_dword(dev, 0x40, &reg);
 118         /* Enable LEGIRQ to use INTC instead of ISA interrupts */
 119         pci_write_config_dword(dev, 0x40, reg | (1<<11));
 120 }
 121
 122
 123 /* Given an mmio phys address, find a pci device that implements
 124  * this address.  This is of course expensive, but only used
 125  * for device initialization or error paths.
 126  * For io BARs it is assumed the pci_io_base has already been added
 127  * into addr.
 128  *
 129  * Bridges are ignored although they could be used to optimize the search.
 130  */
 131 struct pci_dev *pci_find_dev_by_addr(unsigned long addr)
 132 {
 133         struct pci_dev *dev;
 134         int i;
 135         unsigned long ioaddr;
 136
 137         ioaddr = (addr > _IO_BASE) ? addr - _IO_BASE : 0;
 138
 139         pci_for_each_dev(dev) {
 140                 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
 141                         continue;
 142                 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 143                         unsigned long start = pci_resource_start(dev,i);
 144                         unsigned long end = pci_resource_end(dev,i);
 145                         unsigned int flags = pci_resource_flags(dev,i);
 146                         if (start == 0 || ~start == 0 ||
 147                             end == 0 || ~end == 0)
 148                                 continue;
 149                         if ((flags & IORESOURCE_IO) &&
 150                             (ioaddr >= start && ioaddr <= end))
 151                                 return dev;
 152                         else if ((flags & IORESOURCE_MEM) &&
 153                                  (addr >= start && addr <= end))
 154                                 return dev;
 155                 }
 156         }
 157         return NULL;
 158 }
 159
 160 void pcibios_fixup_pbus_ranges(struct pci_bus *pbus,
 161                                 struct pbus_set_ranges_data *pranges)
 162 {
 163 }
 164
 165 void
 166 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
 167                              struct resource *res, int resource)
 168 {
 169         u32 new, check;
 170         int reg;
 171         struct pci_controller* hose = PCI_GET_PHB_PTR(dev);
 172
 173         new = res->start;
 174         if (hose && res->flags & IORESOURCE_MEM)
 175                 new -= hose->pci_mem_offset;
 176         new |= (res->flags & PCI_REGION_FLAG_MASK);
 177         if (resource < 6) {
 178                 reg = PCI_BASE_ADDRESS_0 + 4*resource;
 179         } else if (resource == PCI_ROM_RESOURCE) {
 180                 res->flags |= PCI_ROM_ADDRESS_ENABLE;
 181                 reg = dev->rom_base_reg;
 182         } else {
 183                 /* Somebody might have asked allocation of a non-standard resource */
 184                 return;
 185         }
 186
 187         pci_write_config_dword(dev, reg, new);
 188         pci_read_config_dword(dev, reg, &check);
 189         if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
 190                 printk(KERN_ERR "PCI: Error while updating region "
 191                        "%s/%d (%08x != %08x)\n", dev->slot_name, resource,
 192                        new, check);
 193         }
 194 }
 195
 196 static void
 197 pcibios_fixup_resources(struct pci_dev* dev)
 198 {
 199         fixup_resources(dev);
 200 }
 201
 202 /*
 203  * We need to avoid collisions with `mirrored' VGA ports
 204  * and other strange ISA hardware, so we always want the
 205  * addresses to be allocated in the 0x000-0x0ff region
 206  * modulo 0x400.
 207  *
 208  * Why? Because some silly external IO cards only decode
 209  * the low 10 bits of the IO address. The 0x00-0xff region
 210  * is reserved for motherboard devices that decode all 16
 211  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 212  * but we want to try to avoid allocating at 0x2900-0x2bff
 213  * which might have be mirrored at 0x0100-0x03ff..
 214  */
 215 void
 216 pcibios_align_resource(void *data, struct resource *res, unsigned long size,
 217                        unsigned long align)
 218
 219 {
 220         struct pci_dev *dev = data;
 221
 222         if (res->flags & IORESOURCE_IO) {
 223                 unsigned long start = res->start;
 224
 225                 if (size > 0x100) {
 226                         printk(KERN_ERR "PCI: Can not align I/O Region %s %s because size %ld is too large.\n",
 227                                         dev->slot_name, res->name, size);
 228                 }
 229
 230                 if (start & 0x300) {
 231                         start = (start + 0x3ff) & ~0x3ff;
 232                         res->start = start;
 233                 }
 234         }
 235 }
 236
 237 /*
 238  *  Handle resources of PCI devices.  If the world were perfect, we could
 239  *  just allocate all the resource regions and do nothing more.  It isn't.
 240  *  On the other hand, we cannot just re-allocate all devices, as it would
 241  *  require us to know lots of host bridge internals.  So we attempt to
 242  *  keep as much of the original configuration as possible, but tweak it
 243  *  when it's found to be wrong.
 244  *
 245  *  Known BIOS problems we have to work around:
 246  *      - I/O or memory regions not configured
 247  *      - regions configured, but not enabled in the command register
 248  *      - bogus I/O addresses above 64K used
 249  *      - expansion ROMs left enabled (this may sound harmless, but given
 250  *        the fact the PCI specs explicitly allow address decoders to be
 251  *        shared between expansion ROMs and other resource regions, it's
 252  *        at least dangerous)
 253  *
 254  *  Our solution:
 255  *      (1) Allocate resources for all buses behind PCI-to-PCI bridges.
 256  *          This gives us fixed barriers on where we can allocate.
 257  *      (2) Allocate resources for all enabled devices.  If there is
 258  *          a collision, just mark the resource as unallocated. Also
 259  *          disable expansion ROMs during this step.
 260  *      (3) Try to allocate resources for disabled devices.  If the
 261  *          resources were assigned correctly, everything goes well,
 262  *          if they weren't, they won't disturb allocation of other
 263  *          resources.
 264  *      (4) Assign new addresses to resources which were either
 265  *          not configured at all or misconfigured.  If explicitly
 266  *          requested by the user, configure expansion ROM address
 267  *          as well.
 268  */
 269
 270 static void __init
 271 pcibios_allocate_bus_resources(struct list_head *bus_list)
 272 {
 273         struct list_head *ln;
 274         struct pci_bus *bus;
 275         int i;
 276         struct resource *res, *pr;
 277
 278         /* Depth-First Search on bus tree */
 279         for (ln=bus_list->next; ln != bus_list; ln=ln->next) {
 280                 bus = pci_bus_b(ln);
 281                 for (i = 0; i < 4; ++i) {
 282                         if ((res = bus->resource[i]) == NULL || !res->flags)
 283                                 continue;
 284                         if (bus->parent == NULL)
 285                                 pr = (res->flags & IORESOURCE_IO)?
 286                                         &ioport_resource: &iomem_resource;
 287                         else
 288                                 pr = pci_find_parent_resource(bus->self, res);
 289
 290                         if (pr == res)
 291                                 continue;       /* transparent bus or undefined */
 292                         if (pr && request_resource(pr, res) == 0)
 293                                 continue;
 294                         printk(KERN_ERR "PCI: Cannot allocate resource region "
 295                                "%d of PCI bridge %x\n", i, bus->number);
 296                         printk(KERN_ERR "PCI: resource is %lx..%lx (%lx), parent %p\n",
 297                             res->start, res->end, res->flags, pr);
 298                 }
 299                 pcibios_allocate_bus_resources(&bus->children);
 300         }
 301 }
 302
 303 static void __init
 304 pcibios_allocate_resources(int pass)
 305 {
 306         struct pci_dev *dev;
 307         int idx, disabled;
 308         u16 command;
 309         struct resource *r, *pr;
 310
 311         pci_for_each_dev(dev) {
 312                 pci_read_config_word(dev, PCI_COMMAND, &command);
 313                 for(idx = 0; idx < 6; idx++) {
 314                         r = &dev->resource[idx];
 315                         if (r->parent)          /* Already allocated */
 316                                 continue;
 317                         if (!r->start)          /* Address not assigned at all */
 318                                 continue;
 319
 320                         if (r->flags & IORESOURCE_IO)
 321                                 disabled = !(command & PCI_COMMAND_IO);
 322                         else
 323                                 disabled = !(command & PCI_COMMAND_MEMORY);
 324                         if (pass == disabled) {
 325                                 PPCDBG(PPCDBG_PHBINIT,
 326                                        "PCI: Resource %08lx-%08lx (f=%lx, d=%d, p=%d)\n",
 327                                        r->start, r->end, r->flags, disabled, pass);
 328                                 pr = pci_find_parent_resource(dev, r);
 329                                 if (!pr || request_resource(pr, r) < 0) {
 330                                         PPCDBG(PPCDBG_PHBINIT,
 331                                                "PCI: Cannot allocate resource region %d of device %s, pr = 0x%lx\n", idx, dev->slot_name, pr);
 332                                         if(pr) {
 333                                         PPCDBG(PPCDBG_PHBINIT,
 334                                                "PCI: Cannot allocate resource 0x%lx\n", request_resource(pr,r));
 335                                         }
 336                                         /* We'll assign a new address later */
 337                                         r->end -= r->start;
 338                                         r->start = 0;
 339                                 }
 340                         }
 341                 }
 342                 if (!pass) {
 343                         r = &dev->resource[PCI_ROM_RESOURCE];
 344                         if (r->flags & PCI_ROM_ADDRESS_ENABLE) {
 345                                 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
 346                                 u32 reg;
 347                                 r->flags &= ~PCI_ROM_ADDRESS_ENABLE;
 348                                 pci_read_config_dword(dev, dev->rom_base_reg, &reg);
 349                                 pci_write_config_dword(dev, dev->rom_base_reg, reg & ~PCI_ROM_ADDRESS_ENABLE);
 350                         }
 351                 }
 352         }
 353 }
 354
 355 static void __init
 356 pcibios_assign_resources(void)
 357 {
 358         struct pci_dev *dev;
 359         int idx;
 360         struct resource *r;
 361
 362         pci_for_each_dev(dev) {
 363                 int class = dev->class >> 8;
 364
 365                 /* Don't touch classless devices and host bridges */
 366                 if (!class || class == PCI_CLASS_BRIDGE_HOST)
 367                         continue;
 368
 369                 for(idx=0; idx<6; idx++) {
 370                         r = &dev->resource[idx];
 371
 372                         /*
 373                          *  Don't touch IDE controllers and I/O ports of video cards!
 374                          */
 375                         if ((class == PCI_CLASS_STORAGE_IDE && idx < 4) ||
 376                             (class == PCI_CLASS_DISPLAY_VGA && (r->flags & IORESOURCE_IO)))
 377                                 continue;
 378
 379                         /*
 380                          *  We shall assign a new address to this resource, either because
 381                          *  the BIOS forgot to do so or because we have decided the old
 382                          *  address was unusable for some reason.
 383                          */
 384                         if (!r->start && r->end && ppc_md.pcibios_enable_device_hook &&
 385                             !ppc_md.pcibios_enable_device_hook(dev, 1))
 386                                 pci_assign_resource(dev, idx);
 387                 }
 388
 389                 if (0) { /* don't assign ROMs */
 390                         r = &dev->resource[PCI_ROM_RESOURCE];
 391                         r->end -= r->start;
 392                         r->start = 0;
 393                         if (r->end)
 394                                 pci_assign_resource(dev, PCI_ROM_RESOURCE);
 395                 }
 396         }
 397 }
 398
 399
 400 int
 401 pcibios_enable_resources(struct pci_dev *dev, int mask)
 402 {
 403         u16 cmd, old_cmd;
 404         int idx;
 405         struct resource *r;
 406
 407         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 408         old_cmd = cmd;
 409         for(idx=0; idx<6; idx++) {
 410                 if(!(mask & (1<<idx)))
 411                         continue;
 412                 r = &dev->resource[idx];
 413                 if (!r->start && r->end) {
 414                         printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", dev->slot_name);
 415                         return -EINVAL;
 416                 }
 417                 if (r->flags & IORESOURCE_IO)
 418                         cmd |= PCI_COMMAND_IO;
 419                 if (r->flags & IORESOURCE_MEM)
 420                         cmd |= PCI_COMMAND_MEMORY;
 421         }
 422         if (dev->resource[PCI_ROM_RESOURCE].start)
 423                 cmd |= PCI_COMMAND_MEMORY;
 424         if (cmd != old_cmd) {
 425                 printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
 426                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 427         }
 428         return 0;
 429 }
 430
 431 /*
 432  * Allocate pci_controller(phb) initialized common variables.
 433  */
 434 struct pci_controller * __init
 435 pci_alloc_pci_controller(char *model, enum phb_types controller_type)
 436 {
 437         struct pci_controller *hose;
 438         PPCDBG(PPCDBG_PHBINIT, "PCI: Allocate pci_controller for %s\n",model);
 439         hose = (struct pci_controller *)alloc_bootmem(sizeof(struct pci_controller));
 440         if(hose == NULL) {
 441                 printk(KERN_ERR "PCI: Allocate pci_controller failed.\n");
 442                 return NULL;
 443         }
 444         memset(hose, 0, sizeof(struct pci_controller));
 445         if(strlen(model) < 8)
 446                 strcpy(hose->what,model);
 447         else
 448                 memcpy(hose->what,model,7);
 449         hose->type = controller_type;
 450         hose->global_number = global_phb_number;
 451         phbtab[global_phb_number++] = hose;
 452
 453         *hose_tail = hose;
 454         hose_tail = &hose->next;
 455         return hose;
 456 }
 457
 458 /*
 459  * This fixup is arch independent and probably should go somewhere else.
 460  */
 461 void __init
 462 pcibios_generic_fixup(void)
 463 {
 464         struct pci_dev *dev;
 465
 466         /* Fix miss-identified vendor AMD pcnet32 adapters. */
 467         dev = NULL;
 468         while ((dev = pci_find_device(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE, dev)) != NULL &&
 469                dev->class == (PCI_CLASS_NETWORK_ETHERNET << 8))
 470                 dev->vendor = PCI_VENDOR_ID_AMD;
 471 }
 472
 473
 474
 475 /***********************************************************************
 476  *
 477  *
 478  *
 479  ***********************************************************************/
 480 void __init
 481 pcibios_init(void)
 482 {
 483         struct pci_controller *hose;
 484         struct pci_bus *bus;
 485         int    next_busno;
 486
 487 #ifndef CONFIG_PPC_ISERIES
 488         pSeries_pcibios_init();
 489 #else
 490         iSeries_pcibios_init();
 491 #endif
 492
 493         ppc64_boot_msg(0x40, "PCI Probe");
 494         printk("PCI: Probing PCI hardware\n");
 495         PPCDBG(PPCDBG_BUSWALK,"PCI: Probing PCI hardware\n");
 496
 497         /* Scan all of the recorded PCI controllers.  */
 498         for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
 499                 hose->last_busno = 0xff;
 500                 bus = pci_scan_bus(hose->first_busno, hose->ops, hose->arch_data);
 501                 hose->bus = bus;
 502                 hose->last_busno = bus->subordinate;
 503                 if (pci_assign_all_busses || next_busno <= hose->last_busno)
 504                         next_busno = hose->last_busno+1;
 505         }
 506         pci_bus_count = next_busno;
 507
 508         /* Call machine dependant fixup */
 509         if (ppc_md.pcibios_fixup) {
 510                 ppc_md.pcibios_fixup();
 511         }
 512
 513         /* Generic fixups */
 514         pcibios_generic_fixup();
 515
 516         /* Allocate and assign resources */
 517         pcibios_allocate_bus_resources(&pci_root_buses);
 518         pcibios_allocate_resources(0);
 519         pcibios_allocate_resources(1);
 520         pcibios_assign_resources();
 521
 522 #ifndef CONFIG_PPC_ISERIES
 523         pci_fix_bus_sysdata();
 524
 525         create_tce_tables();
 526         PPCDBG(PPCDBG_BUSWALK,"pSeries create_tce_tables()\n");
 527 #endif
 528
 529         /* Cache the location of the ISA bridge (if we have one) */
 530         ppc64_isabridge_dev = pci_find_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 531         if (ppc64_isabridge_dev != NULL )
 532                 printk("ISA bridge at %s\n", ppc64_isabridge_dev->slot_name);
 533
 534         printk("PCI: Probing PCI hardware done\n");
 535         PPCDBG(PPCDBG_BUSWALK,"PCI: Probing PCI hardware done.\n");
 536         ppc64_boot_msg(0x41, "PCI Done");
 537
 538 }
 539
 540 int __init
 541 pcibios_assign_all_busses(void)
 542 {
 543         return pci_assign_all_busses;
 544 }
 545
 546 unsigned long resource_fixup(struct pci_dev * dev, struct resource * res,
 547                              unsigned long start, unsigned long size)
 548 {
 549         return start;
 550 }
 551
 552 void __init pcibios_fixup_bus(struct pci_bus *bus)
 553 {
 554 #ifndef CONFIG_PPC_ISERIES
 555         struct pci_controller *phb = PCI_GET_PHB_PTR(bus);
 556         struct resource *res;
 557         int i;
 558
 559         if (bus->parent == NULL) {
 560                 /* This is a host bridge - fill in its resources */
 561                 phb->bus = bus;
 562                 bus->resource[0] = res = &phb->io_resource;
 563                 if (!res->flags)
 564                         BUG();  /* No I/O resource for this PHB? */
 565
 566                 for (i = 0; i < 3; ++i) {
 567                         res = &phb->mem_resources[i];
 568                         if (!res->flags) {
 569                                 if (i == 0)
 570                                         BUG();  /* No memory resource for this PHB? */
 571                         }
 572                         bus->resource[i+1] = res;
 573                 }
 574         } else {
 575                 /* This is a subordinate bridge */
 576                 pci_read_bridge_bases(bus);
 577
 578                 for (i = 0; i < 4; ++i) {
 579                         if ((res = bus->resource[i]) == NULL)
 580                                 continue;
 581                         if (!res->flags)
 582                                 continue;
 583                         if (res == pci_find_parent_resource(bus->self, res)) {
 584                                 /* Transparent resource -- don't try to "fix" it. */
 585                                 continue;
 586                         }
 587                         if (res->flags & IORESOURCE_IO) {
 588                                 unsigned long offset = (unsigned long)phb->io_base_virt - pci_io_base;
 589                                 res->start += offset;
 590                                 res->end += offset;
 591                         } else if (phb->pci_mem_offset
 592                                    && (res->flags & IORESOURCE_MEM)) {
 593                                 if (res->start < phb->pci_mem_offset) {
 594                                         res->start += phb->pci_mem_offset;
 595                                         res->end += phb->pci_mem_offset;
 596                                 }
 597                         }
 598                 }
 599         }
 600 #endif
 601         if ( ppc_md.pcibios_fixup_bus )
 602                 ppc_md.pcibios_fixup_bus(bus);
 603 }
 604
 605 char __init *pcibios_setup(char *str)
 606 {
 607         return str;
 608 }
 609
 610 int pcibios_enable_device(struct pci_dev *dev, int mask)
 611 {
 612         u16 cmd, old_cmd;
 613         int idx;
 614         struct resource *r;
 615
 616         PPCDBG(PPCDBG_BUSWALK,"PCI: %s for device %s \n",__FUNCTION__,dev->slot_name);
 617         if (ppc_md.pcibios_enable_device_hook)
 618                 if (ppc_md.pcibios_enable_device_hook(dev, 0))
 619                         return -EINVAL;
 620
 621         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 622         old_cmd = cmd;
 623         for (idx=0; idx<6; idx++) {
 624                 r = &dev->resource[idx];
 625                 if (!r->start && r->end) {
 626                         printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", dev->slot_name);
 627                         return -EINVAL;
 628                 }
 629                 if (r->flags & IORESOURCE_IO)
 630                         cmd |= PCI_COMMAND_IO;
 631                 if (r->flags & IORESOURCE_MEM)
 632                         cmd |= PCI_COMMAND_MEMORY;
 633         }
 634         if (cmd != old_cmd) {
 635                 printk("PCI: Enabling device %s (%04x -> %04x)\n",
 636                        dev->slot_name, old_cmd, cmd);
 637                 PPCDBG(PPCDBG_BUSWALK,"PCI: Enabling device %s \n",dev->slot_name);
 638                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 639         }
 640         return 0;
 641 }
 642
 643 struct pci_controller*
 644 pci_bus_to_hose(int bus)
 645 {
 646         struct pci_controller* hose = hose_head;
 647
 648         for (; hose; hose = hose->next)
 649                 if (bus >= hose->first_busno && bus <= hose->last_busno)
 650                         return hose;
 651         return NULL;
 652 }
 653
 654 void*
 655 pci_bus_io_base(unsigned int bus)
 656 {
 657         struct pci_controller *hose;
 658
 659         hose = pci_bus_to_hose(bus);
 660         if (!hose)
 661                 return NULL;
 662         return hose->io_base_virt;
 663 }
 664
 665 unsigned long
 666 pci_bus_io_base_phys(unsigned int bus)
 667 {
 668         struct pci_controller *hose;
 669
 670         hose = pci_bus_to_hose(bus);
 671         if (!hose)
 672                 return 0;
 673         return hose->io_base_phys;
 674 }
 675
 676 unsigned long
 677 pci_bus_mem_base_phys(unsigned int bus)
 678 {
 679         struct pci_controller *hose;
 680
 681         hose = pci_bus_to_hose(bus);
 682         if (!hose)
 683                 return 0;
 684         return hose->pci_mem_offset;
 685 }
 686
 687 /*
 688  * Return the index of the PCI controller for device pdev.
 689  */
 690 int pci_controller_num(struct pci_dev *dev)
 691 {
 692         struct pci_controller *hose = PCI_GET_PHB_PTR(dev);
 693
 694         return hose->global_number;
 695 }
 696
 697 /*
 698  * Platform support for /proc/bus/pci/X/Y mmap()s,
 699  * modelled on the sparc64 implementation by Dave Miller.
 700  *  -- paulus.
 701  */
 702
 703 /*
 704  * Adjust vm_pgoff of VMA such that it is the physical page offset
 705  * corresponding to the 32-bit pci bus offset for DEV requested by the user.
 706  *
 707  * Basically, the user finds the base address for his device which he wishes
 708  * to mmap.  They read the 32-bit value from the config space base register,
 709  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
 710  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
 711  *
 712  * Returns negative error code on failure, zero on success.
 713  */
 714 static __inline__ int
 715 __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
 716                        enum pci_mmap_state mmap_state)
 717 {
 718         struct pci_controller *hose = PCI_GET_PHB_PTR(dev);
 719         unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
 720         unsigned long io_offset = 0;
 721         int i, res_bit;
 722
 723         if (hose == 0)
 724                 return -EINVAL;         /* should never happen */
 725
 726         /* If memory, add on the PCI bridge address offset */
 727         if (mmap_state == pci_mmap_mem) {
 728                 offset += hose->pci_mem_offset;
 729                 res_bit = IORESOURCE_MEM;
 730         } else {
 731                 io_offset = (unsigned long)hose->io_base_virt;
 732                 offset += io_offset;
 733                 res_bit = IORESOURCE_IO;
 734         }
 735
 736         /*
 737          * Check that the offset requested corresponds to one of the
 738          * resources of the device.
 739          */
 740         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 741                 struct resource *rp = &dev->resource[i];
 742                 int flags = rp->flags;
 743
 744                 /* treat ROM as memory (should be already) */
 745                 if (i == PCI_ROM_RESOURCE)
 746                         flags |= IORESOURCE_MEM;
 747
 748                 /* Active and same type? */
 749                 if ((flags & res_bit) == 0)
 750                         continue;
 751
 752                 /* In the range of this resource? */
 753                 if (offset < (rp->start & PAGE_MASK) || offset > rp->end)
 754                         continue;
 755
 756                 /* found it! construct the final physical address */
 757                 if (mmap_state == pci_mmap_io)
 758                         offset += hose->io_base_phys - io_offset;
 759
 760                 vma->vm_pgoff = offset >> PAGE_SHIFT;
 761                 return 0;
 762         }
 763
 764         return -EINVAL;
 765 }
 766
 767 /*
 768  * Set vm_flags of VMA, as appropriate for this architecture, for a pci device
 769  * mapping.
 770  */
 771 static __inline__ void
 772 __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
 773                      enum pci_mmap_state mmap_state)
 774 {
 775         vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
 776 }
 777
 778 /*
 779  * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
 780  * device mapping.
 781  */
 782 static __inline__ void
 783 __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
 784                       enum pci_mmap_state mmap_state, int write_combine)
 785 {
 786         long prot = pgprot_val(vma->vm_page_prot);
 787
 788         /* XXX would be nice to have a way to ask for write-through */
 789         prot |= _PAGE_NO_CACHE;
 790         prot |= _PAGE_GUARDED;
 791         vma->vm_page_prot = __pgprot(prot);
 792 }
 793
 794 /*
 795  * Perform the actual remap of the pages for a PCI device mapping, as
 796  * appropriate for this architecture.  The region in the process to map
 797  * is described by vm_start and vm_end members of VMA, the base physical
 798  * address is found in vm_pgoff.
 799  * The pci device structure is provided so that architectures may make mapping
 800  * decisions on a per-device or per-bus basis.
 801  *
 802  * Returns a negative error code on failure, zero on success.
 803  */
 804 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 805                         enum pci_mmap_state mmap_state,
 806                         int write_combine)
 807 {
 808         int ret;
 809
 810         ret = __pci_mmap_make_offset(dev, vma, mmap_state);
 811         if (ret < 0)
 812                 return ret;
 813
 814         __pci_mmap_set_flags(dev, vma, mmap_state);
 815         __pci_mmap_set_pgprot(dev, vma, mmap_state, write_combine);
 816
 817         ret = remap_page_range(vma->vm_start, vma->vm_pgoff << PAGE_SHIFT,
 818                                vma->vm_end - vma->vm_start, vma->vm_page_prot);
 819
 820         return ret;
 821 }
 822
 823 /* Provide information on locations of various I/O regions in physical
 824  * memory.  Do this on a per-card basis so that we choose the right
 825  * root bridge.
 826  * Note that the returned IO or memory base is a physical address
 827  */
 828
 829 long
 830 sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
 831 {
 832         struct pci_controller* hose = pci_bus_to_hose(bus);
 833         long result = -EOPNOTSUPP;
 834
 835         if (!hose)
 836                 return -ENODEV;
 837
 838         switch (which) {
 839         case IOBASE_BRIDGE_NUMBER:
 840                 return (long)hose->first_busno;
 841         case IOBASE_MEMORY:
 842                 return (long)hose->pci_mem_offset;
 843         case IOBASE_IO:
 844                 return (long)hose->io_base_phys;
 845         case IOBASE_ISA_IO:
 846                 return (long)isa_io_base;
 847         case IOBASE_ISA_MEM:
 848                 return (long)isa_mem_base;
 849         }
 850
 851         return result;
 852 }
 853 /************************************************************************/
 854 /* Formats the device information and location for service.             */
 855 /* - Pass in pci_dev* pointer to the device.                            */
 856 /* - Pass in buffer to place the data.  Danger here is the buffer must  */
 857 /*   be as big as the client says it is.   Should be at least 128 bytes.*/
 858 /* Return will the length of the string data put in the buffer.         */
 859 /* The brand specific method device_Location is called.                 */
 860 /* Format:                                                              */
 861 /* PCI: Bus  0, Device 26, Vendor 0x12AE  Frame  1, Card  C10  Ethernet */
 862 /* PCI: Bus  0, Device 26, Vendor 0x12AE  Location U0.3-P1-I8  Ethernet */
 863 /* For pSeries, see the Product Topology in the RS/6000 Architecture.   */
 864 /* For iSeries, see the Service Manuals.                                */
 865 /************************************************************************/
 866 int  format_device_location(struct pci_dev* PciDev,char* BufPtr, int BufferSize)
 867 {
 868         struct device_node* DevNode = (struct device_node*)PciDev->sysdata;
 869         int  LineLen = 0;
 870         if (DevNode != NULL && BufferSize >= 128) {
 871                 LineLen += device_Location(PciDev,BufPtr+LineLen);
 872                 LineLen += sprintf(BufPtr+LineLen," %12s",pci_class_name(PciDev->class >> 8) );
 873         }
 874         return LineLen;
 875 }
 876 /************************************************************************
 877  * Saves the config registers for a device.                             *
 878  ************************************************************************
 879  * Note: This does byte reads so the data may appear byte swapped,      *
 880  * The data returned in the pci_config_reg_save_area structure can be   *
 881  * used to the restore of the data.  If the save failed, the data       *
 882  * will not be restore.  Yes I know, you are most likey toast.          *
 883  ************************************************************************/
 884 int pci_save_config_regs(struct pci_dev* PciDev,struct pci_config_reg_save_area* SaveArea)
 885 {
 886         memset(SaveArea,0x00,sizeof(struct pci_config_reg_save_area) );
 887         SaveArea->PciDev    = PciDev;
 888         SaveArea->RCode     = 0;
 889         SaveArea->Register  = 0;
 890         /******************************************************************
 891          * Save All the Regs,  NOTE: restore skips the first 16 bytes.    *
 892          ******************************************************************/
 893         while (SaveArea->Register < REG_SAVE_SIZE && SaveArea->RCode == 0) {
 894                 SaveArea->RCode = pci_read_config_byte(PciDev, SaveArea->Register, &SaveArea->Regs[SaveArea->Register]);
 895                 ++SaveArea->Register;
 896         }
 897         if (SaveArea->RCode != 0) {     /* Ouch */
 898                 SaveArea->Flags = 0x80;
 899                 printk("PCI: pci_restore_save_regs failed! %p\n 0x%04X",PciDev,SaveArea->RCode);
 900                 PCIFR(      "pci_restore_save_regs failed! %p\n 0x%04X",PciDev,SaveArea->RCode);
 901         }
 902         else {
 903                 SaveArea->Flags = 0x01;
 904         }
 905         return  SaveArea->RCode;
 906 }
 907
 908 /************************************************************************
 909  * Restores the registers saved via the save function.  See the save    *
 910  * function for details.                                                *
 911  ************************************************************************/
 912 int pci_restore_config_regs(struct pci_dev* PciDev,struct pci_config_reg_save_area* SaveArea)
 913 {
 914         if (SaveArea->PciDev != PciDev || SaveArea->Flags == 0x80 || SaveArea->RCode != 0) {
 915                 printk("PCI: pci_restore_config_regs failed! %p\n",PciDev);
 916                 return -1;
 917         }
 918         /******************************************************************
 919          * Don't touch the Cmd or BIST regs, user must restore those.     *
 920          * Restore PCI_VENDOR_ID & PCI_DEVICE_ID                          *
 921          * Restore PCI_CACHE_LINE_SIZE & PCI_LATENCY_TIMER                *
 922          * Restore Saved Regs from 0x10 to 0x3F                           *
 923          ******************************************************************/
 924         SaveArea->Register = 0;
 925         while(SaveArea->Register < REG_SAVE_SIZE && SaveArea->RCode == 0) {
 926                 SaveArea->RCode = pci_write_config_byte(PciDev,SaveArea->Register,SaveArea->Regs[SaveArea->Register]);
 927                 ++SaveArea->Register;
 928                 if (     SaveArea->Register == PCI_COMMAND)     SaveArea->Register = PCI_CACHE_LINE_SIZE;
 929                 else if (SaveArea->Register == PCI_HEADER_TYPE) SaveArea->Register = PCI_BASE_ADDRESS_0;
 930         }
 931         if (SaveArea->RCode != 0) {
 932                 printk("PCI: pci_restore_config_regs failed! %p\n 0x%04X",PciDev,SaveArea->RCode);
 933                 PCIFR(      "pci_restore_config_regs failed! %p\n 0x%04X",PciDev,SaveArea->RCode);
 934         }
 935         return  SaveArea->RCode;
 936 }
 937
 938 /************************************************************************/
 939 /* Interface to toggle the reset line                                   */
 940 /* Time is in .1 seconds, need for seconds.                             */
 941 /************************************************************************/
 942 int  pci_reset_device(struct pci_dev* PciDev, int AssertTime, int DelayTime)
 943 {
 944         unsigned long AssertDelay, WaitDelay;
 945         int RtnCode;
 946         /********************************************************************
 947          * Set defaults, Assert is .5 second, Wait is 3 seconds.
 948          ********************************************************************/
 949         if (AssertTime == 0) AssertDelay = ( 5 * HZ)/10;
 950         else                 AssertDelay = (AssertTime*HZ)/10;
 951         if (WaitDelay == 0)  WaitDelay   = (30 * HZ)/10;
 952         else                 WaitDelay   = (DelayTime* HZ)/10;
 953
 954         /********************************************************************
 955          * Assert reset, wait, de-assert reset, wait for IOA to reset.
 956          * - Don't waste the CPU time on jiffies.
 957          ********************************************************************/
 958         RtnCode = pci_set_reset(PciDev,1);
 959         if (RtnCode == 0) {
 960                 set_current_state(TASK_UNINTERRUPTIBLE);
 961                 schedule_timeout(AssertDelay);   /* Sleep for the time     */
 962                 RtnCode = pci_set_reset(PciDev,0);
 963                 set_current_state(TASK_UNINTERRUPTIBLE);
 964                 schedule_timeout(WaitDelay);
 965         }
 966         if (RtnCode == 0) {
 967                 PCIFR(      "Bus%3d, Device%3d, Reset\n",PciDev->bus->number,PCI_SLOT(PciDev->devfn) );
 968         }
 969         else {
 970                 printk("PCI: Bus%3d, Device%3d, Reset Failed:0x%04X\n",PciDev->bus->number,PCI_SLOT(PciDev->devfn),RtnCode );
 971                 PCIFR(      "Bus%3d, Device%3d, Reset Failed:0x%04X\n",PciDev->bus->number,PCI_SLOT(PciDev->devfn),RtnCode );
 972         }
 973         return RtnCode;
 974 }
 975
 976 /*****************************************************
 977  * Dump Resource information
 978  *****************************************************/
 979 void dumpResources(struct resource* Resource)
 980 {
 981         if(Resource != NULL) {
 982                 int Flags = 0x00000F00 & Resource->flags;
 983                 if(Resource->start == 0 && Resource->end == 0) return;
 984                 else if(Resource->start == Resource->end )     return;
 985                 else {
 986                         if     (Flags == IORESOURCE_IO)  udbg_printf("IO.:");
 987                         else if(Flags == IORESOURCE_MEM) udbg_printf("MEM:");
 988                         else if(Flags == IORESOURCE_IRQ) udbg_printf("IRQ:");
 989                         else                             udbg_printf("0x%02X:",Resource->flags);
 990
 991                 }
 992                 udbg_printf("0x%016LX / 0x%016LX (0x%08X)\n",
 993                             Resource->start, Resource->end, Resource->end - Resource->start);
 994         }
 995 }
 996
 997 int  resourceSize(struct resource* Resource)
 998 {
 999         if(Resource->start == 0 && Resource->end == 0) return 0;
1000         else if(Resource->start == Resource->end )     return 0;
1001         else return (Resource->end-1)-Resource->start;
1002 }
1003
1004
1005 /*****************************************************
1006  * Dump PHB information for Debug
1007  *****************************************************/
1008 void dumpPci_Controller(struct pci_controller* phb)
1009 {
1010         udbg_printf("\tpci_controller= 0x%016LX\n", phb);
1011         if (phb != NULL) {
1012                 udbg_printf("\twhat & type   = %s 0x%02X\n ",phb->what,phb->type);
1013                 udbg_printf("\tbus           = ");
1014                 if (phb->bus != NULL) udbg_printf("0x%02X\n",   phb->bus->number);
1015                 else                  udbg_printf("<NULL>\n");
1016                 udbg_printf("\tarch_data     = 0x%016LX\n", phb->arch_data);
1017                 udbg_printf("\tfirst_busno   = 0x%02X\n",   phb->first_busno);
1018                 udbg_printf("\tlast_busno    = 0x%02X\n",   phb->last_busno);
1019                 udbg_printf("\tio_base_virt* = 0x%016LX\n", phb->io_base_virt);
1020                 udbg_printf("\tio_base_phys  = 0x%016LX\n", phb->io_base_phys);
1021                 udbg_printf("\tpci_mem_offset= 0x%016LX\n", phb->pci_mem_offset);
1022                 udbg_printf("\tpci_io_offset = 0x%016LX\n", phb->pci_io_offset);
1023
1024                 udbg_printf("\tcfg_addr      = 0x%016LX\n", phb->cfg_addr);
1025                 udbg_printf("\tcfg_data      = 0x%016LX\n", phb->cfg_data);
1026                 udbg_printf("\tphb_regs      = 0x%016LX\n", phb->phb_regs);
1027                 udbg_printf("\tchip_regs     = 0x%016LX\n", phb->chip_regs);
1028
1029
1030                 udbg_printf("\tResources\n");
1031                 dumpResources(&phb->io_resource);
1032                 if (phb->mem_resource_count >  0) dumpResources(&phb->mem_resources[0]);
1033                 if (phb->mem_resource_count >  1) dumpResources(&phb->mem_resources[1]);
1034                 if (phb->mem_resource_count >  2) dumpResources(&phb->mem_resources[2]);
1035
1036                 udbg_printf("\tglobal_num    = 0x%02X\n",   phb->global_number);
1037                 udbg_printf("\tlocal_num     = 0x%02X\n",   phb->local_number);
1038         }
1039 }
1040
1041 /*****************************************************
1042  * Dump PHB information for Debug
1043  *****************************************************/
1044 void dumpPci_Bus(struct pci_bus* Pci_Bus)
1045 {
1046         int i;
1047         udbg_printf("\tpci_bus         = 0x%016LX   \n",Pci_Bus);
1048         if (Pci_Bus != NULL) {
1049
1050                 udbg_printf("\tnumber          = 0x%02X     \n",Pci_Bus->number);
1051                 udbg_printf("\tprimary         = 0x%02X     \n",Pci_Bus->primary);
1052                 udbg_printf("\tsecondary       = 0x%02X     \n",Pci_Bus->secondary);
1053                 udbg_printf("\tsubordinate     = 0x%02X     \n",Pci_Bus->subordinate);
1054
1055                 for (i=0;i<4;++i) {
1056                         if(Pci_Bus->resource[i] == NULL) continue;
1057                         if(Pci_Bus->resource[i]->start == 0 && Pci_Bus->resource[i]->end == 0) break;
1058                         udbg_printf("\tResources[%d]",i);
1059                         dumpResources(Pci_Bus->resource[i]);
1060                 }
1061         }
1062 }
1063
1064 /*****************************************************
1065  * Dump Device information for Debug
1066  *****************************************************/
1067 void dumpPci_Dev(struct pci_dev* Pci_Dev)
1068 {
1069         int i;
1070         udbg_printf("\tpci_dev*        = 0x%p\n",Pci_Dev);
1071         if ( Pci_Dev == NULL )  return;
1072         udbg_printf("\tname            = %s  \n",Pci_Dev->name);
1073         udbg_printf("\tbus*            = 0x%p\n",Pci_Dev->bus);
1074         udbg_printf("\tsysdata*        = 0x%p\n",Pci_Dev->sysdata);
1075         udbg_printf("\tDevice          = 0x%4X%02X:%02X.%02X 0x%04X:%04X\n",
1076                     PCI_GET_PHB_NUMBER(Pci_Dev),
1077                     PCI_GET_BUS_NUMBER(Pci_Dev),
1078                     PCI_SLOT(Pci_Dev->devfn),
1079                     PCI_FUNC(Pci_Dev->devfn),
1080                     Pci_Dev->vendor,
1081                     Pci_Dev->device);
1082         udbg_printf("\tHdr/Irq         = 0x%02X/0x%02X \n",Pci_Dev->hdr_type,Pci_Dev->irq);
1083         for (i=0;i<DEVICE_COUNT_RESOURCE;++i) {
1084                 if (Pci_Dev->resource[i].start == 0 && Pci_Dev->resource[i].end == 0) continue;
1085                 udbg_printf("\tResources[%d] ",i);
1086                 dumpResources(&Pci_Dev->resource[i]);
1087         }
1088         dumpResources(&Pci_Dev->resource[i]);
1089 }