3 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
5 * Dynamic DMA mapping support.
7 * Manages the TCE space assigned to this partition.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/init.h>
25 #include <linux/types.h>
26 #include <linux/slab.h>
28 #include <linux/spinlock.h>
29 #include <linux/string.h>
30 #include <linux/pci.h>
34 #include <asm/ppcdebug.h>
36 #include <asm/iSeries/HvCallXm.h>
37 #include <asm/iSeries/LparData.h>
38 #include <asm/pci_dma.h>
39 #include <asm/pci-bridge.h>
40 #include <asm/iSeries/iSeries_pci.h>
42 #include <asm/machdep.h>
46 /* #define DEBUG_TCE 1 */
47 /* #define MONITOR_TCE 1 */ /* Turn on to sanity check TCE generation. */
50 /* Initialize so this guy does not end up in the BSS section.
51 * Only used to pass OF initialization data set in prom.c into the main
52 * kernel code -- data ultimately copied into tceTables[].
54 extern struct _of_tce_table of_tce_table[];
56 extern struct pci_controller* hose_head;
57 extern struct pci_controller** hose_tail;
58 extern struct list_head iSeries_Global_Device_List;
60 struct TceTable virtBusVethTceTable; /* Tce table for virtual ethernet */
61 struct TceTable virtBusVioTceTable; /* Tce table for virtual I/O */
63 struct iSeries_Device_Node iSeries_veth_dev_node = { LogicalSlot: 0xFF, DevTceTable: &virtBusVethTceTable };
64 struct iSeries_Device_Node iSeries_vio_dev_node = { LogicalSlot: 0xFF, DevTceTable: &virtBusVioTceTable };
66 struct pci_dev iSeries_veth_dev_st = { sysdata: &iSeries_veth_dev_node };
67 struct pci_dev iSeries_vio_dev_st = { sysdata: &iSeries_vio_dev_node };
69 struct pci_dev * iSeries_veth_dev = &iSeries_veth_dev_st;
70 struct pci_dev * iSeries_vio_dev = &iSeries_vio_dev_st;
72 /* Device TceTable is stored in Device Node */
73 /* struct TceTable * tceTables[256]; */ /* Tce tables for 256 busses
74 * Bus 255 is the virtual bus
75 * zero indicates no bus defined
77 /* allocates a contiguous range of tces (power-of-2 size) */
78 static inline long alloc_tce_range(struct TceTable *,
81 /* allocates a contiguous range of tces (power-of-2 size)
82 * assumes lock already held
84 static long alloc_tce_range_nolock(struct TceTable *,
87 /* frees a contiguous range of tces (power-of-2 size) */
88 static inline void free_tce_range(struct TceTable *,
92 /* frees a contiguous rnage of tces (power-of-2 size)
93 * assumes lock already held
95 void free_tce_range_nolock(struct TceTable *,
99 /* allocates a range of tces and sets them to the pages */
100 static inline dma_addr_t get_tces( struct TceTable *,
106 static long test_tce_range( struct TceTable *,
110 static unsigned fill_scatterlist_sg(struct scatterlist *sg, int nents,
112 unsigned long numTces );
114 static unsigned long num_tces_sg( struct scatterlist *sg,
117 static dma_addr_t create_tces_sg( struct TceTable *tbl,
118 struct scatterlist *sg,
123 static void getTceTableParmsiSeries(struct iSeries_Device_Node* DevNode,
124 struct TceTable *tce_table_parms );
126 static void getTceTableParmsPSeries( struct pci_controller *phb,
127 struct device_node *dn,
128 struct TceTable *tce_table_parms );
130 static void getTceTableParmsPSeriesLP(struct pci_controller *phb,
131 struct device_node *dn,
132 struct TceTable *newTceTable );
134 static struct TceTable* findHwTceTable(struct TceTable * newTceTable );
136 void create_pci_bus_tce_table( unsigned long token );
138 u8 iSeries_Get_Bus( struct pci_dev * dv )
143 static inline struct TceTable *get_tce_table(struct pci_dev *dev)
146 dev = ppc64_isabridge_dev;
149 if (systemcfg->platform == PLATFORM_ISERIES_LPAR) {
150 return ISERIES_DEVNODE(dev)->DevTceTable;
152 return PCI_GET_DN(dev)->tce_table;
156 static unsigned long __inline__ count_leading_zeros64( unsigned long x )
159 asm("cntlzd %0,%1" : "=r"(lz) : "r"(x));
163 static void tce_build_iSeries(struct TceTable *tbl, long tcenum,
164 unsigned long uaddr, int direction )
169 PPCDBG(PPCDBG_TCE, "build_tce: uaddr = 0x%lx\n", uaddr);
170 PPCDBG(PPCDBG_TCE, "\ttcenum = 0x%lx, tbl = 0x%lx, index=%lx\n",
171 tcenum, tbl, tbl->index);
174 tce.tceBits.rpn = (virt_to_absolute(uaddr)) >> PAGE_SHIFT;
176 /* If for virtual bus */
177 if ( tbl->tceType == TCE_VB ) {
178 tce.tceBits.valid = 1;
179 tce.tceBits.allIo = 1;
180 if ( direction != PCI_DMA_TODEVICE )
181 tce.tceBits.readWrite = 1;
184 tce.tceBits.readWrite = 1; // Read allowed
185 if ( direction != PCI_DMA_TODEVICE )
186 tce.tceBits.pciWrite = 1;
189 setTceRc = HvCallXm_setTce((u64)tbl->index,
193 panic("PCI_DMA: HvCallXm_setTce failed, Rc: 0x%lx\n", setTceRc);
197 static void tce_build_pSeries(struct TceTable *tbl, long tcenum,
198 unsigned long uaddr, int direction )
203 PPCDBG(PPCDBG_TCE, "build_tce: uaddr = 0x%lx\n", uaddr);
204 PPCDBG(PPCDBG_TCE, "\ttcenum = 0x%lx, tbl = 0x%lx, index=%lx\n",
205 tcenum, tbl, tbl->index);
208 tce.tceBits.rpn = (virt_to_absolute(uaddr)) >> PAGE_SHIFT;
210 tce.tceBits.readWrite = 1; // Read allowed
211 if ( direction != PCI_DMA_TODEVICE ) tce.tceBits.pciWrite = 1;
213 tce_addr = ((union Tce *)tbl->base) + tcenum;
214 *tce_addr = (union Tce)tce.wholeTce;
219 * Build a TceTable structure. This contains a multi-level bit map which
220 * is used to manage allocation of the tce space.
222 static struct TceTable *build_tce_table( struct TceTable * tbl )
224 unsigned long bits, bytes, totalBytes;
225 unsigned long numBits[NUM_TCE_LEVELS], numBytes[NUM_TCE_LEVELS];
227 unsigned char * pos, * p, b;
229 PPCDBG(PPCDBG_TCEINIT, "build_tce_table: tbl = 0x%lx\n", tbl);
230 spin_lock_init( &(tbl->lock) );
232 tbl->mlbm.maxLevel = 0;
234 /* Compute number of bits and bytes for each level of the
235 * multi-level bit map
238 bits = tbl->size * (PAGE_SIZE / sizeof( union Tce ));
240 for ( i=0; i<NUM_TCE_LEVELS; ++i ) {
241 bytes = ((bits+63)/64) * 8;
242 PPCDBG(PPCDBG_TCEINIT, "build_tce_table: level %d bits=%ld, bytes=%ld\n", i, bits, bytes );
248 PPCDBG(PPCDBG_TCEINIT, "build_tce_table: totalBytes=%ld\n", totalBytes );
250 pos = (char *)__get_free_pages( GFP_ATOMIC, get_order( totalBytes ));
253 panic("PCI_DMA: Allocation failed in build_tce_table!\n");
256 /* For each level, fill in the pointer to the bit map,
257 * and turn on the last bit in the bit map (if the
258 * number of bits in the map is odd). The highest
259 * level will get all of its bits turned on.
261 memset( pos, 0, totalBytes );
262 for (i=0; i<NUM_TCE_LEVELS; ++i) {
264 tbl->mlbm.level[i].map = pos;
265 tbl->mlbm.maxLevel = i;
267 if ( numBits[i] & 1 ) {
268 p = pos + numBytes[i] - 1;
269 m = (( numBits[i] % 8) - 1) & 7;
271 PPCDBG(PPCDBG_TCEINIT, "build_tce_table: level %d last bit %x\n", i, 0x80>>m );
275 tbl->mlbm.level[i].map = 0;
277 tbl->mlbm.level[i].numBits = numBits[i];
278 tbl->mlbm.level[i].numBytes = numBytes[i];
281 /* For the highest level, turn on all the bits */
283 i = tbl->mlbm.maxLevel;
284 p = tbl->mlbm.level[i].map;
286 PPCDBG(PPCDBG_TCEINIT, "build_tce_table: highest level (%d) has all bits set\n", i);
287 for (k=0; k<numBytes[i]; ++k) {
289 /* handle full bytes */
294 /* handle the last partial byte */
310 static inline long alloc_tce_range( struct TceTable *tbl, unsigned order )
315 /* Lock the tce allocation bitmap */
316 spin_lock_irqsave( &(tbl->lock), flags );
318 /* Do the actual work */
319 retval = alloc_tce_range_nolock( tbl, order );
321 /* Unlock the tce allocation bitmap */
322 spin_unlock_irqrestore( &(tbl->lock), flags );
327 static long alloc_tce_range_nolock( struct TceTable *tbl, unsigned order )
329 unsigned long numBits, numBytes;
330 unsigned long i, bit, block, mask;
334 /* If the order (power of 2 size) requested is larger than our
335 * biggest, indicate failure
337 if(order >= NUM_TCE_LEVELS) {
338 /* This can happen if block of TCE's are not found. This code */
339 /* maybe in a recursive loop looking up the bit map for the range.*/
340 panic("PCI_DMA: alloc_tce_range_nolock: invalid order: %d\n",order);
343 numBits = tbl->mlbm.level[order].numBits;
344 numBytes = tbl->mlbm.level[order].numBytes;
345 map = (u64 *)tbl->mlbm.level[order].map;
347 /* Initialize return value to -1 (failure) */
350 /* Loop through the bytes of the bitmap */
351 for (i=0; i<numBytes/8; ++i) {
353 /* A free block is found, compute the block
354 * number (of this size)
356 bit = count_leading_zeros64( *map );
357 block = (i * 64) + bit; /* Bit count to free entry */
359 /* turn off the bit in the map to indicate
360 * that the block is now in use
362 mask = 0x1UL << (63 - bit);
365 /* compute the index into our tce table for
366 * the first tce in the block
368 PPCDBG(PPCDBG_TCE, "alloc_tce_range_nolock: allocating block %ld, (byte=%ld, bit=%ld) order %d\n", block, i, bit, order );
369 tcenum = block << order;
376 if ( tcenum == -1 ) {
377 PPCDBG(PPCDBG_TCE, "alloc_tce_range_nolock: no available blocks of order = %d\n", order );
378 if ( order < tbl->mlbm.maxLevel ) {
379 PPCDBG(PPCDBG_TCE, "alloc_tce_range_nolock: trying next bigger size\n" );
382 panic("PCI_DMA: alloc_tce_range_nolock: maximum size reached...failing\n");
387 /* If no block of the requested size was found, try the next
388 * size bigger. If one of those is found, return the second
389 * half of the block to freespace and keep the first half
391 if((tcenum == -1) && (order < (NUM_TCE_LEVELS - 1))) {
392 tcenum = alloc_tce_range_nolock( tbl, order+1 );
393 if ( tcenum != -1 ) {
394 free_tce_range_nolock( tbl, tcenum+(1<<order), order );
398 /* Return the index of the first tce in the block
399 * (or -1 if we failed)
404 static inline void free_tce_range(struct TceTable *tbl,
405 long tcenum, unsigned order )
409 /* Lock the tce allocation bitmap */
410 spin_lock_irqsave( &(tbl->lock), flags );
412 /* Do the actual work */
413 free_tce_range_nolock( tbl, tcenum, order );
415 /* Unlock the tce allocation bitmap */
416 spin_unlock_irqrestore( &(tbl->lock), flags );
420 void free_tce_range_nolock(struct TceTable *tbl,
421 long tcenum, unsigned order )
424 unsigned byte, bit, mask, b;
425 unsigned char * map, * bytep;
427 if (order >= NUM_TCE_LEVELS) {
428 panic("PCI_DMA: free_tce_range: invalid order: 0x%x\n",order);
432 block = tcenum >> order;
435 if ( tcenum != (block << order ) ) {
436 printk("PCI_DMA: Free_tce_range: tcenum %lx misaligned for order %x\n",tcenum, order);
439 if ( block >= tbl->mlbm.level[order].numBits ) {
440 printk("PCI_DMA: Free_tce_range: tcenum %lx is outside the range of this map (order %x, numBits %lx\n",
441 tcenum, order, tbl->mlbm.level[order].numBits );
444 if ( test_tce_range( tbl, tcenum, order ) ) {
445 printk("PCI_DMA: Freeing range not allocated: tTceTable %p, tcenum %lx, order %x\n",tbl, tcenum, order );
450 map = tbl->mlbm.level[order].map;
457 PPCDBG(PPCDBG_TCE,"free_tce_range_nolock: freeing block %ld (byte=%d, bit=%d) of order %d\n",
458 block, byte, bit, order);
462 if ( *bytep & mask ) {
463 panic("PCI_DMA: Tce already free: TceTable %p, tcenum %lx, order %x\n",tbl,tcenum,order);
469 /* If there is a higher level in the bit map than this we may be
470 * able to buddy up this block with its partner.
471 * If this is the highest level we can't buddy up
472 * If this level has an odd number of bits and
473 * we are freeing the last block we can't buddy up
474 * Don't buddy up if it's in the first 1/4 of the level
476 if (( order < tbl->mlbm.maxLevel ) &&
477 ( block > (tbl->mlbm.level[order].numBits/4) ) &&
478 (( block < tbl->mlbm.level[order].numBits-1 ) ||
479 ( 0 == ( tbl->mlbm.level[order].numBits & 1)))) {
480 /* See if we can buddy up the block we just freed */
481 bit &= 6; /* get to the first of the buddy bits */
482 mask = 0xc0 >> bit; /* build two bit mask */
483 b = *bytep & mask; /* Get the two bits */
484 if ( 0 == (b ^ mask) ) { /* If both bits are on */
485 /* both of the buddy blocks are free we can combine them */
486 *bytep ^= mask; /* turn off the two bits */
487 block = ( byte * 8 ) + bit; /* block of first of buddies */
488 tcenum = block << order;
489 /* free the buddied block */
491 "free_tce_range: buddying blocks %ld & %ld\n",
493 free_tce_range_nolock( tbl, tcenum, order+1 );
498 static long test_tce_range( struct TceTable *tbl, long tcenum, unsigned order )
501 unsigned byte, bit, mask, b;
502 long retval, retLeft, retRight;
505 map = tbl->mlbm.level[order].map;
506 block = tcenum >> order;
507 byte = block / 8; /* Byte within bitmap */
508 bit = block % 8; /* Bit within byte */
510 b = (*(map+byte) & mask ); /* 0 if block is allocated, else free */
512 retval = 1; /* 1 == block is free */
514 retval = 0; /* 0 == block is allocated */
515 /* Test bits at all levels below this to ensure that all agree */
518 retLeft = test_tce_range( tbl, tcenum, order-1 );
519 retRight = test_tce_range( tbl, tcenum+(1<<(order-1)), order-1 );
520 if ( retLeft || retRight ) {
525 /* Test bits at all levels above this to ensure that all agree */
530 static inline dma_addr_t get_tces( struct TceTable *tbl, unsigned order, void *page, unsigned numPages, int direction )
535 dma_addr_t retTce = NO_TCE;
537 uaddr = (unsigned long)page & PAGE_MASK;
539 /* Allocate a range of tces */
540 tcenum = alloc_tce_range( tbl, order );
541 if ( tcenum != -1 ) {
542 /* We got the tces we wanted */
543 tcenum += tbl->startOffset; /* Offset into real TCE table */
544 retTce = tcenum << PAGE_SHIFT; /* Set the return dma address */
545 /* Setup a tce for each page */
546 for (i=0; i<numPages; ++i) {
547 ppc_md.tce_build(tbl, tcenum, uaddr, direction);
551 /* Make sure the update is visible to hardware.
552 sync required to synchronize the update to
553 the TCE table with the MMIO that will send
554 the bus address to the IOA */
555 __asm__ __volatile__ ("sync" : : : "memory");
558 panic("PCI_DMA: Tce Allocation failure in get_tces. 0x%p\n",tbl);
564 static void tce_free_one_iSeries( struct TceTable *tbl, long tcenum )
569 set_tce_rc = HvCallXm_setTce((u64)tbl->index,
573 panic("PCI_DMA: HvCallXm_setTce failed, Rc: 0x%lx\n", set_tce_rc);
577 static void tce_free_one_pSeries( struct TceTable *tbl, long tcenum )
584 tce_addr = ((union Tce *)tbl->base) + tcenum;
585 *tce_addr = (union Tce)tce.wholeTce;
589 static void tce_free(struct TceTable *tbl, dma_addr_t dma_addr,
590 unsigned order, unsigned num_pages)
592 long tcenum, total_tces, free_tce;
595 total_tces = (tbl->size * (PAGE_SIZE / sizeof(union Tce)));
597 tcenum = dma_addr >> PAGE_SHIFT;
598 free_tce = tcenum - tbl->startOffset;
600 if ( ( (free_tce + num_pages) > total_tces ) ||
601 ( tcenum < tbl->startOffset ) ) {
602 printk("tce_free: invalid tcenum\n");
603 printk("\ttcenum = 0x%lx\n", tcenum);
604 printk("\tTCE Table = 0x%lx\n", (u64)tbl);
605 printk("\tbus# = 0x%lx\n", (u64)tbl->busNumber );
606 printk("\tsize = 0x%lx\n", (u64)tbl->size);
607 printk("\tstartOff = 0x%lx\n", (u64)tbl->startOffset );
608 printk("\tindex = 0x%lx\n", (u64)tbl->index);
612 for (i=0; i<num_pages; ++i) {
613 ppc_md.tce_free_one(tbl, tcenum);
617 /* No sync (to make TCE change visible) is required here.
618 The lwsync when acquiring the lock in free_tce_range
619 is sufficient to synchronize with the bitmap.
622 free_tce_range( tbl, free_tce, order );
625 void __init create_virtual_bus_tce_table(void)
628 struct TceTableManagerCB virtBusTceTableParms;
631 virtBusTceTableParms.busNumber = 255; /* Bus 255 is the virtual bus */
632 virtBusTceTableParms.virtualBusFlag = 0xff; /* Ask for virtual bus */
634 absParmsPtr = virt_to_absolute( (u64)&virtBusTceTableParms );
635 HvCallXm_getTceTableParms( absParmsPtr );
637 virtBusVethTceTable.size = virtBusTceTableParms.size / 2;
638 virtBusVethTceTable.busNumber = virtBusTceTableParms.busNumber;
639 virtBusVethTceTable.startOffset = virtBusTceTableParms.startOffset;
640 virtBusVethTceTable.index = virtBusTceTableParms.index;
641 virtBusVethTceTable.tceType = TCE_VB;
643 virtBusVioTceTable.size = virtBusTceTableParms.size - virtBusVethTceTable.size;
644 virtBusVioTceTable.busNumber = virtBusTceTableParms.busNumber;
645 virtBusVioTceTable.startOffset = virtBusTceTableParms.startOffset +
646 virtBusVethTceTable.size * (PAGE_SIZE/sizeof(union Tce));
647 virtBusVioTceTable.index = virtBusTceTableParms.index;
648 virtBusVioTceTable.tceType = TCE_VB;
650 t = build_tce_table( &virtBusVethTceTable );
652 /* tceTables[255] = t; */
653 //VirtBusVethTceTable = t;
654 printk( "Virtual Bus VETH TCE table built successfully.\n");
655 printk( " TCE table size = %ld entries\n",
656 (unsigned long)t->size*(PAGE_SIZE/sizeof(union Tce)) );
657 printk( " TCE table token = %d\n",
658 (unsigned)t->index );
659 printk( " TCE table start entry = 0x%lx\n",
660 (unsigned long)t->startOffset );
662 else printk( "Virtual Bus VETH TCE table failed.\n");
664 t = build_tce_table( &virtBusVioTceTable );
666 //VirtBusVioTceTable = t;
667 printk( "Virtual Bus VIO TCE table built successfully.\n");
668 printk( " TCE table size = %ld entries\n",
669 (unsigned long)t->size*(PAGE_SIZE/sizeof(union Tce)) );
670 printk( " TCE table token = %d\n",
671 (unsigned)t->index );
672 printk( " TCE table start entry = 0x%lx\n",
673 (unsigned long)t->startOffset );
675 else printk( "Virtual Bus VIO TCE table failed.\n");
678 void create_tce_tables_for_buses(struct list_head *bus_list)
680 struct pci_controller* phb;
681 struct device_node *dn, *first_dn;
682 int num_slots, num_slots_ilog2;
685 for (phb=hose_head;phb;phb=phb->next) {
686 first_dn = ((struct device_node *)phb->arch_data)->child;
687 /* Carve 2GB into the largest dma_window_size possible */
688 for (dn = first_dn, num_slots = 0; dn != NULL; dn = dn->sibling)
690 num_slots_ilog2 = __ilog2(num_slots);
691 if ((1<<num_slots_ilog2) != num_slots)
693 phb->dma_window_size = 1 << (22 - num_slots_ilog2);
694 /* Reserve 16MB of DMA space on the first PHB.
695 * We should probably be more careful and use firmware props.
696 * In reality this space is remapped, not lost. But we don't
697 * want to get that smart to handle it -- too much work.
699 phb->dma_window_base_cur = first_phb ? (1 << 12) : 0;
701 for (dn = first_dn, num_slots = 0; dn != NULL; dn = dn->sibling) {
702 create_pci_bus_tce_table((unsigned long)dn);
707 void create_tce_tables_for_busesLP(struct list_head *bus_list)
709 struct list_head *ln;
711 struct device_node *busdn;
713 for (ln=bus_list->next; ln != bus_list; ln=ln->next) {
715 busdn = PCI_GET_DN(bus);
716 /* NOTE: there should never be a window declared on a bus when
717 * child devices also have a window. If this should ever be
718 * architected, we probably want children to have priority.
719 * In reality, the PHB containing ISA has the property, but otherwise
720 * it is the pci-bridges that have the property.
722 dma_window = (u32 *)get_property(busdn, "ibm,dma-window", 0);
724 /* Busno hasn't been copied yet.
725 * Do it now because getTceTableParmsPSeriesLP needs it.
727 busdn->busno = bus->number;
728 create_pci_bus_tce_table((unsigned long)busdn);
730 create_tce_tables_for_busesLP(&bus->children);
734 void create_tce_tables(void) {
736 struct device_node *dn, *mydn;
738 if (systemcfg->platform == PLATFORM_PSERIES_LPAR) {
739 create_tce_tables_for_busesLP(&pci_root_buses);
742 create_tce_tables_for_buses(&pci_root_buses);
744 /* Now copy the tce_table ptr from the bus devices down to every
745 * pci device_node. This means get_tce_table() won't need to search
746 * up the device tree to find it.
748 pci_for_each_dev(dev) {
749 mydn = dn = PCI_GET_DN(dev);
750 while (dn && dn->tce_table == NULL)
753 mydn->tce_table = dn->tce_table;
760 * iSeries token = iSeries_device_Node*
761 * pSeries token = pci_controller*
764 void create_pci_bus_tce_table( unsigned long token ) {
765 struct TceTable * newTceTable;
767 PPCDBG(PPCDBG_TCE, "Entering create_pci_bus_tce_table.\n");
768 PPCDBG(PPCDBG_TCE, "\ttoken = 0x%lx\n", token);
770 newTceTable = (struct TceTable *)kmalloc( sizeof(struct TceTable), GFP_KERNEL );
772 /*****************************************************************/
773 /* For the iSeries machines, the HvTce Table can be one of three */
775 /* - Single bus TCE table, */
776 /* - Tce Table Share between buses, */
777 /* - Tce Table per logical slot. */
778 /*****************************************************************/
779 if(systemcfg->platform == PLATFORM_ISERIES_LPAR) {
781 struct iSeries_Device_Node* DevNode = (struct iSeries_Device_Node*)token;
782 getTceTableParmsiSeries(DevNode,newTceTable);
784 /* Look for existing TCE table for this device. */
785 DevNode->DevTceTable = findHwTceTable(newTceTable );
786 if( DevNode->DevTceTable == NULL) {
787 DevNode->DevTceTable = build_tce_table( newTceTable );
790 /* We're using a shared table, free this new one. */
793 printk("Pci Device 0x%p TceTable: %p\n",DevNode,DevNode->DevTceTable);
798 struct device_node *dn;
799 struct pci_controller *phb;
801 dn = (struct device_node *)token;
803 if (systemcfg->platform == PLATFORM_PSERIES)
804 getTceTableParmsPSeries(phb, dn, newTceTable);
806 getTceTableParmsPSeriesLP(phb, dn, newTceTable);
808 dn->tce_table = build_tce_table( newTceTable );
812 /***********************************************************************/
813 /* This function compares the known Tce tables to find a TceTable that */
814 /* has already been built for hardware TCEs. */
815 /* Search the complete(all devices) for a TCE table assigned. If the */
816 /* startOffset, index, and size match, then the TCE for this device has*/
817 /* already been built and it should be shared with this device */
818 /***********************************************************************/
819 static struct TceTable* findHwTceTable(struct TceTable * newTceTable )
821 struct list_head* Device_Node_Ptr = iSeries_Global_Device_List.next;
822 /* Cache the compare values. */
823 u64 startOffset = newTceTable->startOffset;
824 u64 index = newTceTable->index;
825 u64 size = newTceTable->size;
827 while(Device_Node_Ptr != &iSeries_Global_Device_List) {
828 struct iSeries_Device_Node* CmprNode = (struct iSeries_Device_Node*)Device_Node_Ptr;
829 if( CmprNode->DevTceTable != NULL &&
830 CmprNode->DevTceTable->tceType == TCE_PCI) {
831 if( CmprNode->DevTceTable->startOffset == startOffset &&
832 CmprNode->DevTceTable->index == index &&
833 CmprNode->DevTceTable->size == size ) {
834 printk("PCI TCE table matches 0x%p \n",CmprNode->DevTceTable);
835 return CmprNode->DevTceTable;
838 /* Get next Device Node in List */
839 Device_Node_Ptr = Device_Node_Ptr->next;
844 /***********************************************************************/
845 /* Call Hv with the architected data structure to get TCE table info. */
846 /* info. Put the returned data into the Linux representation of the */
847 /* TCE table data. */
848 /* The Hardware Tce table comes in three flavors. */
849 /* 1. TCE table shared between Buses. */
850 /* 2. TCE table per Bus. */
851 /* 3. TCE Table per IOA. */
852 /***********************************************************************/
853 static void getTceTableParmsiSeries(struct iSeries_Device_Node* DevNode,
854 struct TceTable* newTceTable )
856 struct TceTableManagerCB* pciBusTceTableParms = (struct TceTableManagerCB*)kmalloc( sizeof(struct TceTableManagerCB), GFP_KERNEL );
857 if(pciBusTceTableParms == NULL) panic("PCI_DMA: TCE Table Allocation failed.");
859 memset( (void*)pciBusTceTableParms,0,sizeof(struct TceTableManagerCB) );
860 pciBusTceTableParms->busNumber = ISERIES_BUS(DevNode);
861 pciBusTceTableParms->logicalSlot = DevNode->LogicalSlot;
862 pciBusTceTableParms->virtualBusFlag = 0;
864 HvCallXm_getTceTableParms( REALADDR(pciBusTceTableParms) );
866 /* PciTceTableParms Bus:0x18 Slot:0x04 Start:0x000000 Offset:0x04c000 Size:0x0020 */
867 printk("PciTceTableParms Bus:0x%02lx Slot:0x%02x Start:0x%06lx Offset:0x%06lx Size:0x%04lx\n",
868 pciBusTceTableParms->busNumber,
869 pciBusTceTableParms->logicalSlot,
870 pciBusTceTableParms->start,
871 pciBusTceTableParms->startOffset,
872 pciBusTceTableParms->size);
874 if(pciBusTceTableParms->size == 0) {
875 printk("PCI_DMA: Possible Structure mismatch, 0x%p\n",pciBusTceTableParms);
876 panic( "PCI_DMA: pciBusTceTableParms->size is zero, halt here!");
879 newTceTable->size = pciBusTceTableParms->size;
880 newTceTable->busNumber = pciBusTceTableParms->busNumber;
881 newTceTable->startOffset = pciBusTceTableParms->startOffset;
882 newTceTable->index = pciBusTceTableParms->index;
883 newTceTable->tceType = TCE_PCI;
885 kfree(pciBusTceTableParms);
888 static void getTceTableParmsPSeries(struct pci_controller *phb,
889 struct device_node *dn,
890 struct TceTable *newTceTable ) {
894 node = ((struct device_node *)(phb->arch_data))->node;
896 PPCDBG(PPCDBG_TCEINIT, "getTceTableParms: start\n");
897 PPCDBG(PPCDBG_TCEINIT, "\tof_tce_table = 0x%lx\n", of_tce_table);
898 PPCDBG(PPCDBG_TCEINIT, "\tphb = 0x%lx\n", phb);
899 PPCDBG(PPCDBG_TCEINIT, "\tdn = 0x%lx\n", dn);
900 PPCDBG(PPCDBG_TCEINIT, "\tdn->name = %s\n", dn->name);
901 PPCDBG(PPCDBG_TCEINIT, "\tdn->full_name= %s\n", dn->full_name);
902 PPCDBG(PPCDBG_TCEINIT, "\tnewTceTable = 0x%lx\n", newTceTable);
903 PPCDBG(PPCDBG_TCEINIT, "\tdma_window_size = 0x%lx\n", phb->dma_window_size);
906 while(of_tce_table[i].node) {
907 PPCDBG(PPCDBG_TCEINIT, "\tof_tce_table[%d].node = 0x%lx\n",
908 i, of_tce_table[i].node);
909 PPCDBG(PPCDBG_TCEINIT, "\tof_tce_table[%d].base = 0x%lx\n",
910 i, of_tce_table[i].base);
911 PPCDBG(PPCDBG_TCEINIT, "\tof_tce_table[%d].size = 0x%lx\n",
912 i, of_tce_table[i].size >> PAGE_SHIFT);
913 PPCDBG(PPCDBG_TCEINIT, "\tphb->arch_data->node = 0x%lx\n",
916 if(of_tce_table[i].node == node) {
917 memset((void *)of_tce_table[i].base,
918 0, of_tce_table[i].size);
919 newTceTable->busNumber = phb->bus->number;
921 /* Units of tce entries. */
922 newTceTable->startOffset = phb->dma_window_base_cur;
924 /* Adjust the current table offset to the next */
925 /* region. Measured in TCE entries. Force an */
926 /* alignment to the size alloted per IOA. This */
927 /* makes it easier to remove the 1st 16MB. */
928 phb->dma_window_base_cur += (phb->dma_window_size>>3);
929 phb->dma_window_base_cur &=
930 ~((phb->dma_window_size>>3)-1);
932 /* Set the tce table size - measured in units */
933 /* of pages of tce table. */
934 newTceTable->size = ((phb->dma_window_base_cur -
935 newTceTable->startOffset) << 3)
938 /* Test if we are going over 2GB of DMA space. */
939 if(phb->dma_window_base_cur > (1 << 19)) {
940 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
943 newTceTable->base = of_tce_table[i].base;
944 newTceTable->index = 0;
946 PPCDBG(PPCDBG_TCEINIT,
947 "\tnewTceTable->base = 0x%lx\n",
949 PPCDBG(PPCDBG_TCEINIT,
950 "\tnewTceTable->startOffset = 0x%lx"
952 newTceTable->startOffset);
953 PPCDBG(PPCDBG_TCEINIT,
954 "\tnewTceTable->size = 0x%lx"
955 "(# pages of tce table)\n",
963 * getTceTableParmsPSeriesLP
965 * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
967 * ToDo: properly interpret the ibm,dma-window property. The definition is:
968 * logical-bus-number (1 word)
969 * phys-address (#address-cells words)
970 * size (#cell-size words)
972 * Currently we hard code these sizes (more or less).
974 static void getTceTableParmsPSeriesLP(struct pci_controller *phb,
975 struct device_node *dn,
976 struct TceTable *newTceTable ) {
977 u32 *dma_window = (u32 *)get_property(dn, "ibm,dma-window", 0);
979 panic("PCI_DMA: getTceTableParmsPSeriesLP: device %s has no ibm,dma-window property!\n", dn->full_name);
982 newTceTable->busNumber = dn->busno;
983 newTceTable->size = (((((unsigned long)dma_window[4] << 32) | (unsigned long)dma_window[5]) >> PAGE_SHIFT) << 3) >> PAGE_SHIFT;
984 newTceTable->startOffset = ((((unsigned long)dma_window[2] << 32) | (unsigned long)dma_window[3]) >> 12);
985 newTceTable->base = 0;
986 newTceTable->index = dma_window[0];
987 PPCDBG(PPCDBG_TCEINIT, "getTceTableParmsPSeriesLP for bus 0x%lx:\n", dn->busno);
988 PPCDBG(PPCDBG_TCEINIT, "\tDevice = %s\n", dn->full_name);
989 PPCDBG(PPCDBG_TCEINIT, "\tnewTceTable->index = 0x%lx\n", newTceTable->index);
990 PPCDBG(PPCDBG_TCEINIT, "\tnewTceTable->startOffset = 0x%lx\n", newTceTable->startOffset);
991 PPCDBG(PPCDBG_TCEINIT, "\tnewTceTable->size = 0x%lx\n", newTceTable->size);
994 /* Allocates a contiguous real buffer and creates TCEs over it.
995 * Returns the virtual address of the buffer and sets dma_handle
996 * to the dma address (tce) of the first page.
998 void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
999 dma_addr_t *dma_handle)
1001 struct TceTable * tbl;
1003 unsigned order, nPages;
1006 PPCDBG(PPCDBG_TCE, "pci_alloc_consistent:\n");
1007 PPCDBG(PPCDBG_TCE, "\thwdev = 0x%16.16lx\n", hwdev);
1008 PPCDBG(PPCDBG_TCE, "\tsize = 0x%16.16lx\n", size);
1009 PPCDBG(PPCDBG_TCE, "\tdma_handle = 0x%16.16lx\n", dma_handle);
1011 size = PAGE_ALIGN(size);
1012 order = get_order(size);
1013 nPages = 1 << order;
1015 /* Client asked for way to much space. This is checked later anyway */
1016 /* It is easier to debug here for the drivers than in the tce tables.*/
1017 if(order >= NUM_TCE_LEVELS) {
1018 printk("PCI_DMA: pci_alloc_consistent size to large: 0x%lx \n",size);
1019 return (void *)NO_TCE;
1022 tbl = get_tce_table(hwdev);
1025 /* Alloc enough pages (and possibly more) */
1026 ret = (void *)__get_free_pages( GFP_ATOMIC, order );
1028 /* Page allocation succeeded */
1029 memset(ret, 0, nPages << PAGE_SHIFT);
1030 /* Set up tces to cover the allocated range */
1031 tce = get_tces( tbl, order, ret, nPages, PCI_DMA_BIDIRECTIONAL );
1032 if ( tce == NO_TCE ) {
1033 PPCDBG(PPCDBG_TCE, "pci_alloc_consistent: get_tces failed\n" );
1034 free_pages( (unsigned long)ret, order );
1042 else PPCDBG(PPCDBG_TCE, "pci_alloc_consistent: __get_free_pages failed for order = %d\n", order);
1044 else PPCDBG(PPCDBG_TCE, "pci_alloc_consistent: get_tce_table failed for 0x%016lx\n", hwdev);
1046 PPCDBG(PPCDBG_TCE, "\tpci_alloc_consistent: dma_handle = 0x%16.16lx\n", *dma_handle);
1047 PPCDBG(PPCDBG_TCE, "\tpci_alloc_consistent: return = 0x%16.16lx\n", ret);
1051 void pci_free_consistent(struct pci_dev *hwdev, size_t size,
1052 void *vaddr, dma_addr_t dma_handle)
1054 struct TceTable * tbl;
1055 unsigned order, nPages;
1057 PPCDBG(PPCDBG_TCE, "pci_free_consistent:\n");
1058 PPCDBG(PPCDBG_TCE, "\thwdev = 0x%16.16lx, size = 0x%16.16lx, dma_handle = 0x%16.16lx, vaddr = 0x%16.16lx\n", hwdev, size, dma_handle, vaddr);
1060 size = PAGE_ALIGN(size);
1061 order = get_order(size);
1062 nPages = 1 << order;
1064 /* Client asked for way to much space. This is checked later anyway */
1065 /* It is easier to debug here for the drivers than in the tce tables.*/
1066 if(order >= NUM_TCE_LEVELS) {
1067 printk("PCI_DMA: pci_free_consistent size to large: 0x%lx \n",size);
1071 tbl = get_tce_table(hwdev);
1074 tce_free(tbl, dma_handle, order, nPages);
1075 free_pages( (unsigned long)vaddr, order );
1079 /* Creates TCEs for a user provided buffer. The user buffer must be
1080 * contiguous real kernel storage (not vmalloc). The address of the buffer
1081 * passed here is the kernel (virtual) address of the buffer. The buffer
1082 * need not be page aligned, the dma_addr_t returned will point to the same
1083 * byte within the page as vaddr.
1085 dma_addr_t pci_map_single(struct pci_dev *hwdev, void *vaddr,
1086 size_t size, int direction )
1088 struct TceTable * tbl;
1089 dma_addr_t dma_handle = NO_TCE;
1090 unsigned long uaddr;
1091 unsigned order, nPages;
1093 PPCDBG(PPCDBG_TCE, "pci_map_single:\n");
1094 PPCDBG(PPCDBG_TCE, "\thwdev = 0x%16.16lx, size = 0x%16.16lx, direction = 0x%16.16lx, vaddr = 0x%16.16lx\n", hwdev, size, direction, vaddr);
1095 if ( direction == PCI_DMA_NONE )
1098 uaddr = (unsigned long)vaddr;
1099 nPages = PAGE_ALIGN( uaddr + size ) - ( uaddr & PAGE_MASK );
1100 order = get_order( nPages & PAGE_MASK );
1101 nPages >>= PAGE_SHIFT;
1103 /* Client asked for way to much space. This is checked later anyway */
1104 /* It is easier to debug here for the drivers than in the tce tables.*/
1105 if(order >= NUM_TCE_LEVELS) {
1106 printk("PCI_DMA: pci_map_single size to large: 0x%lx \n",size);
1110 tbl = get_tce_table(hwdev);
1113 dma_handle = get_tces( tbl, order, vaddr, nPages, direction );
1114 dma_handle |= ( uaddr & ~PAGE_MASK );
1120 void pci_unmap_single( struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction )
1122 struct TceTable * tbl;
1123 unsigned order, nPages;
1125 PPCDBG(PPCDBG_TCE, "pci_unmap_single:\n");
1126 PPCDBG(PPCDBG_TCE, "\thwdev = 0x%16.16lx, size = 0x%16.16lx, direction = 0x%16.16lx, dma_handle = 0x%16.16lx\n", hwdev, size, direction, dma_handle);
1127 if ( direction == PCI_DMA_NONE )
1130 nPages = PAGE_ALIGN( dma_handle + size ) - ( dma_handle & PAGE_MASK );
1131 order = get_order( nPages & PAGE_MASK );
1132 nPages >>= PAGE_SHIFT;
1134 /* Client asked for way to much space. This is checked later anyway */
1135 /* It is easier to debug here for the drivers than in the tce tables.*/
1136 if(order >= NUM_TCE_LEVELS) {
1137 printk("PCI_DMA: pci_unmap_single size to large: 0x%lx \n",size);
1141 tbl = get_tce_table(hwdev);
1144 tce_free(tbl, dma_handle, order, nPages);
1148 /* Figure out how many TCEs are actually going to be required
1149 * to map this scatterlist. This code is not optimal. It
1150 * takes into account the case where entry n ends in the same
1151 * page in which entry n+1 starts. It does not handle the
1152 * general case of entry n ending in the same page in which
1155 static unsigned long num_tces_sg( struct scatterlist *sg, int nents )
1157 unsigned long nTces, numPages, startPage, endPage, prevEndPage;
1163 for (i=0; i<nents; ++i) {
1164 /* Compute the starting page number and
1165 * the ending page number for this entry
1167 startPage = (unsigned long)sg->address >> PAGE_SHIFT;
1168 endPage = ((unsigned long)sg->address + sg->length - 1) >> PAGE_SHIFT;
1169 numPages = endPage - startPage + 1;
1170 /* Simple optimization: if the previous entry ended
1171 * in the same page in which this entry starts
1172 * then we can reduce the required pages by one.
1173 * This matches assumptions in fill_scatterlist_sg and
1176 if ( startPage == prevEndPage )
1179 prevEndPage = endPage;
1185 /* Fill in the dma data in the scatterlist
1186 * return the number of dma sg entries created
1188 static unsigned fill_scatterlist_sg( struct scatterlist *sg, int nents,
1189 dma_addr_t dma_addr , unsigned long numTces)
1191 struct scatterlist *dma_sg;
1193 unsigned long cur_len_dma, cur_end_virt, uaddr;
1194 unsigned num_dma_ents;
1199 /* Process the first sg entry */
1200 cur_start_dma = dma_addr + ((unsigned long)sg->address & (~PAGE_MASK));
1201 cur_len_dma = sg->length;
1202 /* cur_end_virt holds the address of the byte immediately after the
1203 * end of the current buffer.
1205 cur_end_virt = (unsigned long)sg->address + cur_len_dma;
1206 /* Later code assumes that unused sg->dma_address and sg->dma_length
1207 * fields will be zero. Other archs seem to assume that the user
1208 * (device driver) guarantees that...I don't want to depend on that
1210 sg->dma_address = sg->dma_length = 0;
1212 /* Process the rest of the sg entries */
1215 /* Clear possibly unused fields. Note: sg >= dma_sg so
1216 * this can't be clearing a field we've already set
1218 sg->dma_address = sg->dma_length = 0;
1220 /* Check if it is possible to make this next entry
1221 * contiguous (in dma space) with the previous entry.
1224 /* The entries can be contiguous in dma space if
1225 * the previous entry ends immediately before the
1226 * start of the current entry (in virtual space)
1227 * or if the previous entry ends at a page boundary
1228 * and the current entry starts at a page boundary.
1230 uaddr = (unsigned long)sg->address;
1231 if ( ( uaddr != cur_end_virt ) &&
1232 ( ( ( uaddr | cur_end_virt ) & (~PAGE_MASK) ) ||
1233 ( ( uaddr & PAGE_MASK ) == ( ( cur_end_virt-1 ) & PAGE_MASK ) ) ) ) {
1234 /* This entry can not be contiguous in dma space.
1235 * save the previous dma entry and start a new one
1237 dma_sg->dma_address = cur_start_dma;
1238 dma_sg->dma_length = cur_len_dma;
1243 cur_start_dma += cur_len_dma-1;
1244 /* If the previous entry ends and this entry starts
1245 * in the same page then they share a tce. In that
1246 * case don't bump cur_start_dma to the next page
1247 * in dma space. This matches assumptions made in
1248 * num_tces_sg and create_tces_sg.
1250 if ((uaddr & PAGE_MASK) == ((cur_end_virt-1) & PAGE_MASK))
1251 cur_start_dma &= PAGE_MASK;
1253 cur_start_dma = PAGE_ALIGN(cur_start_dma+1);
1254 cur_start_dma += ( uaddr & (~PAGE_MASK) );
1257 /* Accumulate the length of this entry for the next
1260 cur_len_dma += sg->length;
1261 cur_end_virt = uaddr + sg->length;
1263 /* Fill in the last dma entry */
1264 dma_sg->dma_address = cur_start_dma;
1265 dma_sg->dma_length = cur_len_dma;
1267 if ((((cur_start_dma +cur_len_dma - 1)>> PAGE_SHIFT) - (dma_addr >> PAGE_SHIFT) + 1) != numTces)
1269 PPCDBG(PPCDBG_TCE, "fill_scatterlist_sg: numTces %ld, used tces %d\n",
1271 (unsigned)(((cur_start_dma + cur_len_dma - 1) >> PAGE_SHIFT) - (dma_addr >> PAGE_SHIFT) + 1));
1275 return num_dma_ents;
1278 /* Call the hypervisor to create the TCE entries.
1279 * return the number of TCEs created
1281 static dma_addr_t create_tces_sg( struct TceTable *tbl, struct scatterlist *sg,
1282 int nents, unsigned numTces, int direction )
1284 unsigned order, i, j;
1285 unsigned long startPage, endPage, prevEndPage, numPages, uaddr;
1286 long tcenum, starttcenum;
1291 order = get_order( numTces << PAGE_SHIFT );
1292 /* Client asked for way to much space. This is checked later anyway */
1293 /* It is easier to debug here for the drivers than in the tce tables.*/
1294 if(order >= NUM_TCE_LEVELS) {
1295 printk("PCI_DMA: create_tces_sg size to large: 0x%x \n",(numTces << PAGE_SHIFT));
1299 /* allocate a block of tces */
1300 tcenum = alloc_tce_range( tbl, order );
1301 if ( tcenum != -1 ) {
1302 tcenum += tbl->startOffset;
1303 starttcenum = tcenum;
1304 dmaAddr = tcenum << PAGE_SHIFT;
1306 for (j=0; j<nents; ++j) {
1307 startPage = (unsigned long)sg->address >> PAGE_SHIFT;
1308 endPage = ((unsigned long)sg->address + sg->length - 1) >> PAGE_SHIFT;
1309 numPages = endPage - startPage + 1;
1311 uaddr = (unsigned long)sg->address;
1313 /* If the previous entry ended in the same page that
1314 * the current page starts then they share that
1315 * tce and we reduce the number of tces we need
1316 * by one. This matches assumptions made in
1317 * num_tces_sg and fill_scatterlist_sg
1319 if ( startPage == prevEndPage ) {
1324 for (i=0; i<numPages; ++i) {
1325 ppc_md.tce_build(tbl, tcenum, uaddr, direction);
1330 prevEndPage = endPage;
1333 /* Make sure the update is visible to hardware.
1334 sync required to synchronize the update to
1335 the TCE table with the MMIO that will send
1336 the bus address to the IOA */
1337 __asm__ __volatile__ ("sync" : : : "memory");
1339 if ((tcenum - starttcenum) != numTces)
1340 PPCDBG(PPCDBG_TCE, "create_tces_sg: numTces %d, tces used %d\n",
1341 numTces, (unsigned)(tcenum - starttcenum));
1348 int pci_map_sg( struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction )
1350 struct TceTable * tbl;
1353 dma_addr_t dma_handle;
1355 PPCDBG(PPCDBG_TCE, "pci_map_sg:\n");
1356 PPCDBG(PPCDBG_TCE, "\thwdev = 0x%16.16lx, sg = 0x%16.16lx, direction = 0x%16.16lx, nents = 0x%16.16lx\n", hwdev, sg, direction, nents);
1357 /* Fast path for a single entry scatterlist */
1359 sg->dma_address = pci_map_single( hwdev, sg->address,
1360 sg->length, direction );
1361 sg->dma_length = sg->length;
1365 if ( direction == PCI_DMA_NONE )
1368 tbl = get_tce_table(hwdev);
1371 /* Compute the number of tces required */
1372 numTces = num_tces_sg( sg, nents );
1373 /* Create the tces and get the dma address */
1374 dma_handle = create_tces_sg( tbl, sg, nents, numTces, direction );
1376 /* Fill in the dma scatterlist */
1377 num_dma = fill_scatterlist_sg( sg, nents, dma_handle, numTces );
1383 void pci_unmap_sg( struct pci_dev *hwdev, struct scatterlist *sg, int nelms, int direction )
1385 struct TceTable * tbl;
1386 unsigned order, numTces, i;
1387 dma_addr_t dma_end_page, dma_start_page;
1389 PPCDBG(PPCDBG_TCE, "pci_unmap_sg:\n");
1390 PPCDBG(PPCDBG_TCE, "\thwdev = 0x%16.16lx, sg = 0x%16.16lx, direction = 0x%16.16lx, nelms = 0x%16.16lx\n", hwdev, sg, direction, nelms);
1392 if ( direction == PCI_DMA_NONE || nelms == 0 )
1395 dma_start_page = sg->dma_address & PAGE_MASK;
1397 for ( i=nelms; i>0; --i ) {
1399 if ( sg[k].dma_length ) {
1400 dma_end_page = ( sg[k].dma_address +
1401 sg[k].dma_length - 1 ) & PAGE_MASK;
1406 numTces = ((dma_end_page - dma_start_page ) >> PAGE_SHIFT) + 1;
1407 order = get_order( numTces << PAGE_SHIFT );
1409 /* Client asked for way to much space. This is checked later anyway */
1410 /* It is easier to debug here for the drivers than in the tce tables.*/
1411 if(order >= NUM_TCE_LEVELS) {
1412 printk("PCI_DMA: dma_start_page:0x%x dma_end_page:0x%x\n",dma_start_page,dma_end_page);
1413 printk("PCI_DMA: pci_unmap_sg size to large: 0x%x \n",(numTces << PAGE_SHIFT));
1417 tbl = get_tce_table(hwdev);
1420 tce_free( tbl, dma_start_page, order, numTces );
1425 * phb_tce_table_init
1427 * Function: Display TCE config registers. Could be easily changed
1428 * to initialize the hardware to use TCEs.
1430 unsigned long phb_tce_table_init(struct pci_controller *phb) {
1431 unsigned int r, cfg_rw, i;
1435 PPCDBG(PPCDBG_TCE, "phb_tce_table_init: start.\n");
1437 node = ((struct device_node *)(phb->arch_data))->node;
1439 PPCDBG(PPCDBG_TCEINIT, "\tphb = 0x%lx\n", phb);
1440 PPCDBG(PPCDBG_TCEINIT, "\tphb->type = 0x%lx\n", phb->type);
1441 PPCDBG(PPCDBG_TCEINIT, "\tphb->phb_regs = 0x%lx\n", phb->phb_regs);
1442 PPCDBG(PPCDBG_TCEINIT, "\tphb->chip_regs = 0x%lx\n", phb->chip_regs);
1443 PPCDBG(PPCDBG_TCEINIT, "\tphb: node = 0x%lx\n", node);
1444 PPCDBG(PPCDBG_TCEINIT, "\tphb->arch_data = 0x%lx\n", phb->arch_data);
1447 while(of_tce_table[i].node) {
1448 if(of_tce_table[i].node == node) {
1449 if(phb->type == phb_type_python) {
1450 r = *(((unsigned int *)phb->phb_regs) + (0xf10>>2));
1451 PPCDBG(PPCDBG_TCEINIT, "\tTAR(low) = 0x%x\n", r);
1452 r = *(((unsigned int *)phb->phb_regs) + (0xf00>>2));
1453 PPCDBG(PPCDBG_TCEINIT, "\tTAR(high) = 0x%x\n", r);
1454 r = *(((unsigned int *)phb->phb_regs) + (0xfd0>>2));
1455 PPCDBG(PPCDBG_TCEINIT, "\tPHB cfg(rw) = 0x%x\n", r);
1457 } else if(phb->type == phb_type_speedwagon) {
1458 r64 = *(((unsigned long *)phb->chip_regs) +
1460 PPCDBG(PPCDBG_TCEINIT, "\tNCFG = 0x%lx\n", r64);
1461 r64 = *(((unsigned long *)phb->chip_regs) +
1463 PPCDBG(PPCDBG_TCEINIT, "\tTAR0 = 0x%lx\n", r64);
1464 r64 = *(((unsigned long *)phb->chip_regs) +
1466 PPCDBG(PPCDBG_TCEINIT, "\tTAR1 = 0x%lx\n", r64);
1467 r64 = *(((unsigned long *)phb->chip_regs) +
1469 PPCDBG(PPCDBG_TCEINIT, "\tTAR2 = 0x%lx\n", r64);
1470 r64 = *(((unsigned long *)phb->chip_regs) +
1472 PPCDBG(PPCDBG_TCEINIT, "\tTAR3 = 0x%lx\n", r64);
1473 cfg_rw = *(((unsigned int *)phb->chip_regs) +
1475 (((phb->local_number)+8)<<12))>>2));
1476 PPCDBG(PPCDBG_TCEINIT, "\tcfg_rw = 0x%x\n", cfg_rw);
1482 PPCDBG(PPCDBG_TCEINIT, "phb_tce_table_init: done\n");
1487 /* These are called very early. */
1488 void tce_init_pSeries(void)
1490 ppc_md.tce_build = tce_build_pSeries;
1491 ppc_md.tce_free_one = tce_free_one_pSeries;
1494 void tce_init_iSeries(void)
1496 ppc_md.tce_build = tce_build_iSeries;
1497 ppc_md.tce_free_one = tce_free_one_iSeries;