2 * arch/ppc64/kernel/ppc_asm.h
4 * Definitions used by various bits of low-level assembly code on PowerPC.
6 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
14 #include <linux/config.h>
16 #include <asm/ppc_asm.tmpl>
20 * Macros for storing registers into and loading registers from
23 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
24 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
25 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
26 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
27 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
28 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
29 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
30 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
31 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
32 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
34 #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
35 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
36 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
37 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
38 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
39 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
40 #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
41 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
42 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
43 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
44 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
45 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
47 #define CHECKANYINT(ra,rb) \
48 mfspr rb,SPRG3; /* Get Paca address */\
49 ld ra,PACALPPACA+LPPACAANYINT(rb); /* Get pending interrupt flags */\
52 /* Macros to adjust thread priority for Iseries hardware multithreading */
53 #define HMT_LOW or 1,1,1
54 #define HMT_MEDIUM or 2,2,2
55 #define HMT_HIGH or 3,3,3
57 /* Insert the high 32 bits of the MSR into what will be the new
58 MSR (via SRR1 and rfid) This preserves the MSR.SF and MSR.ISF
61 #define FIX_SRR1(ra, rb) \
66 #define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
69 * LOADADDR( rn, name )
70 * loads the address of 'name' into 'rn'
72 * LOADBASE( rn, name )
73 * loads the address (less the low 16 bits) of 'name' into 'rn'
74 * suitable for base+disp addressing
76 #define LOADADDR(rn,name) \
77 lis rn,name##@highest; \
78 ori rn,rn,name##@higher; \
80 oris rn,rn,name##@h; \
83 #define LOADBASE(rn,name) \
84 lis rn,name@highest; \
85 ori rn,rn,name@higher; \
90 #define SET_REG_TO_CONST(reg, value) \
91 lis reg,(((value)>>48)&0xFFFF); \
92 ori reg,reg,(((value)>>32)&0xFFFF); \
93 rldicr reg,reg,32,31; \
94 oris reg,reg,(((value)>>16)&0xFFFF); \
95 ori reg,reg,((value)&0xFFFF);
97 #define SET_REG_TO_LABEL(reg, label) \
98 lis reg,(label)@highest; \
99 ori reg,reg,(label)@higher; \
100 rldicr reg,reg,32,31; \
101 oris reg,reg,(label)@h; \
102 ori reg,reg,(label)@l;
105 /* PPPBBB - DRENG If KERNELBASE is always 0xC0...,
106 * Then we can easily do this with one asm insn. -Peter
108 #define tophys(rd,rs) \
109 lis rd,((KERNELBASE>>48)&0xFFFF); \
110 rldicr rd,rd,32,31; \
113 #define tovirt(rd,rs) \
114 lis rd,((KERNELBASE>>48)&0xFFFF); \
115 rldicr rd,rd,32,31; \