1 /* $Id: math.c,v 1.11 1999/12/20 05:02:25 davem Exp $
2 * arch/sparc64/math-emu/math.c
4 * Copyright (C) 1997,1999 Jakub Jelinek (jj@ultra.linux.cz)
5 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
7 * Emulation routines originate from soft-fp package, which is part
8 * of glibc and has appropriate copyrights in it.
11 #include <linux/types.h>
12 #include <linux/sched.h>
14 #include <asm/fpumacro.h>
15 #include <asm/ptrace.h>
16 #include <asm/uaccess.h>
19 #include <math-emu/soft-fp.h>
20 #include <math-emu/single.h>
21 #include <math-emu/double.h>
22 #include <math-emu/quad.h>
42 /* SUBNORMAL - ftt == 2 */
60 #define FXTOS 0x084 /* Only Ultra-III generates this. */
61 #define FXTOD 0x088 /* Only Ultra-III generates this. */
62 #if 0 /* Optimized inline in sparc64/kernel/entry.S */
63 #define FITOS 0x0c4 /* Only Ultra-III generates this. */
65 #define FITOD 0x0c8 /* Only Ultra-III generates this. */
82 #define FSR_TEM_SHIFT 23UL
83 #define FSR_TEM_MASK (0x1fUL << FSR_TEM_SHIFT)
84 #define FSR_AEXC_SHIFT 5UL
85 #define FSR_AEXC_MASK (0x1fUL << FSR_AEXC_SHIFT)
86 #define FSR_CEXC_SHIFT 0UL
87 #define FSR_CEXC_MASK (0x1fUL << FSR_CEXC_SHIFT)
89 /* All routines returning an exception to raise should detect
90 * such exceptions _before_ rounding to be consistant with
91 * the behavior of the hardware in the implemented cases
92 * (and thus with the recommendations in the V9 architecture
95 * We return 0 if a SIGFPE should be sent, 1 otherwise.
97 static inline int record_exception(struct pt_regs *regs, int eflag)
99 u64 fsr = current->thread.xfsr[0];
102 /* Determine if this exception would have generated a trap. */
103 would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL;
105 /* If trapping, we only want to signal one bit. */
106 if(would_trap != 0) {
107 eflag &= ((fsr & FSR_TEM_MASK) >> FSR_TEM_SHIFT);
108 if((eflag & (eflag - 1)) != 0) {
109 if(eflag & FP_EX_INVALID)
110 eflag = FP_EX_INVALID;
111 else if(eflag & FP_EX_OVERFLOW)
112 eflag = FP_EX_OVERFLOW;
113 else if(eflag & FP_EX_UNDERFLOW)
114 eflag = FP_EX_UNDERFLOW;
115 else if(eflag & FP_EX_DIVZERO)
116 eflag = FP_EX_DIVZERO;
117 else if(eflag & FP_EX_INEXACT)
118 eflag = FP_EX_INEXACT;
122 /* Set CEXC, here is the rule:
124 * In general all FPU ops will set one and only one
125 * bit in the CEXC field, this is always the case
126 * when the IEEE exception trap is enabled in TEM.
128 fsr &= ~(FSR_CEXC_MASK);
129 fsr |= ((long)eflag << FSR_CEXC_SHIFT);
131 /* Set the AEXC field, rule is:
133 * If a trap would not be generated, the
134 * CEXC just generated is OR'd into the
135 * existing value of AEXC.
138 fsr |= ((long)eflag << FSR_AEXC_SHIFT);
140 /* If trapping, indicate fault trap type IEEE. */
144 current->thread.xfsr[0] = fsr;
146 /* If we will not trap, advance the program counter over
147 * the instruction being handled.
149 if(would_trap == 0) {
150 regs->tpc = regs->tnpc;
154 return (would_trap ? 0 : 1);
163 int do_mathemu(struct pt_regs *regs, struct fpustate *f)
165 unsigned long pc = regs->tpc;
166 unsigned long tstate = regs->tstate;
169 /* ftt tells which ftt it may happen in, r is rd, b is rs2 and a is rs1. The *u arg tells
170 whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack)
171 non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */
172 #define TYPE(ftt, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru << 8) | (r << 6) | (ftt << 9)
174 static u64 zero[2] = { 0L, 0L };
177 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
178 FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
179 FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
183 if(tstate & TSTATE_PRIV)
184 die_if_kernel("unfinished/unimplemented FPop from kernel", regs);
185 if(current->thread.flags & SPARC_FLAG_32BIT)
187 if (get_user(insn, (u32 *)pc) != -EFAULT) {
188 if ((insn & 0xc1f80000) == 0x81a00000) /* FPOP1 */ {
189 switch ((insn >> 5) & 0x1ff) {
190 /* QUAD - ftt == 3 */
193 case FABSQ: TYPE(3,3,0,3,0,0,0); break;
194 case FSQRTQ: TYPE(3,3,1,3,1,0,0); break;
198 case FDIVQ: TYPE(3,3,1,3,1,3,1); break;
199 case FDMULQ: TYPE(3,3,1,2,1,2,1); break;
200 case FQTOX: TYPE(3,2,0,3,1,0,0); break;
201 case FXTOQ: TYPE(3,3,1,2,0,0,0); break;
202 case FQTOS: TYPE(3,1,1,3,1,0,0); break;
203 case FQTOD: TYPE(3,2,1,3,1,0,0); break;
204 case FITOQ: TYPE(3,3,1,1,0,0,0); break;
205 case FSTOQ: TYPE(3,3,1,1,1,0,0); break;
206 case FDTOQ: TYPE(3,3,1,2,1,0,0); break;
207 case FQTOI: TYPE(3,1,0,3,1,0,0); break;
208 /* SUBNORMAL - ftt == 2 */
209 case FSQRTS: TYPE(2,1,1,1,1,0,0); break;
210 case FSQRTD: TYPE(2,2,1,2,1,0,0); break;
214 case FDIVD: TYPE(2,2,1,2,1,2,1); break;
218 case FDIVS: TYPE(2,1,1,1,1,1,1); break;
219 case FSMULD: TYPE(2,2,1,1,1,1,1); break;
220 case FSTOX: TYPE(2,2,0,1,1,0,0); break;
221 case FDTOX: TYPE(2,2,0,2,1,0,0); break;
222 case FDTOS: TYPE(2,1,1,2,1,0,0); break;
223 case FSTOD: TYPE(2,2,1,1,1,0,0); break;
224 case FSTOI: TYPE(2,1,0,1,1,0,0); break;
225 case FDTOI: TYPE(2,1,0,2,1,0,0); break;
227 /* Only Ultra-III generates these */
228 case FXTOS: TYPE(2,1,1,2,0,0,0); break;
229 case FXTOD: TYPE(2,2,1,2,0,0,0); break;
230 #if 0 /* Optimized inline in sparc64/kernel/entry.S */
231 case FITOS: TYPE(2,1,1,1,0,0,0); break;
233 case FITOD: TYPE(2,2,1,1,0,0,0); break;
236 else if ((insn & 0xc1f80000) == 0x81a80000) /* FPOP2 */ {
238 switch ((insn >> 5) & 0x1ff) {
239 case FCMPQ: TYPE(3,0,0,3,1,3,1); break;
240 case FCMPEQ: TYPE(3,0,0,3,1,3,1); break;
241 /* Now the conditional fmovq support */
246 /* fmovq %fccX, %fY, %fZ */
247 if (!((insn >> 11) & 3))
248 XR = current->thread.xfsr[0] >> 10;
250 XR = current->thread.xfsr[0] >> (30 + ((insn >> 10) & 0x6));
253 switch ((insn >> 14) & 0x7) {
254 /* case 0: IR = 0; break; */ /* Never */
255 case 1: if (XR) IR = 1; break; /* Not Equal */
256 case 2: if (XR == 1 || XR == 2) IR = 1; break; /* Less or Greater */
257 case 3: if (XR & 1) IR = 1; break; /* Unordered or Less */
258 case 4: if (XR == 1) IR = 1; break; /* Less */
259 case 5: if (XR & 2) IR = 1; break; /* Unordered or Greater */
260 case 6: if (XR == 2) IR = 1; break; /* Greater */
261 case 7: if (XR == 3) IR = 1; break; /* Unordered */
263 if ((insn >> 14) & 8)
268 /* fmovq %[ix]cc, %fY, %fZ */
269 XR = regs->tstate >> 32;
270 if ((insn >> 5) & 0x80)
274 freg = ((XR >> 2) ^ XR) & 2;
275 switch ((insn >> 14) & 0x7) {
276 /* case 0: IR = 0; break; */ /* Never */
277 case 1: if (XR & 4) IR = 1; break; /* Equal */
278 case 2: if ((XR & 4) || freg) IR = 1; break; /* Less or Equal */
279 case 3: if (freg) IR = 1; break; /* Less */
280 case 4: if (XR & 5) IR = 1; break; /* Less or Equal Unsigned */
281 case 5: if (XR & 1) IR = 1; break; /* Carry Set */
282 case 6: if (XR & 8) IR = 1; break; /* Negative */
283 case 7: if (XR & 2) IR = 1; break; /* Overflow Set */
285 if ((insn >> 14) & 8)
294 freg = (insn >> 14) & 0x1f;
298 XR = regs->u_regs[freg];
299 else if (current->thread.flags & SPARC_FLAG_32BIT) {
300 struct reg_window32 *win32;
302 win32 = (struct reg_window32 *)((unsigned long)((u32)regs->u_regs[UREG_FP]));
303 get_user(XR, &win32->locals[freg - 16]);
305 struct reg_window *win;
307 win = (struct reg_window *)(regs->u_regs[UREG_FP] + STACK_BIAS);
308 get_user(XR, &win->locals[freg - 16]);
311 switch ((insn >> 10) & 3) {
312 case 1: if (!XR) IR = 1; break; /* Register Zero */
313 case 2: if (XR <= 0) IR = 1; break; /* Register Less Than or Equal to Zero */
314 case 3: if (XR < 0) IR = 1; break; /* Register Less Than Zero */
316 if ((insn >> 10) & 4)
321 /* The fmov test was false. Do a nop instead */
322 current->thread.xfsr[0] &= ~(FSR_CEXC_MASK);
323 regs->tpc = regs->tnpc;
326 } else if (IR == 1) {
327 /* Change the instruction into plain fmovq */
328 insn = (insn & 0x3e00001f) | 0x81a00060;
334 argp rs1 = NULL, rs2 = NULL, rd = NULL;
336 freg = (current->thread.xfsr[0] >> 14) & 0xf;
337 if (freg != (type >> 9))
339 current->thread.xfsr[0] &= ~0x1c000;
340 freg = ((insn >> 14) & 0x1f);
341 switch (type & 0x3) {
342 case 3: if (freg & 2) {
343 current->thread.xfsr[0] |= (6 << 14) /* invalid_fp_register */;
346 case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
347 case 1: rs1 = (argp)&f->regs[freg];
348 flags = (freg < 32) ? FPRS_DL : FPRS_DU;
349 if (!(current->thread.fpsaved[0] & flags))
353 switch (type & 0x7) {
354 case 7: FP_UNPACK_QP (QA, rs1); break;
355 case 6: FP_UNPACK_DP (DA, rs1); break;
356 case 5: FP_UNPACK_SP (SA, rs1); break;
358 freg = (insn & 0x1f);
359 switch ((type >> 3) & 0x3) {
360 case 3: if (freg & 2) {
361 current->thread.xfsr[0] |= (6 << 14) /* invalid_fp_register */;
364 case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
365 case 1: rs2 = (argp)&f->regs[freg];
366 flags = (freg < 32) ? FPRS_DL : FPRS_DU;
367 if (!(current->thread.fpsaved[0] & flags))
371 switch ((type >> 3) & 0x7) {
372 case 7: FP_UNPACK_QP (QB, rs2); break;
373 case 6: FP_UNPACK_DP (DB, rs2); break;
374 case 5: FP_UNPACK_SP (SB, rs2); break;
376 freg = ((insn >> 25) & 0x1f);
377 switch ((type >> 6) & 0x3) {
378 case 3: if (freg & 2) {
379 current->thread.xfsr[0] |= (6 << 14) /* invalid_fp_register */;
382 case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
383 case 1: rd = (argp)&f->regs[freg];
384 flags = (freg < 32) ? FPRS_DL : FPRS_DU;
385 if (!(current->thread.fpsaved[0] & FPRS_FEF)) {
386 current->thread.fpsaved[0] = FPRS_FEF;
387 current->thread.gsr[0] = 0;
389 if (!(current->thread.fpsaved[0] & flags)) {
391 memset(f->regs, 0, 32*sizeof(u32));
393 memset(f->regs+32, 0, 32*sizeof(u32));
395 current->thread.fpsaved[0] |= flags;
398 switch ((insn >> 5) & 0x1ff) {
400 case FADDS: FP_ADD_S (SR, SA, SB); break;
401 case FADDD: FP_ADD_D (DR, DA, DB); break;
402 case FADDQ: FP_ADD_Q (QR, QA, QB); break;
404 case FSUBS: FP_SUB_S (SR, SA, SB); break;
405 case FSUBD: FP_SUB_D (DR, DA, DB); break;
406 case FSUBQ: FP_SUB_Q (QR, QA, QB); break;
408 case FMULS: FP_MUL_S (SR, SA, SB); break;
409 case FSMULD: FP_CONV (D, S, 1, 1, DA, SA);
410 FP_CONV (D, S, 1, 1, DB, SB);
411 case FMULD: FP_MUL_D (DR, DA, DB); break;
412 case FDMULQ: FP_CONV (Q, D, 2, 1, QA, DA);
413 FP_CONV (Q, D, 2, 1, QB, DB);
414 case FMULQ: FP_MUL_Q (QR, QA, QB); break;
416 case FDIVS: FP_DIV_S (SR, SA, SB); break;
417 case FDIVD: FP_DIV_D (DR, DA, DB); break;
418 case FDIVQ: FP_DIV_Q (QR, QA, QB); break;
420 case FSQRTS: FP_SQRT_S (SR, SB); break;
421 case FSQRTD: FP_SQRT_D (DR, DB); break;
422 case FSQRTQ: FP_SQRT_Q (QR, QB); break;
424 case FMOVQ: rd->q[0] = rs2->q[0]; rd->q[1] = rs2->q[1]; break;
425 case FABSQ: rd->q[0] = rs2->q[0] & 0x7fffffffffffffffUL; rd->q[1] = rs2->q[1]; break;
426 case FNEGQ: rd->q[0] = rs2->q[0] ^ 0x8000000000000000UL; rd->q[1] = rs2->q[1]; break;
428 case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break;
429 case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break;
430 case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break;
431 case FSTOX: FP_TO_INT_S (XR, SB, 64, 1); break;
432 case FDTOX: FP_TO_INT_D (XR, DB, 64, 1); break;
433 case FQTOX: FP_TO_INT_Q (XR, QB, 64, 1); break;
435 case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break;
436 case FXTOQ: XR = rs2->d; FP_FROM_INT_Q (QR, XR, 64, long); break;
437 /* Only Ultra-III generates these */
438 case FXTOS: XR = rs2->d; FP_FROM_INT_S (SR, XR, 64, long); break;
439 case FXTOD: XR = rs2->d; FP_FROM_INT_D (DR, XR, 64, long); break;
440 #if 0 /* Optimized inline in sparc64/kernel/entry.S */
441 case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break;
443 case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break;
445 case FSTOD: FP_CONV (D, S, 1, 1, DR, SB); break;
446 case FSTOQ: FP_CONV (Q, S, 2, 1, QR, SB); break;
447 case FDTOQ: FP_CONV (Q, D, 2, 1, QR, DB); break;
448 case FDTOS: FP_CONV (S, D, 1, 1, SR, DB); break;
449 case FQTOS: FP_CONV (S, Q, 1, 2, SR, QB); break;
450 case FQTOD: FP_CONV (D, Q, 1, 2, DR, QB); break;
454 FP_CMP_Q(XR, QB, QA, 3);
456 (((insn >> 5) & 0x1ff) == FCMPEQ ||
459 FP_SET_EXCEPTION (FP_EX_INVALID);
461 if (!FP_INHIBIT_RESULTS) {
462 switch ((type >> 6) & 0x7) {
463 case 0: xfsr = current->thread.xfsr[0];
464 if (XR == -1) XR = 2;
467 case 0: xfsr &= ~0xc00; xfsr |= (XR << 10); break;
468 case 1: xfsr &= ~0x300000000UL; xfsr |= (XR << 32); break;
469 case 2: xfsr &= ~0xc00000000UL; xfsr |= (XR << 34); break;
470 case 3: xfsr &= ~0x3000000000UL; xfsr |= (XR << 36); break;
472 current->thread.xfsr[0] = xfsr;
474 case 1: rd->s = IR; break;
475 case 2: rd->d = XR; break;
476 case 5: FP_PACK_SP (rd, SR); break;
477 case 6: FP_PACK_DP (rd, DR); break;
478 case 7: FP_PACK_QP (rd, QR); break;
483 return record_exception(regs, _fex);
485 /* Success and no exceptions detected. */
486 current->thread.xfsr[0] &= ~(FSR_CEXC_MASK);
487 regs->tpc = regs->tnpc;