2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
23 #include <linux/irq.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/config.h>
29 #include <linux/smp_lock.h>
30 #include <linux/mc146818rtc.h>
36 #undef APIC_LOCKUP_DEBUG
38 #define APIC_LOCKUP_DEBUG
40 static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED;
43 * # of IRQ routing registers
45 int nr_ioapic_registers[MAX_IO_APICS];
48 * Rough estimation of how many shared IRQs there are, can
51 #define MAX_PLUS_SHARED_IRQS NR_IRQS
52 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
55 * This is performance-critical, we want to do it O(1)
57 * the indexing order of this array favors 1:1 mappings
58 * between pins and IRQs.
61 static struct irq_pin_list {
63 } irq_2_pin[PIN_MAP_SIZE];
66 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
67 * shared ISA-space IRQs, so we have to support them. We are super
68 * fast in the common case, and fast for shared ISA-space IRQs.
70 static void __init add_pin_to_irq(unsigned int irq, int apic, int pin)
72 static int first_free_entry = NR_IRQS;
73 struct irq_pin_list *entry = irq_2_pin + irq;
76 entry = irq_2_pin + entry->next;
78 if (entry->pin != -1) {
79 entry->next = first_free_entry;
80 entry = irq_2_pin + entry->next;
81 if (++first_free_entry >= PIN_MAP_SIZE)
82 panic("io_apic.c: whoops");
89 * Reroute an IRQ to a different pin.
91 static void __init replace_pin_at_irq(unsigned int irq,
92 int oldapic, int oldpin,
93 int newapic, int newpin)
95 struct irq_pin_list *entry = irq_2_pin + irq;
98 if (entry->apic == oldapic && entry->pin == oldpin) {
99 entry->apic = newapic;
104 entry = irq_2_pin + entry->next;
108 #define __DO_ACTION(R, ACTION, FINAL) \
112 struct irq_pin_list *entry = irq_2_pin + irq; \
119 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
121 io_apic_modify(entry->apic, reg); \
124 entry = irq_2_pin + entry->next; \
129 #define DO_ACTION(name,R,ACTION, FINAL) \
131 static void name##_IO_APIC_irq (unsigned int irq) \
132 __DO_ACTION(R, ACTION, FINAL)
134 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
136 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
138 DO_ACTION( __mask_and_edge, 0, = (reg & 0xffff7fff) | 0x00010000, )
139 /* mask = 1, trigger = 0 */
140 DO_ACTION( __unmask_and_level, 0, = (reg & 0xfffeffff) | 0x00008000, )
141 /* mask = 0, trigger = 1 */
143 static void mask_IO_APIC_irq (unsigned int irq)
147 spin_lock_irqsave(&ioapic_lock, flags);
148 __mask_IO_APIC_irq(irq);
149 spin_unlock_irqrestore(&ioapic_lock, flags);
152 static void unmask_IO_APIC_irq (unsigned int irq)
156 spin_lock_irqsave(&ioapic_lock, flags);
157 __unmask_IO_APIC_irq(irq);
158 spin_unlock_irqrestore(&ioapic_lock, flags);
161 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
163 struct IO_APIC_route_entry entry;
167 * Disable it in the IO-APIC irq-routing table:
169 memset(&entry, 0, sizeof(entry));
171 spin_lock_irqsave(&ioapic_lock, flags);
172 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
173 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
174 spin_unlock_irqrestore(&ioapic_lock, flags);
177 static void clear_IO_APIC (void)
181 for (apic = 0; apic < nr_ioapics; apic++)
182 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
183 clear_IO_APIC_pin(apic, pin);
187 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
188 * specific CPU-side IRQs.
192 int pirq_entries [MAX_PIRQS];
194 int skip_ioapic_setup;
196 static int __init noioapic_setup(char *str)
198 skip_ioapic_setup = 1;
202 __setup("noapic", noioapic_setup);
204 static int __init ioapic_setup(char *str)
206 skip_ioapic_setup = 0;
210 __setup("apic", ioapic_setup);
213 static int __init ioapic_pirq_setup(char *str)
216 int ints[MAX_PIRQS+1];
218 get_options(str, ARRAY_SIZE(ints), ints);
220 for (i = 0; i < MAX_PIRQS; i++)
221 pirq_entries[i] = -1;
224 printk(KERN_INFO "PIRQ redirection, working around broken MP-BIOS.\n");
226 if (ints[0] < MAX_PIRQS)
229 for (i = 0; i < max; i++) {
230 printk(KERN_DEBUG "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
232 * PIRQs are mapped upside down, usually.
234 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
239 __setup("pirq=", ioapic_pirq_setup);
242 * Find the IRQ entry number of a certain pin.
244 static int __init find_irq_entry(int apic, int pin, int type)
248 for (i = 0; i < mp_irq_entries; i++)
249 if (mp_irqs[i].mpc_irqtype == type &&
250 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
251 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
252 mp_irqs[i].mpc_dstirq == pin)
259 * Find the pin to which IRQ[irq] (ISA) is connected
261 static int __init find_isa_irq_pin(int irq, int type)
265 for (i = 0; i < mp_irq_entries; i++) {
266 int lbus = mp_irqs[i].mpc_srcbus;
268 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
269 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
270 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
271 (mp_irqs[i].mpc_irqtype == type) &&
272 (mp_irqs[i].mpc_srcbusirq == irq))
274 return mp_irqs[i].mpc_dstirq;
280 * Find a specific PCI IRQ entry.
281 * Not an __init, possibly needed by modules
283 static int pin_2_irq(int idx, int apic, int pin);
285 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
287 int apic, i, best_guess = -1;
289 Dprintk("querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
291 if (mp_bus_id_to_pci_bus[bus] == -1) {
292 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
295 for (i = 0; i < mp_irq_entries; i++) {
296 int lbus = mp_irqs[i].mpc_srcbus;
298 for (apic = 0; apic < nr_ioapics; apic++)
299 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
300 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
303 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
304 !mp_irqs[i].mpc_irqtype &&
306 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
307 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
309 if (!(apic || IO_APIC_IRQ(irq)))
312 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
315 * Use the first all-but-pin matching entry as a
316 * best-guess fuzzy result for broken mptables.
326 * EISA Edge/Level control register, ELCR
328 static int __init EISA_ELCR(unsigned int irq)
331 unsigned int port = 0x4d0 + (irq >> 3);
332 return (inb(port) >> (irq & 7)) & 1;
334 printk(KERN_INFO "Broken MPtable reports ISA irq %d\n", irq);
338 /* EISA interrupts are always polarity zero and can be edge or level
339 * trigger depending on the ELCR value. If an interrupt is listed as
340 * EISA conforming in the MP table, that means its trigger type must
341 * be read in from the ELCR */
343 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
344 #define default_EISA_polarity(idx) (0)
346 /* ISA interrupts are always polarity zero edge triggered,
347 * when listed as conforming in the MP table. */
349 #define default_ISA_trigger(idx) (0)
350 #define default_ISA_polarity(idx) (0)
352 /* PCI interrupts are always polarity one level triggered,
353 * when listed as conforming in the MP table. */
355 #define default_PCI_trigger(idx) (1)
356 #define default_PCI_polarity(idx) (1)
358 /* MCA interrupts are always polarity zero level triggered,
359 * when listed as conforming in the MP table. */
361 #define default_MCA_trigger(idx) (1)
362 #define default_MCA_polarity(idx) (0)
364 static int __init MPBIOS_polarity(int idx)
366 int bus = mp_irqs[idx].mpc_srcbus;
370 * Determine IRQ line polarity (high active or low active):
372 switch (mp_irqs[idx].mpc_irqflag & 3)
374 case 0: /* conforms, ie. bus-type dependent polarity */
376 switch (mp_bus_id_to_type[bus])
378 case MP_BUS_ISA: /* ISA pin */
380 polarity = default_ISA_polarity(idx);
383 case MP_BUS_EISA: /* EISA pin */
385 polarity = default_EISA_polarity(idx);
388 case MP_BUS_PCI: /* PCI pin */
390 polarity = default_PCI_polarity(idx);
393 case MP_BUS_MCA: /* MCA pin */
395 polarity = default_MCA_polarity(idx);
400 printk(KERN_WARNING "broken BIOS!!\n");
407 case 1: /* high active */
412 case 2: /* reserved */
414 printk(KERN_WARNING "broken BIOS!!\n");
418 case 3: /* low active */
423 default: /* invalid */
425 printk(KERN_WARNING "broken BIOS!!\n");
433 static int __init MPBIOS_trigger(int idx)
435 int bus = mp_irqs[idx].mpc_srcbus;
439 * Determine IRQ trigger mode (edge or level sensitive):
441 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
443 case 0: /* conforms, ie. bus-type dependent */
445 switch (mp_bus_id_to_type[bus])
447 case MP_BUS_ISA: /* ISA pin */
449 trigger = default_ISA_trigger(idx);
452 case MP_BUS_EISA: /* EISA pin */
454 trigger = default_EISA_trigger(idx);
457 case MP_BUS_PCI: /* PCI pin */
459 trigger = default_PCI_trigger(idx);
462 case MP_BUS_MCA: /* MCA pin */
464 trigger = default_MCA_trigger(idx);
469 printk(KERN_WARNING "broken BIOS!!\n");
481 case 2: /* reserved */
483 printk(KERN_WARNING "broken BIOS!!\n");
492 default: /* invalid */
494 printk(KERN_WARNING "broken BIOS!!\n");
502 static inline int irq_polarity(int idx)
504 return MPBIOS_polarity(idx);
507 static inline int irq_trigger(int idx)
509 return MPBIOS_trigger(idx);
512 static int pin_2_irq(int idx, int apic, int pin)
515 int bus = mp_irqs[idx].mpc_srcbus;
518 * Debugging check, we are in big trouble if this message pops up!
520 if (mp_irqs[idx].mpc_dstirq != pin)
521 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
523 switch (mp_bus_id_to_type[bus])
525 case MP_BUS_ISA: /* ISA pin */
529 irq = mp_irqs[idx].mpc_srcbusirq;
532 case MP_BUS_PCI: /* PCI pin */
535 * PCI IRQs are mapped in order
539 irq += nr_ioapic_registers[i++];
545 printk(KERN_ERR "unknown bus type %d.\n",bus);
552 * PCI IRQ command line redirection. Yes, limits are hardcoded.
554 if ((pin >= 16) && (pin <= 23)) {
555 if (pirq_entries[pin-16] != -1) {
556 if (!pirq_entries[pin-16]) {
557 printk(KERN_DEBUG "disabling PIRQ%d\n", pin-16);
559 irq = pirq_entries[pin-16];
560 printk(KERN_DEBUG "using PIRQ%d -> IRQ %d\n",
568 static inline int IO_APIC_irq_trigger(int irq)
572 for (apic = 0; apic < nr_ioapics; apic++) {
573 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
574 idx = find_irq_entry(apic,pin,mp_INT);
575 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
576 return irq_trigger(idx);
580 * nonexistent IRQs are edge default
585 int irq_vector[NR_IRQS] = { FIRST_DEVICE_VECTOR , 0 };
587 static int __init assign_irq_vector(int irq)
589 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
590 if (IO_APIC_VECTOR(irq) > 0)
591 return IO_APIC_VECTOR(irq);
594 if (current_vector == IA32_SYSCALL_VECTOR)
597 if (current_vector > FIRST_SYSTEM_VECTOR) {
599 current_vector = FIRST_DEVICE_VECTOR + offset;
602 if (current_vector == FIRST_SYSTEM_VECTOR)
603 panic("ran out of interrupt sources!");
605 IO_APIC_VECTOR(irq) = current_vector;
606 return current_vector;
609 extern void (*interrupt[NR_IRQS])(void);
610 static struct hw_interrupt_type ioapic_level_irq_type;
611 static struct hw_interrupt_type ioapic_edge_irq_type;
613 void __init setup_IO_APIC_irqs(void)
615 struct IO_APIC_route_entry entry;
616 int apic, pin, idx, irq, first_notcon = 1, vector;
619 printk(KERN_DEBUG "init IO_APIC IRQs\n");
621 for (apic = 0; apic < nr_ioapics; apic++) {
622 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
625 * add it to the IO-APIC irq-routing table:
627 memset(&entry,0,sizeof(entry));
629 entry.delivery_mode = dest_LowestPrio;
630 entry.dest_mode = INT_DELIVERY_MODE;
631 entry.mask = 0; /* enable IRQ */
632 entry.dest.logical.logical_dest = TARGET_CPUS;
634 idx = find_irq_entry(apic,pin,mp_INT);
637 printk(KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
640 printk(", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
644 entry.trigger = irq_trigger(idx);
645 entry.polarity = irq_polarity(idx);
647 if (irq_trigger(idx)) {
650 entry.dest.logical.logical_dest = TARGET_CPUS;
653 irq = pin_2_irq(idx, apic, pin);
654 add_pin_to_irq(irq, apic, pin);
656 if (!apic && !IO_APIC_IRQ(irq))
659 if (IO_APIC_IRQ(irq)) {
660 vector = assign_irq_vector(irq);
661 entry.vector = vector;
663 if (IO_APIC_irq_trigger(irq))
664 irq_desc[irq].handler = &ioapic_level_irq_type;
666 irq_desc[irq].handler = &ioapic_edge_irq_type;
668 set_intr_gate(vector, interrupt[irq]);
670 if (!apic && (irq < 16))
671 disable_8259A_irq(irq);
673 spin_lock_irqsave(&ioapic_lock, flags);
674 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
675 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
676 spin_unlock_irqrestore(&ioapic_lock, flags);
681 printk(" not connected.\n");
685 * Set up the 8259A-master output pin as broadcast to all
688 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
690 struct IO_APIC_route_entry entry;
693 memset(&entry,0,sizeof(entry));
695 disable_8259A_irq(0);
698 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
701 * We use logical delivery to get the timer IRQ
704 entry.dest_mode = INT_DELIVERY_MODE;
705 entry.mask = 0; /* unmask IRQ now */
706 entry.dest.logical.logical_dest = TARGET_CPUS;
707 entry.delivery_mode = dest_LowestPrio;
710 entry.vector = vector;
713 * The timer IRQ doesnt have to know that behind the
714 * scene we have a 8259A-master in AEOI mode ...
716 irq_desc[0].handler = &ioapic_edge_irq_type;
719 * Add it to the IO-APIC irq-routing table:
721 spin_lock_irqsave(&ioapic_lock, flags);
722 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
723 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
724 spin_unlock_irqrestore(&ioapic_lock, flags);
729 void __init UNEXPECTED_IO_APIC(void)
731 printk(KERN_WARNING " WARNING: unexpected IO-APIC, please mail\n");
732 printk(KERN_WARNING " to linux-smp@vger.kernel.org\n");
735 void __init print_IO_APIC(void)
738 struct IO_APIC_reg_00 reg_00;
739 struct IO_APIC_reg_01 reg_01;
740 struct IO_APIC_reg_02 reg_02;
743 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
744 for (i = 0; i < nr_ioapics; i++)
745 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
746 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
749 * We are a bit conservative about what we expect. We have to
750 * know about every hardware change ASAP.
752 printk(KERN_INFO "testing the IO APIC.......................\n");
754 for (apic = 0; apic < nr_ioapics; apic++) {
756 spin_lock_irqsave(&ioapic_lock, flags);
757 *(int *)®_00 = io_apic_read(apic, 0);
758 *(int *)®_01 = io_apic_read(apic, 1);
759 if (reg_01.version >= 0x10)
760 *(int *)®_02 = io_apic_read(apic, 2);
761 spin_unlock_irqrestore(&ioapic_lock, flags);
764 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
765 printk(KERN_DEBUG ".... register #00: %08X\n", *(int *)®_00);
766 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.ID);
767 if (reg_00.__reserved_1 || reg_00.__reserved_2)
768 UNEXPECTED_IO_APIC();
770 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
771 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.entries);
772 if ( (reg_01.entries != 0x0f) && /* older (Neptune) boards */
773 (reg_01.entries != 0x17) && /* typical ISA+PCI boards */
774 (reg_01.entries != 0x1b) && /* Compaq Proliant boards */
775 (reg_01.entries != 0x1f) && /* dual Xeon boards */
776 (reg_01.entries != 0x22) && /* bigger Xeon boards */
777 (reg_01.entries != 0x2E) &&
778 (reg_01.entries != 0x3F) &&
779 (reg_01.entries != 0x03) /* Golem */
781 UNEXPECTED_IO_APIC();
783 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.PRQ);
784 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.version);
785 if ( (reg_01.version != 0x01) && /* 82489DX IO-APICs */
786 (reg_01.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
787 (reg_01.version != 0x10) && /* oldest IO-APICs */
788 (reg_01.version != 0x11) && /* Pentium/Pro IO-APICs / GOLEM */
789 (reg_01.version != 0x13) && /* Xeon IO-APICs */
790 (reg_01.version != 0x20) /* Intel P64H (82806 AA) */
792 UNEXPECTED_IO_APIC();
793 if (reg_01.__reserved_1 || reg_01.__reserved_2)
794 UNEXPECTED_IO_APIC();
796 if (reg_01.version >= 0x10) {
797 printk(KERN_DEBUG ".... register #02: %08X\n", *(int *)®_02);
798 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.arbitration);
799 if (reg_02.__reserved_1 || reg_02.__reserved_2)
800 UNEXPECTED_IO_APIC();
803 printk(KERN_DEBUG ".... IRQ redirection table:\n");
805 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
806 " Stat Dest Deli Vect: \n");
808 for (i = 0; i <= reg_01.entries; i++) {
809 struct IO_APIC_route_entry entry;
811 spin_lock_irqsave(&ioapic_lock, flags);
812 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
813 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
814 spin_unlock_irqrestore(&ioapic_lock, flags);
816 printk(KERN_DEBUG " %02x %03X %02X ",
818 entry.dest.logical.logical_dest,
819 entry.dest.physical.physical_dest
822 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
827 entry.delivery_status,
834 printk(KERN_DEBUG "IRQ to pin mappings:\n");
835 for (i = 0; i < NR_IRQS; i++) {
836 struct irq_pin_list *entry = irq_2_pin + i;
839 printk(KERN_DEBUG "IRQ%d ", i);
841 printk("-> %d:%d", entry->apic, entry->pin);
844 entry = irq_2_pin + entry->next;
849 printk(KERN_INFO ".................................... done.\n");
854 static void print_APIC_bitfield (int base)
859 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
860 for (i = 0; i < 8; i++) {
861 v = apic_read(base + i*0x10);
862 for (j = 0; j < 32; j++) {
872 void /*__init*/ print_local_APIC(void * dummy)
874 unsigned int v, ver, maxlvt;
876 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
877 smp_processor_id(), hard_smp_processor_id());
878 v = apic_read(APIC_ID);
879 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
880 v = apic_read(APIC_LVR);
881 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
882 ver = GET_APIC_VERSION(v);
883 maxlvt = get_maxlvt();
885 v = apic_read(APIC_TASKPRI);
886 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
888 if (APIC_INTEGRATED(ver)) { /* !82489DX */
889 v = apic_read(APIC_ARBPRI);
890 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
891 v & APIC_ARBPRI_MASK);
892 v = apic_read(APIC_PROCPRI);
893 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
896 v = apic_read(APIC_EOI);
897 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
898 v = apic_read(APIC_RRR);
899 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
900 v = apic_read(APIC_LDR);
901 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
902 v = apic_read(APIC_DFR);
903 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
904 v = apic_read(APIC_SPIV);
905 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
907 printk(KERN_DEBUG "... APIC ISR field:\n");
908 print_APIC_bitfield(APIC_ISR);
909 printk(KERN_DEBUG "... APIC TMR field:\n");
910 print_APIC_bitfield(APIC_TMR);
911 printk(KERN_DEBUG "... APIC IRR field:\n");
912 print_APIC_bitfield(APIC_IRR);
914 if (APIC_INTEGRATED(ver)) { /* !82489DX */
915 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
916 apic_write(APIC_ESR, 0);
917 v = apic_read(APIC_ESR);
918 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
921 v = apic_read(APIC_ICR);
922 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
923 v = apic_read(APIC_ICR2);
924 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
926 v = apic_read(APIC_LVTT);
927 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
929 if (maxlvt > 3) { /* PC is LVT#4. */
930 v = apic_read(APIC_LVTPC);
931 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
933 v = apic_read(APIC_LVT0);
934 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
935 v = apic_read(APIC_LVT1);
936 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
938 if (maxlvt > 2) { /* ERR is LVT#3. */
939 v = apic_read(APIC_LVTERR);
940 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
943 v = apic_read(APIC_TMICT);
944 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
945 v = apic_read(APIC_TMCCT);
946 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
947 v = apic_read(APIC_TDCR);
948 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
952 void print_all_local_APICs (void)
954 smp_call_function(print_local_APIC, NULL, 1, 1);
955 print_local_APIC(NULL);
958 void /*__init*/ print_PIC(void)
960 extern spinlock_t i8259A_lock;
964 printk(KERN_DEBUG "\nprinting PIC contents\n");
966 spin_lock_irqsave(&i8259A_lock, flags);
968 v = inb(0xa1) << 8 | inb(0x21);
969 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
971 v = inb(0xa0) << 8 | inb(0x20);
972 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
976 v = inb(0xa0) << 8 | inb(0x20);
980 spin_unlock_irqrestore(&i8259A_lock, flags);
982 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
984 v = inb(0x4d1) << 8 | inb(0x4d0);
985 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
988 static void __init enable_IO_APIC(void)
990 struct IO_APIC_reg_01 reg_01;
994 for (i = 0; i < PIN_MAP_SIZE; i++) {
995 irq_2_pin[i].pin = -1;
996 irq_2_pin[i].next = 0;
999 for (i = 0; i < MAX_PIRQS; i++)
1000 pirq_entries[i] = -1;
1003 * The number of IO-APIC IRQ registers (== #pins):
1005 for (i = 0; i < nr_ioapics; i++) {
1006 spin_lock_irqsave(&ioapic_lock, flags);
1007 *(int *)®_01 = io_apic_read(i, 1);
1008 spin_unlock_irqrestore(&ioapic_lock, flags);
1009 nr_ioapic_registers[i] = reg_01.entries+1;
1013 * Do not trust the IO-APIC being empty at bootup
1019 * Not an __init, needed by the reboot code
1021 void disable_IO_APIC(void)
1024 * Clear the IO-APIC before rebooting:
1028 disconnect_bsp_APIC();
1032 * function to set the IO-APIC physical IDs based on the
1033 * values stored in the MPC table.
1035 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1038 static void __init setup_ioapic_ids_from_mpc (void)
1040 struct IO_APIC_reg_00 reg_00;
1041 unsigned long phys_id_present_map = phys_cpu_present_map;
1044 unsigned char old_id;
1045 unsigned long flags;
1048 * Set the IOAPIC ID to the value stored in the MPC table.
1050 for (apic = 0; apic < nr_ioapics; apic++) {
1052 /* Read the register 0 value */
1053 spin_lock_irqsave(&ioapic_lock, flags);
1054 *(int *)®_00 = io_apic_read(apic, 0);
1055 spin_unlock_irqrestore(&ioapic_lock, flags);
1057 old_id = mp_ioapics[apic].mpc_apicid;
1059 if (mp_ioapics[apic].mpc_apicid >= 0xf) {
1060 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1061 apic, mp_ioapics[apic].mpc_apicid);
1062 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1064 mp_ioapics[apic].mpc_apicid = reg_00.ID;
1068 * Sanity check, is the ID really free? Every APIC in a
1069 * system must have a unique ID or we get lots of nice
1070 * 'stuck on smp_invalidate_needed IPI wait' messages.
1072 if (phys_id_present_map & (1 << mp_ioapics[apic].mpc_apicid)) {
1073 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1074 apic, mp_ioapics[apic].mpc_apicid);
1075 for (i = 0; i < 0xf; i++)
1076 if (!(phys_id_present_map & (1 << i)))
1079 panic("Max APIC ID exceeded!\n");
1080 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1082 phys_id_present_map |= 1 << i;
1083 mp_ioapics[apic].mpc_apicid = i;
1085 printk("Setting %d in the phys_id_present_map\n", mp_ioapics[apic].mpc_apicid);
1086 phys_id_present_map |= 1 << mp_ioapics[apic].mpc_apicid;
1091 * We need to adjust the IRQ routing table
1092 * if the ID changed.
1094 if (old_id != mp_ioapics[apic].mpc_apicid)
1095 for (i = 0; i < mp_irq_entries; i++)
1096 if (mp_irqs[i].mpc_dstapic == old_id)
1097 mp_irqs[i].mpc_dstapic
1098 = mp_ioapics[apic].mpc_apicid;
1101 * Read the right value from the MPC table and
1102 * write it into the ID register.
1104 printk(KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1105 mp_ioapics[apic].mpc_apicid);
1107 reg_00.ID = mp_ioapics[apic].mpc_apicid;
1108 spin_lock_irqsave(&ioapic_lock, flags);
1109 io_apic_write(apic, 0, *(int *)®_00);
1110 spin_unlock_irqrestore(&ioapic_lock, flags);
1115 spin_lock_irqsave(&ioapic_lock, flags);
1116 *(int *)®_00 = io_apic_read(apic, 0);
1117 spin_unlock_irqrestore(&ioapic_lock, flags);
1118 if (reg_00.ID != mp_ioapics[apic].mpc_apicid)
1119 panic("could not set ID!\n");
1126 * There is a nasty bug in some older SMP boards, their mptable lies
1127 * about the timer IRQ. We do the following to work around the situation:
1129 * - timer IRQ defaults to IO-APIC IRQ
1130 * - if this function detects that timer IRQs are defunct, then we fall
1131 * back to ISA timer IRQs
1133 static int __init timer_irq_works(void)
1135 unsigned int t1 = jiffies;
1138 /* Let ten ticks pass... */
1139 mdelay((10 * 1000) / HZ);
1142 * Expect a few ticks at least, to be sure some possible
1143 * glue logic does not lock up after one or two first
1144 * ticks in a non-ExtINT mode. Also the local APIC
1145 * might have cached one ExtINT interrupt. Finally, at
1146 * least one tick may be lost due to delays.
1148 if (jiffies - t1 > 4)
1155 * In the SMP+IOAPIC case it might happen that there are an unspecified
1156 * number of pending IRQ events unhandled. These cases are very rare,
1157 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1158 * better to do it this way as thus we do not have to be aware of
1159 * 'pending' interrupts in the IRQ path, except at this point.
1162 * Edge triggered needs to resend any interrupt
1163 * that was delayed but this is now handled in the device
1166 #define enable_edge_ioapic_irq unmask_IO_APIC_irq
1168 static void disable_edge_ioapic_irq (unsigned int irq) { /* nothing */ }
1171 * Starting up a edge-triggered IO-APIC interrupt is
1172 * nasty - we need to make sure that we get the edge.
1173 * If it is already asserted for some reason, we need
1174 * return 1 to indicate that is was pending.
1176 * This is not complete - we should be able to fake
1177 * an edge even if it isn't on the 8259A...
1180 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1182 int was_pending = 0;
1183 unsigned long flags;
1185 spin_lock_irqsave(&ioapic_lock, flags);
1187 disable_8259A_irq(irq);
1188 if (i8259A_irq_pending(irq))
1191 __unmask_IO_APIC_irq(irq);
1192 spin_unlock_irqrestore(&ioapic_lock, flags);
1197 #define shutdown_edge_ioapic_irq disable_edge_ioapic_irq
1200 * Once we have recorded IRQ_PENDING already, we can mask the
1201 * interrupt for real. This prevents IRQ storms from unhandled
1204 static void ack_edge_ioapic_irq(unsigned int irq)
1206 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1207 == (IRQ_PENDING | IRQ_DISABLED))
1208 mask_IO_APIC_irq(irq);
1212 static void end_edge_ioapic_irq (unsigned int i) { /* nothing */ }
1216 * Level triggered interrupts can just be masked,
1217 * and shutting down and starting up the interrupt
1218 * is the same as enabling and disabling them -- except
1219 * with a startup need to return a "was pending" value.
1221 * Level triggered interrupts are special because we
1222 * do not touch any IO-APIC register while handling
1223 * them. We ack the APIC in the end-IRQ handler, not
1224 * in the start-IRQ-handler. Protection against reentrance
1225 * from the same interrupt is still provided, both by the
1226 * generic IRQ layer and by the fact that an unacked local
1227 * APIC does not accept IRQs.
1229 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1231 unmask_IO_APIC_irq(irq);
1233 return 0; /* don't check for pending */
1236 #define shutdown_level_ioapic_irq mask_IO_APIC_irq
1237 #define enable_level_ioapic_irq unmask_IO_APIC_irq
1238 #define disable_level_ioapic_irq mask_IO_APIC_irq
1240 static void end_level_ioapic_irq (unsigned int irq)
1246 * It appears there is an erratum which affects at least version 0x11
1247 * of I/O APIC (that's the 82093AA and cores integrated into various
1248 * chipsets). Under certain conditions a level-triggered interrupt is
1249 * erroneously delivered as edge-triggered one but the respective IRR
1250 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1251 * message but it will never arrive and further interrupts are blocked
1252 * from the source. The exact reason is so far unknown, but the
1253 * phenomenon was observed when two consecutive interrupt requests
1254 * from a given source get delivered to the same CPU and the source is
1255 * temporarily disabled in between.
1257 * A workaround is to simulate an EOI message manually. We achieve it
1258 * by setting the trigger mode to edge and then to level when the edge
1259 * trigger mode gets detected in the TMR of a local APIC for a
1260 * level-triggered interrupt. We mask the source for the time of the
1261 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1262 * The idea is from Manfred Spraul. --macro
1264 i = IO_APIC_VECTOR(irq);
1265 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1269 if (!(v & (1 << (i & 0x1f)))) {
1270 #ifdef APIC_LOCKUP_DEBUG
1271 struct irq_pin_list *entry;
1274 #ifdef APIC_MISMATCH_DEBUG
1275 atomic_inc(&irq_mis_count);
1277 spin_lock(&ioapic_lock);
1278 __mask_and_edge_IO_APIC_irq(irq);
1279 #ifdef APIC_LOCKUP_DEBUG
1280 for (entry = irq_2_pin + irq;;) {
1283 if (entry->pin == -1)
1285 reg = io_apic_read(entry->apic, 0x10 + entry->pin * 2);
1286 if (reg & 0x00004000)
1287 printk(KERN_CRIT "Aieee!!! Remote IRR"
1288 " still set after unlock!\n");
1291 entry = irq_2_pin + entry->next;
1294 __unmask_and_level_IO_APIC_irq(irq);
1295 spin_unlock(&ioapic_lock);
1299 static void mask_and_ack_level_ioapic_irq (unsigned int irq) { /* nothing */ }
1301 static void set_ioapic_affinity (unsigned int irq, unsigned long mask)
1303 unsigned long flags;
1305 * Only the first 8 bits are valid.
1309 spin_lock_irqsave(&ioapic_lock, flags);
1310 __DO_ACTION(1, = mask, )
1311 spin_unlock_irqrestore(&ioapic_lock, flags);
1315 * Level and edge triggered IO-APIC interrupts need different handling,
1316 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1317 * handled with the level-triggered descriptor, but that one has slightly
1318 * more overhead. Level-triggered interrupts cannot be handled with the
1319 * edge-triggered handler, without risking IRQ storms and other ugly
1323 static struct hw_interrupt_type ioapic_edge_irq_type = {
1325 startup_edge_ioapic_irq,
1326 shutdown_edge_ioapic_irq,
1327 enable_edge_ioapic_irq,
1328 disable_edge_ioapic_irq,
1329 ack_edge_ioapic_irq,
1330 end_edge_ioapic_irq,
1331 set_ioapic_affinity,
1334 static struct hw_interrupt_type ioapic_level_irq_type = {
1336 startup_level_ioapic_irq,
1337 shutdown_level_ioapic_irq,
1338 enable_level_ioapic_irq,
1339 disable_level_ioapic_irq,
1340 mask_and_ack_level_ioapic_irq,
1341 end_level_ioapic_irq,
1342 set_ioapic_affinity,
1345 static inline void init_IO_APIC_traps(void)
1350 * NOTE! The local APIC isn't very good at handling
1351 * multiple interrupts at the same interrupt level.
1352 * As the interrupt level is determined by taking the
1353 * vector number and shifting that right by 4, we
1354 * want to spread these out a bit so that they don't
1355 * all fall in the same interrupt level.
1357 * Also, we've got to be careful not to trash gate
1358 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1360 for (irq = 0; irq < NR_IRQS ; irq++) {
1361 if (IO_APIC_IRQ(irq) && !IO_APIC_VECTOR(irq)) {
1363 * Hmm.. We don't have an entry for this,
1364 * so default to an old-fashioned 8259
1365 * interrupt if we can..
1368 make_8259A_irq(irq);
1370 /* Strange. Oh, well.. */
1371 irq_desc[irq].handler = &no_irq_type;
1376 static void enable_lapic_irq (unsigned int irq)
1380 v = apic_read(APIC_LVT0);
1381 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1384 static void disable_lapic_irq (unsigned int irq)
1388 v = apic_read(APIC_LVT0);
1389 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1392 static void ack_lapic_irq (unsigned int irq)
1397 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1399 static struct hw_interrupt_type lapic_irq_type = {
1401 NULL, /* startup_irq() not used for IRQ0 */
1402 NULL, /* shutdown_irq() not used for IRQ0 */
1409 void enable_NMI_through_LVT0 (void * dummy)
1411 unsigned int v, ver;
1413 printk("enable NMI through LVT0 on cpu %d\n", smp_processor_id());
1415 ver = apic_read(APIC_LVR);
1416 ver = GET_APIC_VERSION(ver);
1417 v = APIC_DM_NMI; /* unmask and set to NMI */
1418 if (!APIC_INTEGRATED(ver)) /* 82489DX */
1419 v |= APIC_LVT_LEVEL_TRIGGER;
1420 apic_write_around(APIC_LVT0, v);
1423 static void setup_nmi (void)
1426 * Dirty trick to enable the NMI watchdog ...
1427 * We put the 8259A master into AEOI mode and
1428 * unmask on all local APICs LVT0 as NMI.
1430 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1431 * is from Maciej W. Rozycki - so we do not have to EOI from
1432 * the NMI handler or the timer interrupt.
1434 printk(KERN_INFO "activating NMI Watchdog ...");
1436 smp_call_function(enable_NMI_through_LVT0, NULL, 1, 1);
1437 enable_NMI_through_LVT0(NULL);
1443 * This looks a bit hackish but it's about the only one way of sending
1444 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1445 * not support the ExtINT mode, unfortunately. We need to send these
1446 * cycles as some i82489DX-based boards have glue logic that keeps the
1447 * 8259A interrupt line asserted until INTA. --macro
1449 static inline void unlock_ExtINT_logic(void)
1452 struct IO_APIC_route_entry entry0, entry1;
1453 unsigned char save_control, save_freq_select;
1454 unsigned long flags;
1456 pin = find_isa_irq_pin(8, mp_INT);
1460 spin_lock_irqsave(&ioapic_lock, flags);
1461 *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1462 *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1463 spin_unlock_irqrestore(&ioapic_lock, flags);
1464 clear_IO_APIC_pin(0, pin);
1466 memset(&entry1, 0, sizeof(entry1));
1468 entry1.dest_mode = 0; /* physical delivery */
1469 entry1.mask = 0; /* unmask IRQ now */
1470 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1471 entry1.delivery_mode = dest_ExtINT;
1472 entry1.polarity = entry0.polarity;
1476 spin_lock_irqsave(&ioapic_lock, flags);
1477 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1478 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1479 spin_unlock_irqrestore(&ioapic_lock, flags);
1481 save_control = CMOS_READ(RTC_CONTROL);
1482 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1483 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1485 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1490 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1494 CMOS_WRITE(save_control, RTC_CONTROL);
1495 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1496 clear_IO_APIC_pin(0, pin);
1498 spin_lock_irqsave(&ioapic_lock, flags);
1499 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1500 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1501 spin_unlock_irqrestore(&ioapic_lock, flags);
1505 * This code may look a bit paranoid, but it's supposed to cooperate with
1506 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1507 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1508 * fanatically on his truly buggy board.
1510 static inline void check_timer(void)
1516 * get/set the timer IRQ vector:
1518 disable_8259A_irq(0);
1519 vector = assign_irq_vector(0);
1520 set_intr_gate(vector, interrupt[0]);
1523 * Subtle, code in do_timer_interrupt() expects an AEOI
1524 * mode for the 8259A whenever interrupts are routed
1525 * through I/O APICs. Also IRQ0 has to be enabled in
1526 * the 8259A which implies the virtual wire has to be
1527 * disabled in the local APIC.
1529 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1531 enable_8259A_irq(0);
1533 pin1 = find_isa_irq_pin(0, mp_INT);
1534 pin2 = find_isa_irq_pin(0, mp_ExtINT);
1536 printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1540 * Ok, does IRQ0 through the IOAPIC work?
1542 unmask_IO_APIC_irq(0);
1543 if (timer_irq_works()) {
1544 if (nmi_watchdog == NMI_IO_APIC) {
1545 disable_8259A_irq(0);
1547 enable_8259A_irq(0);
1548 check_nmi_watchdog();
1552 clear_IO_APIC_pin(0, pin1);
1553 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1556 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1558 printk("\n..... (found pin %d) ...", pin2);
1560 * legacy devices should be connected to IO APIC #0
1562 setup_ExtINT_IRQ0_pin(pin2, vector);
1563 if (timer_irq_works()) {
1566 replace_pin_at_irq(0, 0, pin1, 0, pin2);
1568 add_pin_to_irq(0, 0, pin2);
1569 if (nmi_watchdog == NMI_IO_APIC) {
1571 check_nmi_watchdog();
1576 * Cleanup, just in case ...
1578 clear_IO_APIC_pin(0, pin2);
1580 printk(" failed.\n");
1583 printk(KERN_WARNING "timer doesnt work through the IO-APIC - disabling NMI Watchdog!\n");
1587 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1589 disable_8259A_irq(0);
1590 irq_desc[0].handler = &lapic_irq_type;
1591 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1592 enable_8259A_irq(0);
1594 if (timer_irq_works()) {
1595 printk(" works.\n");
1598 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1599 printk(" failed.\n");
1601 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1605 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1607 unlock_ExtINT_logic();
1609 if (timer_irq_works()) {
1610 printk(" works.\n");
1613 printk(" failed :(.\n");
1614 panic("IO-APIC + timer doesn't work! pester mingo@redhat.com");
1619 * IRQ's that are handled by the old PIC in all cases:
1620 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1621 * Linux doesn't really care, as it's not actually used
1622 * for any interrupt handling anyway.
1623 * - There used to be IRQ13 here as well, but all
1624 * MPS-compliant must not use it for FPU coupling and we
1625 * want to use exception 16 anyway. And there are
1626 * systems who connect it to an I/O APIC for other uses.
1627 * Thus we don't mark it special any longer.
1629 * Additionally, something is definitely wrong with irq9
1632 #define PIC_IRQS (1<<2)
1634 void __init setup_IO_APIC(void)
1638 io_apic_irqs = ~PIC_IRQS;
1639 printk("ENABLING IO-APIC IRQs\n");
1642 * Set up the IO-APIC IRQ routing table by parsing the MP-BIOS
1645 setup_ioapic_ids_from_mpc();
1647 setup_IO_APIC_irqs();
1648 init_IO_APIC_traps();