1 /* x86-64 MTRR (Memory Type Range Register) driver.
2 Based largely upon arch/i386/kernel/mtrr.c
4 Copyright (C) 1997-2000 Richard Gooch
5 Copyright (C) 2002 Dave Jones.
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Library General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Library General Public License for more details.
17 You should have received a copy of the GNU Library General Public
18 License along with this library; if not, write to the Free
19 Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 (For earlier history, see arch/i386/kernel/mtrr.c)
22 v2.00 September 2001 Dave Jones <davej@suse.de>
23 Initial rewrite for x86-64.
24 Removal of non-Intel style MTRR code.
25 v2.01 June 2002 Dave Jones <davej@suse.de>
26 Removal of redundant abstraction layer.
28 v2.02 July 2002 Dave Jones <davej@suse.de>
29 Fix gentry inconsistencies between kernel/userspace.
30 More casts to clean up warnings.
33 #include <linux/types.h>
34 #include <linux/errno.h>
35 #include <linux/sched.h>
36 #include <linux/tty.h>
37 #include <linux/timer.h>
38 #include <linux/config.h>
39 #include <linux/kernel.h>
40 #include <linux/wait.h>
41 #include <linux/string.h>
42 #include <linux/slab.h>
43 #include <linux/ioport.h>
44 #include <linux/delay.h>
46 #include <linux/ctype.h>
47 #include <linux/proc_fs.h>
48 #include <linux/devfs_fs_kernel.h>
50 #include <linux/module.h>
51 #define MTRR_NEED_STRINGS
53 #include <linux/init.h>
54 #include <linux/smp.h>
55 #include <linux/smp_lock.h>
56 #include <linux/agp_backend.h>
58 #include <asm/uaccess.h>
60 #include <asm/processor.h>
61 #include <asm/system.h>
62 #include <asm/pgtable.h>
63 #include <asm/segment.h>
64 #include <asm/bitops.h>
65 #include <asm/atomic.h>
68 #include <asm/hardirq.h>
69 #include <linux/irq.h>
71 #define MTRR_VERSION "2.02 (20020716)"
73 #define MTRR_BEG_BIT 12
74 #define MTRR_END_BIT 7
83 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
84 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
86 #define NUM_FIXED_RANGES 88
88 #define MTRR_CHANGE_MASK_FIXED 0x01
89 #define MTRR_CHANGE_MASK_VARIABLE 0x02
90 #define MTRR_CHANGE_MASK_DEFTYPE 0x04
97 #define set_mtrr(reg,base,size,type) set_mtrr_smp (reg, base, size, type)
99 #define set_mtrr(reg,base,size,type) set_mtrr_up (reg, base, size, type, TRUE)
102 #if defined(CONFIG_PROC_FS) || defined(CONFIG_DEVFS_FS)
103 #define USERSPACE_INTERFACE
106 #ifdef USERSPACE_INTERFACE
107 static char *ascii_buffer;
108 static unsigned int ascii_buf_bytes;
109 static void compute_ascii (void);
111 #define compute_ascii() while (0)
114 static unsigned int *usage_table;
115 static DECLARE_MUTEX (mtrr_lock);
117 struct set_mtrr_context {
125 /* Put the processor into a state where MTRRs can be safely set */
126 static void set_mtrr_prepare (struct set_mtrr_context *ctxt)
130 /* Disable interrupts locally */
131 __save_flags(ctxt->flags);
134 /* Save value of CR4 and clear Page Global Enable (bit 7) */
135 if (test_bit(X86_FEATURE_PGE, boot_cpu_data.x86_capability)) {
136 ctxt->cr4val = read_cr4();
137 write_cr4(ctxt->cr4val & ~(1UL << 7));
140 /* Disable and flush caches. Note that wbinvd flushes the TLBs as
142 cr0 = read_cr0() | 0x40000000;
147 rdmsr(MSR_MTRRdefType, ctxt->deftype_lo, ctxt->deftype_hi);
150 static void set_mtrr_disable(struct set_mtrr_context *ctxt)
152 /* Disable MTRRs, and set the default type to uncached */
153 wrmsr(MSR_MTRRdefType, ctxt->deftype_lo & 0xf300UL, ctxt->deftype_hi);
156 /* Restore the processor after a set_mtrr_prepare */
157 static void set_mtrr_done (struct set_mtrr_context *ctxt)
159 /* Flush caches and TLBs */
162 /* Restore MTRRdefType */
163 wrmsr(MSR_MTRRdefType, ctxt->deftype_lo, ctxt->deftype_hi);
166 write_cr0(read_cr0() & 0xbfffffff);
168 /* Restore value of CR4 */
169 if (test_bit(X86_FEATURE_PGE, boot_cpu_data.x86_capability))
170 write_cr4 (ctxt->cr4val);
172 /* Re-enable interrupts locally (if enabled previously) */
173 __restore_flags(ctxt->flags);
177 /* This function returns the number of variable MTRRs */
178 static unsigned int get_num_var_ranges (void)
182 rdmsr (MSR_MTRRcap, config, dummy);
183 return (config & 0xff);
187 /* Returns non-zero if we have the write-combining memory type */
188 static int have_wrcomb (void)
192 rdmsr (MSR_MTRRcap, config, dummy);
193 return (config & (1 << 10));
197 static u64 size_or_mask, size_and_mask;
199 static void get_mtrr (unsigned int reg, u64 *base, u32 *size, mtrr_type * type)
201 u32 mask_lo, mask_hi;
202 u32 base_lo, base_hi;
204 rdmsr (MSR_MTRRphysMask(reg), mask_lo, mask_hi);
205 if ((mask_lo & 0x800) == 0) {
206 /* Invalid (i.e. free) range */
213 rdmsr (MSR_MTRRphysBase(reg), base_lo, base_hi);
215 /* Work out the shifted address mask */
216 mask_lo = size_or_mask | mask_hi << (32 - PAGE_SHIFT) |
217 mask_lo >> PAGE_SHIFT;
219 /* This works correctly if size is a power of two, i.e. a
220 continguous range. */
222 *base = base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT;
223 *type = base_lo & 0xff;
227 * Set variable MTRR register on the local CPU.
228 * <reg> The register to set.
229 * <base> The base address of the region.
230 * <size> The size of the region. If this is 0 the region is disabled.
231 * <type> The type of the region.
232 * <do_safe> If TRUE, do the change safely. If FALSE, safety measures should
233 * be done externally.
235 static void set_mtrr_up (unsigned int reg, u64 base,
236 u32 size, mtrr_type type, int do_safe)
238 struct set_mtrr_context ctxt;
241 set_mtrr_prepare (&ctxt);
242 set_mtrr_disable (&ctxt);
246 /* The invalid bit is kept in the mask, so we simply clear the
247 relevant mask register to disable a range. */
248 wrmsr (MSR_MTRRphysMask(reg), 0, 0);
250 wrmsr (MSR_MTRRphysBase(reg), base << PAGE_SHIFT | type,
251 (base & size_and_mask) >> (32 - PAGE_SHIFT));
252 wrmsr(MSR_MTRRphysMask(reg), -size << PAGE_SHIFT | 0x800,
253 (-size & size_and_mask) >> (32 - PAGE_SHIFT));
256 set_mtrr_done (&ctxt);
262 struct mtrr_var_range {
269 /* Get the MSR pair relating to a var range */
270 static void __init get_mtrr_var_range (unsigned int index,
271 struct mtrr_var_range *vr)
273 rdmsr (MSR_MTRRphysBase(index), vr->base_lo, vr->base_hi);
274 rdmsr (MSR_MTRRphysMask(index), vr->mask_lo, vr->mask_hi);
278 /* Set the MSR pair relating to a var range. Returns TRUE if
280 static int __init set_mtrr_var_range_testing (unsigned int index,
281 struct mtrr_var_range *vr)
286 rdmsr (MSR_MTRRphysBase(index), lo, hi);
287 if ((vr->base_lo & 0xfffff0ff) != (lo & 0xfffff0ff) ||
288 (vr->base_hi & 0x000fffff) != (hi & 0x000fffff)) {
289 wrmsr (MSR_MTRRphysBase(index), vr->base_lo, vr->base_hi);
293 rdmsr (MSR_MTRRphysMask(index), lo, hi);
294 if ((vr->mask_lo & 0xfffff800) != (lo & 0xfffff800) ||
295 (vr->mask_hi & 0x000fffff) != (hi & 0x000fffff)) {
296 wrmsr (MSR_MTRRphysMask(index), vr->mask_lo, vr->mask_hi);
303 static void __init get_fixed_ranges (mtrr_type * frs)
305 u32 *p = (u32 *) frs;
308 rdmsr (MSR_MTRRfix64K_00000, p[0], p[1]);
310 for (i = 0; i < 2; i++)
311 rdmsr (MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]);
312 for (i = 0; i < 8; i++)
313 rdmsr (MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]);
317 static int __init set_fixed_ranges_testing (mtrr_type * frs)
319 u32 *p = (u32 *) frs;
324 Dprintk (KERN_INFO "mtrr: rdmsr 64K_00000\n");
325 rdmsr (MSR_MTRRfix64K_00000, lo, hi);
326 if (p[0] != lo || p[1] != hi) {
327 Dprintk (KERN_INFO "mtrr: Writing %x:%x to 64K MSR. lohi were %x:%x\n", p[0], p[1], lo, hi);
328 wrmsr (MSR_MTRRfix64K_00000, p[0], p[1]);
332 Dprintk (KERN_INFO "mtrr: rdmsr 16K_80000\n");
333 for (i = 0; i < 2; i++) {
334 rdmsr (MSR_MTRRfix16K_80000 + i, lo, hi);
335 if (p[2 + i * 2] != lo || p[3 + i * 2] != hi) {
336 Dprintk (KERN_INFO "mtrr: Writing %x:%x to 16K MSR%d. lohi were %x:%x\n", p[2 + i * 2], p[3 + i * 2], i, lo, hi );
337 wrmsr (MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]);
342 Dprintk (KERN_INFO "mtrr: rdmsr 4K_C0000\n");
343 for (i = 0; i < 8; i++) {
344 rdmsr (MSR_MTRRfix4K_C0000 + i, lo, hi);
345 Dprintk (KERN_INFO "mtrr: MTRRfix4K_C0000+%d = %x:%x\n", i, lo, hi);
346 if (p[6 + i * 2] != lo || p[7 + i * 2] != hi) {
347 Dprintk (KERN_INFO "mtrr: Writing %x:%x to 4K MSR%d. lohi were %x:%x\n", p[6 + i * 2], p[7 + i * 2], i, lo, hi);
348 wrmsr (MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]);
357 unsigned int num_var_ranges;
358 struct mtrr_var_range *var_ranges;
359 mtrr_type fixed_ranges[NUM_FIXED_RANGES];
361 unsigned char enabled;
365 /* Grab all of the MTRR state for this CPU into *state */
366 static void __init get_mtrr_state (struct mtrr_state *state)
368 unsigned int nvrs, i;
369 struct mtrr_var_range *vrs;
372 nvrs = state->num_var_ranges = get_num_var_ranges();
373 vrs = state->var_ranges
374 = kmalloc (nvrs * sizeof (struct mtrr_var_range), GFP_KERNEL);
376 nvrs = state->num_var_ranges = 0;
378 for (i = 0; i < nvrs; i++)
379 get_mtrr_var_range (i, &vrs[i]);
380 get_fixed_ranges (state->fixed_ranges);
382 rdmsr (MSR_MTRRdefType, lo, dummy);
383 state->def_type = (lo & 0xff);
384 state->enabled = (lo & 0xc00) >> 10;
388 /* Free resources associated with a struct mtrr_state */
389 static void __init finalize_mtrr_state (struct mtrr_state *state)
391 if (state->var_ranges)
392 kfree (state->var_ranges);
397 * Set the MTRR state for this CPU.
398 * <state> The MTRR state information to read.
399 * <ctxt> Some relevant CPU context.
400 * [NOTE] The CPU must already be in a safe state for MTRR changes.
401 * [RETURNS] 0 if no changes made, else a mask indication what was changed.
403 static u64 __init set_mtrr_state (struct mtrr_state *state,
404 struct set_mtrr_context *ctxt)
409 for (i = 0; i < state->num_var_ranges; i++)
410 if (set_mtrr_var_range_testing (i, &state->var_ranges[i]))
411 change_mask |= MTRR_CHANGE_MASK_VARIABLE;
413 if (set_fixed_ranges_testing (state->fixed_ranges))
414 change_mask |= MTRR_CHANGE_MASK_FIXED;
415 /* Set_mtrr_restore restores the old value of MTRRdefType,
416 so to set it we fiddle with the saved value */
417 if ((ctxt->deftype_lo & 0xff) != state->def_type
418 || ((ctxt->deftype_lo & 0xc00) >> 10) != state->enabled) {
419 ctxt->deftype_lo |= (state->def_type | state->enabled << 10);
420 change_mask |= MTRR_CHANGE_MASK_DEFTYPE;
427 static atomic_t undone_count;
428 static volatile int wait_barrier_mtrr_disable = FALSE;
429 static volatile int wait_barrier_execute = FALSE;
430 static volatile int wait_barrier_cache_enable = FALSE;
432 struct set_mtrr_data {
435 unsigned int smp_reg;
440 * Synchronisation handler. Executed by "other" CPUs.
442 static void ipi_handler (void *info)
444 struct set_mtrr_data *data = info;
445 struct set_mtrr_context ctxt;
447 set_mtrr_prepare (&ctxt);
448 /* Notify master that I've flushed and disabled my cache */
449 atomic_dec (&undone_count);
451 while (wait_barrier_mtrr_disable) {
455 set_mtrr_disable (&ctxt);
456 /* wait again for disable confirmation*/
457 atomic_dec (&undone_count);
458 while (wait_barrier_execute) {
463 /* The master has cleared me to execute */
464 set_mtrr_up (data->smp_reg, data->smp_base, data->smp_size,
465 data->smp_type, FALSE);
467 /* Notify master CPU that I've executed the function */
468 atomic_dec (&undone_count);
470 /* Wait for master to clear me to enable cache and return */
471 while (wait_barrier_cache_enable) {
475 set_mtrr_done (&ctxt);
479 static void set_mtrr_smp (unsigned int reg, u64 base, u32 size, mtrr_type type)
481 struct set_mtrr_data data;
482 struct set_mtrr_context ctxt;
485 data.smp_base = base;
486 data.smp_size = size;
487 data.smp_type = type;
488 wait_barrier_execute = TRUE;
489 wait_barrier_cache_enable = TRUE;
490 wait_barrier_mtrr_disable = TRUE;
491 atomic_set (&undone_count, smp_num_cpus - 1);
493 /* Start the ball rolling on other CPUs */
494 if (smp_call_function (ipi_handler, &data, 1, 0) != 0)
495 panic ("mtrr: timed out waiting for other CPUs\n");
497 /* Flush and disable the local CPU's cache */
498 set_mtrr_prepare (&ctxt);
499 while (atomic_read (&undone_count) > 0) {
504 /* Set up for completion wait and then release other CPUs to change MTRRs*/
505 atomic_set (&undone_count, smp_num_cpus - 1);
506 wait_barrier_mtrr_disable = FALSE;
507 set_mtrr_disable (&ctxt);
509 /* Wait for all other CPUs to flush and disable their caches */
510 while (atomic_read (&undone_count) > 0) {
515 /* Set up for completion wait and then release other CPUs to change MTRRs */
516 atomic_set (&undone_count, smp_num_cpus - 1);
517 wait_barrier_execute = FALSE;
518 set_mtrr_up (reg, base, size, type, FALSE);
520 /* Now wait for other CPUs to complete the function */
521 while (atomic_read (&undone_count) > 0) {
526 /* Now all CPUs should have finished the function. Release the barrier to
527 allow them to re-enable their caches and return from their interrupt,
528 then enable the local cache and return */
529 wait_barrier_cache_enable = FALSE;
530 set_mtrr_done (&ctxt);
534 /* Some BIOS's are fucked and don't set all MTRRs the same! */
535 static void __init mtrr_state_warn (u32 mask)
539 if (mask & MTRR_CHANGE_MASK_FIXED)
540 printk (KERN_INFO "mtrr: your CPUs had inconsistent fixed MTRR settings\n");
541 if (mask & MTRR_CHANGE_MASK_VARIABLE)
542 printk (KERN_INFO "mtrr: your CPUs had inconsistent variable MTRR settings\n");
543 if (mask & MTRR_CHANGE_MASK_DEFTYPE)
544 printk (KERN_INFO "mtrr: your CPUs had inconsistent MTRRdefType settings\n");
545 printk (KERN_INFO "mtrr: probably your BIOS does not setup all CPUs\n");
548 #endif /* CONFIG_SMP */
551 static inline char * attrib_to_str (int x)
553 return (x <= 6) ? mtrr_strings[x] : "?";
557 static void __init init_table (void)
561 max = get_num_var_ranges ();
562 if ((usage_table = kmalloc (max * sizeof *usage_table, GFP_KERNEL))==NULL) {
563 printk ("mtrr: could not allocate\n");
567 for (i = 0; i < max; i++)
570 #ifdef USERSPACE_INTERFACE
571 if ((ascii_buffer = kmalloc (max * LINE_SIZE, GFP_KERNEL)) == NULL) {
572 printk ("mtrr: could not allocate\n");
583 * returns the index of the region on success, else -1 on error.
585 static int get_free_region(void)
592 max = get_num_var_ranges ();
593 for (i = 0; i < max; ++i) {
594 get_mtrr (i, &lbase, &lsize, <ype);
603 * mtrr_add_page - Add a memory type region
604 * @base: Physical base address of region in pages (4 KB)
605 * @size: Physical size of region in pages (4 KB)
606 * @type: Type of MTRR desired
607 * @increment: If this is true do usage counting on the region
608 * Returns The MTRR register on success, else a negative number
609 * indicating the error code.
611 * Memory type region registers control the caching on newer
612 * processors. This function allows drivers to request an MTRR is added.
613 * The caller should expect to need to provide a power of two size on
614 * an equivalent power of two boundary.
616 * If the region cannot be added either because all regions are in use
617 * or the CPU cannot support it a negative value is returned. On success
618 * the register number for this entry is returned, but should be treated
621 * On a multiprocessor machine the changes are made to all processors.
623 * The available types are
625 * %MTRR_TYPE_UNCACHABLE - No caching
626 * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
627 * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
628 * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
630 * BUGS: Needs a quiet flag for the cases where drivers do not mind
631 * failures and do not wish system log messages to be sent.
634 int mtrr_add_page (u64 base, u32 size, unsigned int type, char increment)
641 if (base + size < 0x100) {
643 "mtrr: cannot set region below 1 MiB (0x%Lx000,0x%x000)\n",
648 #if 0 && defined(__x86_64__) && defined(CONFIG_AGP)
651 if (type != MTRR_TYPE_UNCACHABLE && agp_copy_info(&info) >= 0 &&
652 base<<PAGE_SHIFT >= info.aper_base &&
653 (base<<PAGE_SHIFT)+(size<<PAGE_SHIFT) >=
654 info.aper_base+info.aper_size*1024*1024)
655 printk(KERN_INFO "%s[%d] setting conflicting mtrr into agp aperture\n",current->comm,current->pid);
659 /* Check upper bits of base and last are equal and lower bits are 0
660 for base and 1 for last */
661 last = base + size - 1;
662 for (lbase = base; !(lbase & 1) && (last & 1);
663 lbase = lbase >> 1, last = last >> 1) ;
667 "mtrr: base(0x%Lx000) is not aligned on a size(0x%x000) boundary\n",
672 if (type >= MTRR_NUM_TYPES) {
673 printk ("mtrr: type: %u illegal\n", type);
677 /* If the type is WC, check that this processor supports it */
678 if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) {
680 "mtrr: your processor doesn't support write-combining\n");
684 if (base & size_or_mask) {
685 printk (KERN_WARNING "mtrr: base(%Lx) exceeds the MTRR width(%Lx)\n",
690 if (size & size_or_mask) {
691 printk (KERN_WARNING "mtrr: size exceeds the MTRR width\n");
695 increment = increment ? 1 : 0;
696 max = get_num_var_ranges ();
697 /* Search for existing MTRR */
699 for (i = 0; i < max; ++i) {
700 get_mtrr (i, &lbase, &lsize, <ype);
701 if (base >= lbase + lsize)
703 if ((base < lbase) && (base + size <= lbase))
706 /* At this point we know there is some kind of overlap/enclosure */
707 if ((base < lbase) || (base + size > lbase + lsize)) {
710 "mtrr: 0x%Lx000,0x%x000 overlaps existing"
711 " 0x%Lx000,0x%x000\n", base, size, lbase, lsize);
714 /* New region is enclosed by an existing region */
716 if (type == MTRR_TYPE_UNCACHABLE)
720 ("mtrr: type mismatch for %Lx000,%x000 old: %s new: %s\n",
722 attrib_to_str (ltype),
723 attrib_to_str (type));
732 /* Search for an empty MTRR */
733 i = get_free_region();
736 printk ("mtrr: no more MTRRs available\n");
739 set_mtrr (i, base, size, type);
748 * mtrr_add - Add a memory type region
749 * @base: Physical base address of region
750 * @size: Physical size of region
751 * @type: Type of MTRR desired
752 * @increment: If this is true do usage counting on the region
753 * Return the MTRR register on success, else a negative numbe
754 * indicating the error code.
756 * Memory type region registers control the caching on newer processors.
757 * This function allows drivers to request an MTRR is added.
758 * The caller should expect to need to provide a power of two size on
759 * an equivalent power of two boundary.
761 * If the region cannot be added either because all regions are in use
762 * or the CPU cannot support it a negative value is returned. On success
763 * the register number for this entry is returned, but should be treated
766 * On a multiprocessor machine the changes are made to all processors.
767 * This is required on x86 by the Intel processors.
769 * The available types are
771 * %MTRR_TYPE_UNCACHABLE - No caching
772 * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
773 * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
774 * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
776 * BUGS: Needs a quiet flag for the cases where drivers do not mind
777 * failures and do not wish system log messages to be sent.
780 int mtrr_add (u64 base, u32 size, unsigned int type, char increment)
782 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
783 printk ("mtrr: size and base must be multiples of 4 kiB\n");
784 printk ("mtrr: size: 0x%x base: 0x%Lx\n", size, base);
787 return mtrr_add_page (base >> PAGE_SHIFT, size >> PAGE_SHIFT, type,
793 * mtrr_del_page - delete a memory type region
794 * @reg: Register returned by mtrr_add
795 * @base: Physical base address
796 * @size: Size of region
798 * If register is supplied then base and size are ignored. This is
799 * how drivers should call it.
801 * Releases an MTRR region. If the usage count drops to zero the
802 * register is freed and the region returns to default state.
803 * On success the register is returned, on failure a negative error
807 int mtrr_del_page (int reg, u64 base, u32 size)
814 max = get_num_var_ranges ();
817 /* Search for existing MTRR */
818 for (i = 0; i < max; ++i) {
819 get_mtrr (i, &lbase, &lsize, <ype);
820 if (lbase == base && lsize == size) {
827 printk ("mtrr: no MTRR for %Lx000,%x000 found\n", base, size);
834 printk ("mtrr: register: %d too big\n", reg);
837 get_mtrr (reg, &lbase, &lsize, <ype);
841 printk ("mtrr: MTRR %d not used\n", reg);
845 if (usage_table[reg] < 1) {
847 printk ("mtrr: reg: %d has count=0\n", reg);
851 if (--usage_table[reg] < 1)
852 set_mtrr (reg, 0, 0, 0);
860 * mtrr_del - delete a memory type region
861 * @reg: Register returned by mtrr_add
862 * @base: Physical base address
863 * @size: Size of region
865 * If register is supplied then base and size are ignored. This is
866 * how drivers should call it.
868 * Releases an MTRR region. If the usage count drops to zero the
869 * register is freed and the region returns to default state.
870 * On success the register is returned, on failure a negative error
874 int mtrr_del (int reg, u64 base, u32 size)
876 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
877 printk ("mtrr: size and base must be multiples of 4 kiB\n");
878 printk ("mtrr: size: 0x%x base: 0x%Lx\n", size, base);
881 return mtrr_del_page (reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT);
885 #ifdef USERSPACE_INTERFACE
887 static int mtrr_file_add (u64 base, u32 size, unsigned int type,
888 struct file *file, int page)
891 unsigned int *fcount = file->private_data;
893 max = get_num_var_ranges ();
894 if (fcount == NULL) {
896 kmalloc (max * sizeof *fcount, GFP_KERNEL)) == NULL) {
897 printk ("mtrr: could not allocate\n");
900 memset (fcount, 0, max * sizeof *fcount);
901 file->private_data = fcount;
905 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
907 (KERN_INFO "mtrr: size and base must be multiples of 4 kiB\n");
908 printk (KERN_INFO "mtrr: size: 0x%x base: 0x%Lx\n", size, base);
915 reg = mtrr_add_page (base, size, type, 1);
923 static int mtrr_file_del (u64 base, u32 size,
924 struct file *file, int page)
927 unsigned int *fcount = file->private_data;
930 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
932 (KERN_INFO "mtrr: size and base must be multiples of 4 kiB\n");
933 printk (KERN_INFO "mtrr: size: 0x%x base: 0x%Lx\n", size, base);
939 reg = mtrr_del_page (-1, base, size);
951 static ssize_t mtrr_read (struct file *file, char *buf, size_t len,
957 if (pos != n || pos >= ascii_buf_bytes)
960 if (len > ascii_buf_bytes - pos)
961 len = ascii_buf_bytes - pos;
963 if (copy_to_user (buf, ascii_buffer + pos, len))
971 static ssize_t mtrr_write (struct file *file, const char *buf,
972 size_t len, loff_t * ppos)
973 /* Format of control line:
974 "base=%Lx size=%Lx type=%s" OR:
982 char line[LINE_SIZE];
984 if (!capable(CAP_SYS_ADMIN))
987 /* Can't seek (pwrite) on this device */
988 if (ppos != &file->f_pos)
990 memset (line, 0, LINE_SIZE);
995 if (copy_from_user (line, buf, len - 1))
997 ptr = line + strlen (line) - 1;
1002 if (!strncmp (line, "disable=", 8)) {
1003 reg = simple_strtoul (line + 8, &ptr, 0);
1004 err = mtrr_del_page (reg, 0, 0);
1010 if (strncmp (line, "base=", 5)) {
1011 printk (KERN_INFO "mtrr: no \"base=\" in line: \"%s\"\n", line);
1015 base = simple_strtoull (line + 5, &ptr, 0);
1017 for (; isspace (*ptr); ++ptr) ;
1019 if (strncmp (ptr, "size=", 5)) {
1020 printk (KERN_INFO "mtrr: no \"size=\" in line: \"%s\"\n", line);
1024 size = simple_strtoull (ptr + 5, &ptr, 0);
1026 if ((base & 0xfff) || (size & 0xfff)) {
1027 printk (KERN_INFO "mtrr: size and base must be multiples of 4 kiB\n");
1028 printk (KERN_INFO "mtrr: size: 0x%x base: 0x%Lx\n", size, base);
1032 for (; isspace (*ptr); ++ptr) ;
1034 if (strncmp (ptr, "type=", 5)) {
1035 printk (KERN_INFO "mtrr: no \"type=\" in line: \"%s\"\n", line);
1040 for (; isspace (*ptr); ++ptr) ;
1042 for (i = 0; i < MTRR_NUM_TYPES; ++i) {
1043 if (strcmp (ptr, mtrr_strings[i]))
1045 base >>= PAGE_SHIFT;
1046 size >>= PAGE_SHIFT;
1047 err = mtrr_add_page ((u64) base, size, i, 1);
1052 printk (KERN_INFO "mtrr: illegal type: \"%s\"\n", ptr);
1057 static int mtrr_ioctl (struct inode *inode, struct file *file,
1058 unsigned int cmd, unsigned long arg)
1062 struct mtrr_sentry sentry;
1063 struct mtrr_gentry gentry;
1067 return -ENOIOCTLCMD;
1069 case MTRRIOC_ADD_ENTRY:
1070 if (!capable(CAP_SYS_ADMIN))
1072 if (copy_from_user (&sentry, (void *) arg, sizeof sentry))
1074 err = mtrr_file_add (sentry.base, sentry.size, sentry.type,
1080 case MTRRIOC_SET_ENTRY:
1081 if (!capable(CAP_SYS_ADMIN))
1083 if (copy_from_user (&sentry, (void *) arg, sizeof sentry))
1085 err = mtrr_add (sentry.base, sentry.size, sentry.type, 0);
1090 case MTRRIOC_DEL_ENTRY:
1091 if (!capable(CAP_SYS_ADMIN))
1093 if (copy_from_user (&sentry, (void *) arg, sizeof sentry))
1095 err = mtrr_file_del (sentry.base, sentry.size, file, 0);
1100 case MTRRIOC_KILL_ENTRY:
1101 if (!capable(CAP_SYS_ADMIN))
1103 if (copy_from_user (&sentry, (void *) arg, sizeof sentry))
1105 err = mtrr_del (-1, sentry.base, sentry.size);
1110 case MTRRIOC_GET_ENTRY:
1111 if (copy_from_user (&gentry, (void *) arg, sizeof gentry))
1113 if (gentry.regnum >= get_num_var_ranges ())
1115 get_mtrr (gentry.regnum, (u64*) &gentry.base, &gentry.size, &type);
1117 /* Hide entries that go above 4GB */
1118 if (gentry.base + gentry.size > 0x100000
1119 || gentry.size == 0x100000)
1120 gentry.base = gentry.size = gentry.type = 0;
1122 gentry.base <<= PAGE_SHIFT;
1123 gentry.size <<= PAGE_SHIFT;
1127 if (copy_to_user ((void *) arg, &gentry, sizeof gentry))
1131 case MTRRIOC_ADD_PAGE_ENTRY:
1132 if (!capable(CAP_SYS_ADMIN))
1134 if (copy_from_user (&sentry, (void *) arg, sizeof sentry))
1136 err = mtrr_file_add (sentry.base, sentry.size, sentry.type, file, 1);
1141 case MTRRIOC_SET_PAGE_ENTRY:
1142 if (!capable(CAP_SYS_ADMIN))
1144 if (copy_from_user (&sentry, (void *) arg, sizeof sentry))
1146 err = mtrr_add_page (sentry.base, sentry.size, sentry.type, 0);
1151 case MTRRIOC_DEL_PAGE_ENTRY:
1152 if (!capable(CAP_SYS_ADMIN))
1154 if (copy_from_user (&sentry, (void *) arg, sizeof sentry))
1156 err = mtrr_file_del (sentry.base, sentry.size, file, 1);
1161 case MTRRIOC_KILL_PAGE_ENTRY:
1162 if (!capable(CAP_SYS_ADMIN))
1164 if (copy_from_user (&sentry, (void *) arg, sizeof sentry))
1166 err = mtrr_del_page (-1, sentry.base, sentry.size);
1171 case MTRRIOC_GET_PAGE_ENTRY:
1172 if (copy_from_user (&gentry, (void *) arg, sizeof gentry))
1174 if (gentry.regnum >= get_num_var_ranges ())
1176 get_mtrr (gentry.regnum, (u64*) &gentry.base, &gentry.size, &type);
1179 if (copy_to_user ((void *) arg, &gentry, sizeof gentry))
1187 static int mtrr_close (struct inode *ino, struct file *file)
1190 unsigned int *fcount = file->private_data;
1196 max = get_num_var_ranges ();
1197 for (i = 0; i < max; ++i) {
1198 while (fcount[i] > 0) {
1199 if (mtrr_del (i, 0, 0) < 0)
1200 printk ("mtrr: reg %d not used\n", i);
1206 file->private_data = NULL;
1211 static struct file_operations mtrr_fops = {
1219 #ifdef CONFIG_PROC_FS
1220 static struct proc_dir_entry *proc_root_mtrr;
1223 static devfs_handle_t devfs_handle;
1225 static void compute_ascii (void)
1233 ascii_buf_bytes = 0;
1234 max = get_num_var_ranges ();
1235 for (i = 0; i < max; i++) {
1236 get_mtrr (i, &base, &size, &type);
1240 if (size < (0x100000 >> PAGE_SHIFT)) {
1243 size <<= PAGE_SHIFT - 10;
1246 size >>= 20 - PAGE_SHIFT;
1248 sprintf (ascii_buffer + ascii_buf_bytes,
1249 "reg%02i: base=0x%05Lx000 (%4iMB), size=%4i%cB: %s, count=%d\n",
1250 i, base, (u32) base >> (20 - PAGE_SHIFT), size, factor,
1251 attrib_to_str (type), usage_table[i]);
1252 ascii_buf_bytes += strlen (ascii_buffer + ascii_buf_bytes);
1255 devfs_set_file_size (devfs_handle, ascii_buf_bytes);
1256 #ifdef CONFIG_PROC_FS
1258 proc_root_mtrr->size = ascii_buf_bytes;
1262 #endif /* USERSPACE_INTERFACE */
1264 EXPORT_SYMBOL (mtrr_add);
1265 EXPORT_SYMBOL (mtrr_del);
1268 static void __init mtrr_setup (void)
1270 printk ("mtrr: v%s)\n", MTRR_VERSION);
1272 if (test_bit (X86_FEATURE_MTRR, boot_cpu_data.x86_capability)) {
1273 /* Query the width (in bits) of the physical
1274 addressable memory. This is an AMD specific MSR,
1275 but we assume(hope?) Intel will implement it too
1276 when they extend the width of the Xeon address bus. */
1277 if (cpuid_eax (0x80000000) >= 0x80000008) {
1279 phys_addr = cpuid_eax (0x80000008) & 0xff;
1280 size_or_mask = ~((1L << (phys_addr - PAGE_SHIFT)) - 1);
1282 * top bits MBZ as its beyond the addressable range.
1283 * bottom bits MBZ as we don't care about lower 12 bits of addr.
1285 size_and_mask = ~size_or_mask & 0xfff00000;
1287 /* 36bit fallback */
1288 size_or_mask = 0xff000000;
1289 size_and_mask = 0x00f00000;
1296 static volatile u32 smp_changes_mask __initdata = 0;
1297 static struct mtrr_state smp_mtrr_state __initdata = { 0, 0 };
1299 void __init mtrr_init_boot_cpu (void)
1302 get_mtrr_state (&smp_mtrr_state);
1306 void __init mtrr_init_secondary_cpu (void)
1310 struct set_mtrr_context ctxt;
1312 /* Note that this is not ideal, since the cache is only flushed/disabled
1313 for this CPU while the MTRRs are changed, but changing this requires
1314 more invasive changes to the way the kernel boots */
1315 set_mtrr_prepare (&ctxt);
1316 set_mtrr_disable (&ctxt);
1317 mask = set_mtrr_state (&smp_mtrr_state, &ctxt);
1318 set_mtrr_done (&ctxt);
1320 /* Use the atomic bitops to update the global mask */
1321 for (count = 0; count < sizeof mask * 8; ++count) {
1323 set_bit (count, &smp_changes_mask);
1328 #endif /* CONFIG_SMP */
1331 int __init mtrr_init (void)
1334 /* mtrr_setup() should already have been called from mtrr_init_boot_cpu() */
1336 finalize_mtrr_state (&smp_mtrr_state);
1337 mtrr_state_warn (smp_changes_mask);
1342 #ifdef CONFIG_PROC_FS
1343 proc_root_mtrr = create_proc_entry ("mtrr", S_IWUSR | S_IRUGO, &proc_root);
1344 if (proc_root_mtrr) {
1345 proc_root_mtrr->owner = THIS_MODULE;
1346 proc_root_mtrr->proc_fops = &mtrr_fops;
1349 #ifdef CONFIG_DEVFS_FS
1350 devfs_handle = devfs_register (NULL, "cpu/mtrr", DEVFS_FL_DEFAULT, 0, 0,
1351 S_IFREG | S_IRUGO | S_IWUSR,