2 * Low-Level PCI Support for PC
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
5 * 2001 Andi Kleen. Cleanup for x86-64. Removed PCI-BIOS access and fixups
6 * for hardware that is unlikely to exist on any Hammer platform.
8 * On x86-64 we don't have any access to the PCI-BIOS in long mode, so we
9 * cannot sort the pci device table based on what the BIOS did. This might
10 * change the probing order of some devices compared to an i386 kernel.
11 * May need to use ACPI to fix this.
14 #include <linux/config.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/sched.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/ioport.h>
21 #include <linux/acpi.h>
23 #include <asm/segment.h>
25 #include <asm/mpspec.h>
26 #include <asm/proto.h>
28 #include "pci-x86_64.h"
30 unsigned int pci_probe = PCI_PROBE_CONF1 | PCI_PROBE_CONF2;
32 int pcibios_last_bus = -1;
33 struct pci_bus *pci_root_bus;
34 struct pci_ops *pci_root_ops;
36 int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int len, u32 *value) = NULL;
37 int (*pci_config_write)(int seg, int bus, int dev, int fn, int reg, int len, u32 value) = NULL;
39 static int pci_using_acpi_prt = 0;
41 /* XXX: not taken by all accesses currently */
42 static spinlock_t pci_config_lock = SPIN_LOCK_UNLOCKED;
45 * Direct access to PCI hardware...
48 #ifdef CONFIG_PCI_DIRECT
51 * Functions for accessing PCI configuration space with type 1 accesses
54 #define CONFIG_CMD(dev, where) (0x80000000 | (dev->bus->number << 16) | (dev->devfn << 8) | (where & ~3))
56 #define PCI_CONF1_ADDRESS(bus, dev, fn, reg) \
57 (0x80000000 | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
59 static int pci_conf1_read (int seg, int bus, int dev, int fn, int reg, int len,
64 if (!value || (bus > 255) || (dev > 31) || (fn > 7) || (reg > 255))
67 spin_lock_irqsave(&pci_config_lock, flags);
69 outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8);
73 *value = inb(0xCFC + (reg & 3));
76 *value = inw(0xCFC + (reg & 2));
83 spin_unlock_irqrestore(&pci_config_lock, flags);
88 static int pci_conf1_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value)
92 if ((bus > 255) || (dev > 31) || (fn > 7) || (reg > 255))
95 spin_lock_irqsave(&pci_config_lock, flags);
97 outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8);
101 outb((u8)value, 0xCFC + (reg & 3));
104 outw((u16)value, 0xCFC + (reg & 2));
107 outl((u32)value, 0xCFC);
111 spin_unlock_irqrestore(&pci_config_lock, flags);
116 static int pci_conf1_read_config_byte(struct pci_dev *dev, int where, u8 *value)
124 result = pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
125 PCI_FUNC(dev->devfn), where, 1, &data);
132 static int pci_conf1_read_config_word(struct pci_dev *dev, int where, u16 *value)
140 result = pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
141 PCI_FUNC(dev->devfn), where, 2, &data);
148 static int pci_conf1_read_config_dword(struct pci_dev *dev, int where, u32 *value)
150 return pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
151 PCI_FUNC(dev->devfn), where, 4, value);
155 static int pci_conf1_write_config_byte(struct pci_dev *dev, int where, u8 value)
157 return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
158 PCI_FUNC(dev->devfn), where, 1, value);
161 static int pci_conf1_write_config_word(struct pci_dev *dev, int where, u16 value)
163 return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
164 PCI_FUNC(dev->devfn), where, 2, value);
167 static int pci_conf1_write_config_dword(struct pci_dev *dev, int where, u32 value)
169 return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
170 PCI_FUNC(dev->devfn), where, 4, value);
175 static struct pci_ops pci_direct_conf1 = {
176 pci_conf1_read_config_byte,
177 pci_conf1_read_config_word,
178 pci_conf1_read_config_dword,
179 pci_conf1_write_config_byte,
180 pci_conf1_write_config_word,
181 pci_conf1_write_config_dword
185 * Functions for accessing PCI configuration space with type 2 accesses
188 #define IOADDR(devfn, where) ((0xC000 | ((devfn & 0x78) << 5)) + where)
189 #define FUNC(devfn) (((devfn & 7) << 1) | 0xf0)
190 #define SET(dev) if (dev->devfn & 0x80) return PCIBIOS_DEVICE_NOT_FOUND; \
191 outb(FUNC(dev->devfn), 0xCF8); \
192 outb(dev->bus->number, 0xCFA);
194 #define PCI_CONF2_ADDRESS(dev, reg) (u16)(0xC000 | (dev << 8) | reg)
196 static int pci_conf2_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value)
200 if (!value || (bus > 255) || (dev > 31) || (fn > 7) || (reg > 255))
204 return PCIBIOS_DEVICE_NOT_FOUND;
206 spin_lock_irqsave(&pci_config_lock, flags);
208 outb((u8)(0xF0 | (fn << 1)), 0xCF8);
209 outb((u8)bus, 0xCFA);
213 *value = inb(PCI_CONF2_ADDRESS(dev, reg));
216 *value = inw(PCI_CONF2_ADDRESS(dev, reg));
219 *value = inl(PCI_CONF2_ADDRESS(dev, reg));
225 spin_unlock_irqrestore(&pci_config_lock, flags);
230 static int pci_conf2_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value)
234 if ((bus > 255) || (dev > 31) || (fn > 7) || (reg > 255))
238 return PCIBIOS_DEVICE_NOT_FOUND;
240 spin_lock_irqsave(&pci_config_lock, flags);
242 outb((u8)(0xF0 | (fn << 1)), 0xCF8);
243 outb((u8)bus, 0xCFA);
247 outb ((u8)value, PCI_CONF2_ADDRESS(dev, reg));
250 outw ((u16)value, PCI_CONF2_ADDRESS(dev, reg));
253 outl ((u32)value, PCI_CONF2_ADDRESS(dev, reg));
259 spin_unlock_irqrestore(&pci_config_lock, flags);
264 static int pci_conf2_read_config_byte(struct pci_dev *dev, int where, u8 *value)
272 result = pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
273 PCI_FUNC(dev->devfn), where, 1, &data);
280 static int pci_conf2_read_config_word(struct pci_dev *dev, int where, u16 *value)
288 result = pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
289 PCI_FUNC(dev->devfn), where, 2, &data);
296 static int pci_conf2_read_config_dword(struct pci_dev *dev, int where, u32 *value)
298 return pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
299 PCI_FUNC(dev->devfn), where, 4, value);
302 static int pci_conf2_write_config_byte(struct pci_dev *dev, int where, u8 value)
304 return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
305 PCI_FUNC(dev->devfn), where, 1, value);
308 static int pci_conf2_write_config_word(struct pci_dev *dev, int where, u16 value)
310 return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
311 PCI_FUNC(dev->devfn), where, 2, value);
314 static int pci_conf2_write_config_dword(struct pci_dev *dev, int where, u32 value)
316 return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
317 PCI_FUNC(dev->devfn), where, 4, value);
324 static struct pci_ops pci_direct_conf2 = {
325 pci_conf2_read_config_byte,
326 pci_conf2_read_config_word,
327 pci_conf2_read_config_dword,
328 pci_conf2_write_config_byte,
329 pci_conf2_write_config_word,
330 pci_conf2_write_config_dword
334 * Before we decide to use direct hardware access mechanisms, we try to do some
335 * trivial checks to ensure it at least _seems_ to be working -- we just test
336 * whether bus 00 contains a host bridge (this is similar to checking
337 * techniques used in XFree86, but ours should be more reliable since we
338 * attempt to make use of direct access hints provided by the PCI BIOS).
340 * This should be close to trivial, but it isn't, because there are buggy
341 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
343 static int __devinit pci_sanity_check(struct pci_ops *o)
346 struct pci_bus bus; /* Fake bus and device */
349 if (pci_probe & PCI_NO_CHECKS)
353 for(dev.devfn=0; dev.devfn < 0x100; dev.devfn++)
354 if ((!o->read_word(&dev, PCI_CLASS_DEVICE, &x) &&
355 (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)) ||
356 (!o->read_word(&dev, PCI_VENDOR_ID, &x) &&
357 (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)))
359 DBG("PCI: Sanity check failed\n");
363 static struct pci_ops * __devinit pci_check_direct(void)
368 __save_flags(flags); __cli();
371 * Check if configuration type 1 works.
373 if (pci_probe & PCI_PROBE_CONF1) {
376 outl (0x80000000, 0xCF8);
377 if (inl (0xCF8) == 0x80000000 &&
378 pci_sanity_check(&pci_direct_conf1)) {
380 __restore_flags(flags);
381 printk(KERN_INFO "PCI: Using configuration type 1\n");
382 request_region(0xCF8, 8, "PCI conf1");
383 return &pci_direct_conf1;
389 * Check if configuration type 2 works.
391 if (pci_probe & PCI_PROBE_CONF2) {
395 if (inb (0xCF8) == 0x00 && inb (0xCFA) == 0x00 &&
396 pci_sanity_check(&pci_direct_conf2)) {
397 __restore_flags(flags);
398 printk(KERN_INFO "PCI: Using configuration type 2\n");
399 request_region(0xCF8, 4, "PCI conf2");
400 return &pci_direct_conf2;
404 __restore_flags(flags);
410 struct pci_bus * __devinit pcibios_scan_root(int busnum)
412 struct list_head *list;
415 list_for_each(list, &pci_root_buses) {
416 bus = pci_bus_b(list);
417 if (bus->number == busnum) {
418 /* Already scanned */
423 printk("PCI: Probing PCI hardware (bus %02x)\n", busnum);
425 return pci_scan_bus(busnum, pci_root_ops, NULL);
429 * Several buggy motherboards address only 16 devices and mirror
430 * them to next 16 IDs. We try to detect this `feature' on all
431 * primary buses (those containing host bridges as they are
432 * expected to be unique) and remove the ghost devices.
435 static void __devinit pcibios_fixup_ghosts(struct pci_bus *b)
437 struct list_head *ln, *mn;
438 struct pci_dev *d, *e;
439 int mirror = PCI_DEVFN(16,0);
440 int seen_host_bridge = 0;
443 DBG("PCI: Scanning for ghost devices on bus %d\n", b->number);
444 for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
446 if ((d->class >> 8) == PCI_CLASS_BRIDGE_HOST)
448 for (mn=ln->next; mn != &b->devices; mn=mn->next) {
450 if (e->devfn != d->devfn + mirror ||
451 e->vendor != d->vendor ||
452 e->device != d->device ||
453 e->class != d->class)
455 for(i=0; i<PCI_NUM_RESOURCES; i++)
456 if (e->resource[i].start != d->resource[i].start ||
457 e->resource[i].end != d->resource[i].end ||
458 e->resource[i].flags != d->resource[i].flags)
462 if (mn == &b->devices)
465 if (!seen_host_bridge)
467 printk(KERN_INFO "PCI: Ignoring ghost devices on bus %02x\n", b->number);
470 while (ln->next != &b->devices) {
471 d = pci_dev_b(ln->next);
472 if (d->devfn >= mirror) {
473 list_del(&d->global_list);
474 list_del(&d->bus_list);
482 * Discover remaining PCI buses in case there are peer host bridges.
484 static void __devinit pcibios_fixup_peer_bridges(void)
491 if (pcibios_last_bus <= 0 || pcibios_last_bus >= 0xff)
493 DBG("PCI: Peer bridge fixup\n");
494 for (n=0; n <= pcibios_last_bus; n++) {
495 if (pci_bus_exists(&pci_root_buses, n))
498 bus.ops = pci_root_ops;
500 for(dev.devfn=0; dev.devfn<256; dev.devfn += 8)
501 if (!pci_read_config_word(&dev, PCI_VENDOR_ID, &l) &&
502 l != 0x0000 && l != 0xffff) {
503 DBG("Found device at %02x:%02x [%04x]\n", n, dev.devfn, l);
504 printk(KERN_INFO "PCI: Discovered peer bus %02x\n", n);
505 pci_scan_bus(n, pci_root_ops, NULL);
511 static void __devinit pci_scan_mptable(void)
515 /* Handle ACPI here */
516 if (!smp_found_config) {
517 printk(KERN_WARNING "PCI: Warning: no mptable. Scanning busses upto 0xff\n");
518 pcibios_last_bus = 0xff;
522 pcibios_last_bus = 0xff;
524 for (i = 0; i < MAX_MP_BUSSES; i++) {
525 int n = mp_bus_id_to_pci_bus[i];
526 if (n < 0 || n >= 0xff)
528 if (pci_bus_exists(&pci_root_buses, n))
530 printk(KERN_INFO "PCI: Scanning bus %02x from mptable\n", n);
531 pci_scan_bus(n, pci_root_ops, NULL);
535 static void __devinit pci_fixup_ide_bases(struct pci_dev *d)
540 * PCI IDE controllers use non-standard I/O port decoding, respect it.
542 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
544 DBG("PCI: IDE base address fixup for %s\n", d->slot_name);
546 struct resource *r = &d->resource[i];
547 if ((r->start & ~0x80) == 0x374) {
554 struct pci_fixup pcibios_fixups[] = {
555 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases },
560 * Called after each bus is probed, but before its children
564 void __devinit pcibios_fixup_bus(struct pci_bus *b)
566 pcibios_fixup_ghosts(b);
567 pci_read_bridge_bases(b);
570 void __devinit pcibios_config_init(void)
573 * Try all known PCI access methods. Note that we support using
574 * both PCI BIOS and direct access, with a preference for direct.
577 #ifdef CONFIG_PCI_DIRECT
578 if ((pci_probe & (PCI_PROBE_CONF1 | PCI_PROBE_CONF2))
579 && (pci_root_ops = pci_check_direct())) {
580 if (pci_root_ops == &pci_direct_conf1) {
581 pci_config_read = pci_conf1_read;
582 pci_config_write = pci_conf1_write;
585 pci_config_read = pci_conf2_read;
586 pci_config_write = pci_conf2_write;
589 printk("??? no pci access\n");
595 void __devinit pcibios_init(void)
597 struct pci_ops *dir = NULL;
600 pcibios_config_init();
602 #ifdef CONFIG_PCI_DIRECT
603 if (pci_probe & (PCI_PROBE_CONF1 | PCI_PROBE_CONF2))
604 dir = pci_check_direct();
609 printk(KERN_INFO "PCI: No PCI bus detected\n");
613 printk(KERN_INFO "PCI: Probing PCI hardware\n");
614 #ifdef CONFIG_ACPI_PCI
615 if (!acpi_disabled && !acpi_noirq && !acpi_pci_irq_init())
616 pci_using_acpi_prt = 1;
618 if (!pci_using_acpi_prt) {
619 pci_root_bus = pcibios_scan_root(0);
622 pcibios_fixup_peer_bridges();
623 pcibios_fixup_irqs();
626 pcibios_resource_survey();
628 #ifdef CONFIG_GART_IOMMU
633 char * __devinit pcibios_setup(char *str)
635 if (!strcmp(str, "off")) {
639 else if (!strncmp(str, "bios", 4)) {
640 printk(KERN_WARNING "PCI: No PCI bios access on x86-64. BIOS hint ignored.\n");
642 } else if (!strcmp(str, "nobios")) {
643 pci_probe &= ~PCI_PROBE_BIOS;
645 } else if (!strcmp(str, "nosort")) { /* Default */
646 pci_probe |= PCI_NO_SORT;
649 #ifdef CONFIG_PCI_DIRECT
650 else if (!strcmp(str, "conf1")) {
651 pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
654 else if (!strcmp(str, "conf2")) {
655 pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
659 else if (!strcmp(str, "rom")) {
660 pci_probe |= PCI_ASSIGN_ROMS;
662 } else if (!strcmp(str, "assign-busses")) {
663 pci_probe |= PCI_ASSIGN_ALL_BUSSES;
665 } else if (!strncmp(str, "irqmask=", 8)) {
666 pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
668 } else if (!strncmp(str, "lastbus=", 8)) {
669 pcibios_last_bus = simple_strtol(str+8, NULL, 0);
671 } else if (!strncmp(str, "noacpi", 6)) {
678 unsigned int pcibios_assign_all_busses(void)
680 return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
683 int pcibios_enable_device(struct pci_dev *dev, int mask)
687 if ((err = pcibios_enable_resources(dev, mask)) < 0)
690 #ifdef CONFIG_ACPI_PCI
691 if (!acpi_noirq && pci_using_acpi_prt) {
692 acpi_pci_irq_enable(dev);
697 pcibios_enable_irq(dev);