2 #ifndef _ASM_PCI_BRIDGE_H
3 #define _ASM_PCI_BRIDGE_H
5 #include <linux/ioport.h>
12 * pci_io_base returns the memory address at which you can access
13 * the I/O space for PCI bus number `bus' (or NULL on error).
15 extern void *pci_bus_io_base(unsigned int bus);
16 extern unsigned long pci_bus_io_base_phys(unsigned int bus);
17 extern unsigned long pci_bus_mem_base_phys(unsigned int bus);
19 /* Allocate a new PCI host bridge structure */
20 extern struct pci_controller* pcibios_alloc_controller(void);
22 /* Helper function for setting up resources */
23 extern void pci_init_resource(struct resource *res, unsigned long start,
24 unsigned long end, int flags, char *name);
27 * PCI <-> OF matching functions
29 extern int pci_device_from_OF_node(struct device_node *node,
31 extern struct device_node* pci_device_to_OF_node(struct pci_dev *);
32 extern void pci_create_OF_bus_map(void);
34 /* Get the PCI host controller for a bus */
35 extern struct pci_controller* pci_bus_to_hose(int bus);
37 /* Get the PCI host controller for an OF device */
38 extern struct pci_controller*
39 pci_find_hose_for_OF_device(struct device_node* node);
41 /* Fill up host controller resources from the OF node */
43 pci_process_bridge_OF_ranges(struct pci_controller *hose,
44 struct device_node *dev, int primary);
47 * Structure of a PCI controller (host bridge)
49 struct pci_controller {
50 int index; /* used for pci_controller_num */
51 struct pci_controller *next;
60 unsigned long io_base_phys;
62 /* Some machines (PReP) have a non 1:1 mapping of
63 * the PCI memory space in the CPU bus space
65 unsigned long pci_mem_offset;
68 volatile unsigned int *cfg_addr;
69 volatile unsigned char *cfg_data;
71 * If set, indirect method will set the cfg_type bit as
72 * needed to generate type 1 configuration transactions.
76 /* Currently, we limit ourselves to 1 IO range and 3 mem
77 * ranges since the common pci_bus structure can't handle more
79 struct resource io_resource;
80 struct resource mem_resources[3];
81 int mem_resource_count;
83 /* Host bridge I/O and Memory space
84 * Used for BAR placement algorithms
86 struct resource io_space;
87 struct resource mem_space;
90 /* These are used for config access before all the PCI probing
92 int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
94 int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
96 int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
98 int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
100 int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
102 int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
105 extern void setup_indirect_pci(struct pci_controller* hose,
106 u32 cfg_addr, u32 cfg_data);
107 extern void setup_grackle(struct pci_controller *hose);
109 extern unsigned char common_swizzle(struct pci_dev *, unsigned char *);
112 * The following code swizzles for exactly one bridge. The routine
113 * common_swizzle below handles multiple bridges. But there are a
114 * some boards that don't follow the PCI spec's suggestion so we
115 * break this piece out separately.
117 static inline unsigned char bridge_swizzle(unsigned char pin,
120 return (((pin-1) + idsel) % 4) + 1;
124 * The following macro is used to lookup irqs in a standard table
125 * format for those PPC systems that do not already have PCI
126 * interrupts properly routed.
128 /* FIXME - double check this */
129 #define PCI_IRQ_TABLE_LOOKUP \
130 ({ long _ctl_ = -1; \
131 if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \
132 _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \
136 * Scan the buses below a given PCI host bridge and assign suitable
137 * resources to all devices found.
139 extern int pciauto_bus_scan(struct pci_controller *, int);
142 #endif /* __KERNEL__ */