2 * include/asm-ppc/ppc_asm.h
4 * Definitions used by various bits of low-level assembly code on PowerPC.
6 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
14 #include <linux/config.h>
17 * Macros for storing registers into and loading registers from
20 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
21 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
22 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
23 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
24 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
25 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
26 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
27 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
28 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
29 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
31 #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
32 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
33 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
34 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
35 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
36 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
37 #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
38 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
39 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
40 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
41 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
42 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
45 * Once a version of gas that understands the AltiVec instructions
46 * is freely available, we can do this the normal way... - paulus
48 #define LVX(r,a,b) .long (31<<26)+((r)<<21)+((a)<<16)+((b)<<11)+(103<<1)
49 #define STVX(r,a,b) .long (31<<26)+((r)<<21)+((a)<<16)+((b)<<11)+(231<<1)
50 #define MFVSCR(r) .long (4<<26)+((r)<<21)+(770<<1)
51 #define MTVSCR(r) .long (4<<26)+((r)<<11)+(802<<1)
52 #define DSSALL .long (0x1f<<26)+(0x10<<21)+(0x336<<1)
54 #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); STVX(n,b,base)
55 #define SAVE_2VR(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
56 #define SAVE_4VR(n,b,base) SAVE_2VR(n,b,base); SAVE_2VR(n+2,b,base)
57 #define SAVE_8VR(n,b,base) SAVE_4VR(n,b,base); SAVE_4VR(n+4,b,base)
58 #define SAVE_16VR(n,b,base) SAVE_8VR(n,b,base); SAVE_8VR(n+8,b,base)
59 #define SAVE_32VR(n,b,base) SAVE_16VR(n,b,base); SAVE_16VR(n+16,b,base)
60 #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); LVX(n,b,base)
61 #define REST_2VR(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
62 #define REST_4VR(n,b,base) REST_2VR(n,b,base); REST_2VR(n+2,b,base)
63 #define REST_8VR(n,b,base) REST_4VR(n,b,base); REST_4VR(n+4,b,base)
64 #define REST_16VR(n,b,base) REST_8VR(n,b,base); REST_8VR(n+8,b,base)
65 #define REST_32VR(n,b,base) REST_16VR(n,b,base); REST_16VR(n+16,b,base)
67 #ifdef CONFIG_PPC601_SYNC_FIX
72 END_FTR_SECTION_IFSET(CPU_FTR_601)
76 END_FTR_SECTION_IFSET(CPU_FTR_601)
80 END_FTR_SECTION_IFSET(CPU_FTR_601)
89 #else /* CONFIG_SMP */
90 /* tlbsync is not implemented on 601 */
95 END_FTR_SECTION_IFCLR(CPU_FTR_601)
99 * This instruction is not implemented on the PPC 603 or 601; however, on
100 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
101 * All of these instructions exist in the 8xx, they have magical powers,
102 * and they must be used.
105 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
109 lis r4,KERNELBASE@h; \
116 #define tophys(rd,rs) \
118 #define tovirt(rd,rs) \
120 #else /* CONFIG_BOOKE */
122 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
123 * physical base address of RAM at compile time.
125 #define tophys(rd,rs) \
126 0: addis rd,rs,-KERNELBASE@h; \
127 .section ".vtop_fixup","aw"; \
132 #define tovirt(rd,rs) \
133 0: addis rd,rs,KERNELBASE@h; \
134 .section ".ptov_fixup","aw"; \
138 #endif /* CONFIG_BOOKE */
141 * On 64-bit cpus, we use the rfid instruction instead of rfi, but
142 * we then have to make sure we preserve the top 32 bits except for
143 * the 64-bit mode bit, which we clear.
145 #ifdef CONFIG_PPC64BRIDGE
146 #define FIX_SRR1(ra, rb) \
149 clrldi ra,ra,1; /* turn off 64-bit mode */ \
151 #define RFI .long 0x4c000024 /* rfid instruction */
152 #define MTMSRD(r) .long (0x7c000164 + ((r) << 21)) /* mtmsrd */
153 #define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
156 #define FIX_SRR1(ra, rb)
160 #define RFI rfi; b . /* prevent prefetch past rfi */
162 #define MTMSRD(r) mtmsr r
164 #endif /* CONFIG_PPC64BRIDGE */
166 #define RFMCI .long 0x4c00004c /* rfmci instruction */
168 #ifdef CONFIG_IBM405_ERR77
169 #define PPC405_ERR77(ra,rb) dcbt ra, rb;
170 #define PPC405_ERR77_SYNC sync;
172 #define PPC405_ERR77(ra,rb)
173 #define PPC405_ERR77_SYNC
176 /* The boring bits... */
178 /* Condition Register Bit Fields */
190 /* General Purpose Registers (GPRs) */
226 /* Floating Point Registers (FPRs) */
294 /* some stab codes */