3 Copyright 2002 Broadcom Corp. All Rights Reserved.
5 This program is free software; you can distribute it and/or modify it
6 under the terms of the GNU General Public License (Version 2) as
7 published by the Free Software Foundation.
9 This program is distributed in the hope it will be useful, but WITHOUT
10 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 You should have received a copy of the GNU General Public License along
15 with this program; if not, write to the Free Software Foundation, Inc.,
16 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 #ifndef __BCM6348_MAP_H
21 #define __BCM6348_MAP_H
29 #define PERF_BASE 0xfffe0000
30 #define TIMR_BASE 0xfffe0200
31 #define UART_BASE 0xfffe0300
32 #define GPIO_BASE 0xfffe0400
33 #define MPI_BASE 0xfffe2000 /* MPI control registers */
34 #define USB_HOST_BASE 0xfffe1b00 /* USB host registers */
35 #define USB_HOST_NON_OHCI 0xfffe1c00 /* USB host non-OHCI registers */
37 typedef struct PerfControl {
41 #define EMAC_CLK_EN 0x0010
42 #define SAR_CLK_EN 0x0020
43 #define USBS_CLK_EN 0x0040
44 #define USBH_CLK_EN 0x0100
47 #define SOFT_RESET 0x00000001
53 #define EI_SENSE_SHFT 0
54 #define EI_STATUS_SHFT 5
55 #define EI_CLEAR_SHFT 10
56 #define EI_MASK_SHFT 15
57 #define EI_INSENS_SHFT 20
58 #define EI_LEVEL_SHFT 25
60 uint32 unused[4]; /* (18) */
61 uint32 BlockSoftReset; /* (28) */
62 #define BSR_SPI 0x00000001
63 #define BSR_EMAC 0x00000004
64 #define BSR_USBH 0x00000008
65 #define BSR_USBS 0x00000010
66 #define BSR_ADSL 0x00000020
67 #define BSR_DMAMEM 0x00000040
68 #define BSR_SAR 0x00000080
69 #define BSR_ACLC 0x00000100
70 #define BSR_ADSL_MIPS_PLL 0x00000400
71 #define BSR_ALL_BLOCKS \
72 (BSR_SPI | BSR_EMAC | BSR_USBH | BSR_USBS | BSR_ADSL | BSR_DMAMEM | \
73 BSR_SAR | BSR_ACLC | BSR_ADSL_MIPS_PLL)
74 uint32 unused2[2]; /* (2c) */
75 uint32 PllStrap; /* (34) */
76 #define PLL_N1_SHFT 20
77 #define PLL_N1_MASK (7<<PLL_N1_SHFT)
78 #define PLL_N2_SHFT 15
79 #define PLL_N2_MASK (0x1f<<PLL_N2_SHFT)
80 #define PLL_M1_REF_SHFT 12
81 #define PLL_M1_REF_MASK (7<<PLL_M1_REF_SHFT)
82 #define PLL_M2_REF_SHFT 9
83 #define PLL_M2_REF_MASK (7<<PLL_M2_REF_SHFT)
84 #define PLL_M1_CPU_SHFT 6
85 #define PLL_M1_CPU_MASK (7<<PLL_M1_CPU_SHFT)
86 #define PLL_M1_BUS_SHFT 3
87 #define PLL_M1_BUS_MASK (7<<PLL_M1_BUS_SHFT)
88 #define PLL_M2_BUS_SHFT 0
89 #define PLL_M2_BUS_MASK (7<<PLL_M2_BUS_SHFT)
92 #define PERF ((volatile PerfControl * const) PERF_BASE)
94 typedef struct Timer {
104 #define WATCHDOG 0x08
108 #define TIMERENABLE 0x80000000
109 #define RSTCNTCLR 0x40000000
113 uint32 WatchDogDefCount;
115 /* Write 0xff00 0x00ff to Start timer
116 * Write 0xee00 0x00ee to Stop and re-load default count
117 * Read from this register returns current watch dog count
121 /* Number of 40-MHz ticks for WD Reset pulse to last */
125 #define TIMER ((volatile Timer * const) TIMR_BASE)
127 typedef struct UartChannel {
130 #define BRGEN 0x80 /* Control register bit defs */
134 #define TXPARITYEN 0x08
135 #define TXPARITYEVEN 0x04
136 #define RXPARITYEN 0x02
137 #define RXPARITYEVEN 0x01
140 #define XMITBREAK 0x40
141 #define BITS5SYM 0x00
142 #define BITS6SYM 0x10
143 #define BITS7SYM 0x20
144 #define BITS8SYM 0x30
147 /* 4-LSBS represent STOP bits/char
148 * in 1/8 bit-time intervals. Zero
149 * represents 1/8 stop bit interval.
150 * Fifteen represents 2 stop bits.
153 #define RSTTXFIFOS 0x80
154 #define RSTRXFIFOS 0x40
155 /* 5-bit TimeoutCnt is in low bits of this register.
156 * This count represents the number of characters
157 * idle times before setting receive Irq when below threshold
160 /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate
163 byte txf_levl; /* Read-only fifo depth */
164 byte rxf_levl; /* Read-only fifo depth */
165 byte fifocfg; /* Upper 4-bits are TxThresh, Lower are
166 * RxThreshold. Irq can be asserted
167 * when rx fifo> thresh, txfifo<thresh
169 byte prog_out; /* Set value of DTR (Bit0), RTS (Bit1)
170 * if these bits are also enabled to GPIO_o
176 byte DeltaIPEdgeNoSense; /* Low 4-bits, set corr bit to 1 to
177 * detect irq on rising AND falling
178 * edges for corresponding GPIO_i
179 * if enabled (edge insensitive)
181 byte DeltaIPConfig_Mask; /* Upper 4 bits: 1 for posedge sense
182 * 0 for negedge sense if
183 * not configured for edge
184 * insensitive (see above)
185 * Lower 4 bits: Mask to enable change
186 * detection IRQ for corresponding
189 byte DeltaIP_SyncIP; /* Upper 4 bits show which bits
190 * have changed (may set IRQ).
191 * read automatically clears bit
192 * Lower 4 bits are actual status
195 uint16 intMask; /* Same Bit defs for Mask and status */
197 #define DELTAIP 0x0001
198 #define TXUNDERR 0x0002
199 #define TXOVFERR 0x0004
200 #define TXFIFOTHOLD 0x0008
201 #define TXREADLATCH 0x0010
202 #define TXFIFOEMT 0x0020
203 #define RXUNDERR 0x0040
204 #define RXOVFERR 0x0080
205 #define RXTIMEOUT 0x0100
206 #define RXFIFOFULL 0x0200
207 #define RXFIFOTHOLD 0x0400
208 #define RXFIFONE 0x0800
209 #define RXFRAMERR 0x1000
210 #define RXPARERR 0x2000
214 uint16 Data; /* Write to TX, Read from RX */
215 /* bits 11:8 are BRK,PAR,FRM errors */
221 #define UART ((volatile Uart * const) UART_BASE)
223 typedef struct GpioControl {
224 uint32 GPIODir_high; /* bits 36:32 */
225 uint32 GPIODir; /* bits 31:00 */
226 uint32 GPIOio_high; /* bits 36:32 */
227 uint32 GPIOio; /* bits 31:00 */
229 #define LED3_STROBE 0x08000000
230 #define LED2_STROBE 0x04000000
231 #define LED1_STROBE 0x02000000
232 #define LED0_STROBE 0x01000000
233 #define LED_TEST 0x00010000
234 #define LED3_DISABLE_LINK_ACT 0x00008000
235 #define LED2_DISABLE_LINK_ACT 0x00004000
236 #define LED1_DISABLE_LINK_ACT 0x00002000
237 #define LED0_DISABLE_LINK_ACT 0x00001000
238 #define LED_INTERVAL_SET_MASK 0x00000f00
239 #define LED_INTERVAL_SET_320MS 0x00000500
240 #define LED_INTERVAL_SET_160MS 0x00000400
241 #define LED_INTERVAL_SET_80MS 0x00000300
242 #define LED_INTERVAL_SET_40MS 0x00000200
243 #define LED_INTERVAL_SET_20MS 0x00000100
244 #define LED3_ON 0x00000080
245 #define LED2_ON 0x00000040
246 #define LED1_ON 0x00000020
247 #define LED0_ON 0x00000010
248 #define LED3_ENABLE 0x00000008
249 #define LED2_ENABLE 0x00000004
250 #define LED1_ENABLE 0x00000002
251 #define LED0_ENABLE 0x00000001
253 #define SPI_SLAVE_RESET 0x00010000
254 #define SPI_RESTRICT 0x00000400
255 #define SPI_DELAY_DISABLE 0x00000200
256 #define SPI_PROBE_MUX_SEL_MASK 0x000001e0
257 #define SPI_SER_ADDR_CFG_MASK 0x0000000c
258 #define SPI_MODE 0x00000001
260 #define GROUP4_DIAG 0x00090000
261 #define GROUP4_UTOPIA 0x00080000
262 #define GROUP4_LEGACY_LED 0x00030000
263 #define GROUP4_MII_SNOOP 0x00020000
264 #define GROUP4_EXT_EPHY 0x00010000
265 #define GROUP3_DIAG 0x00009000
266 #define GROUP3_UTOPIA 0x00008000
267 #define GROUP3_EXT_MII 0x00007000
268 #define GROUP2_DIAG 0x00000900
269 #define GROUP2_PCI 0x00000500
270 #define GROUP1_DIAG 0x00000090
271 #define GROUP1_UTOPIA 0x00000080
272 #define GROUP1_SPI_UART 0x00000060
273 #define GROUP1_SPI_MASTER 0x00000060
274 #define GROUP1_MII_PCCARD 0x00000040
275 #define GROUP1_MII_SNOOP 0x00000020
276 #define GROUP1_EXT_EPHY 0x00000010
277 #define GROUP0_DIAG 0x00000009
278 #define GROUP0_EXT_MII 0x00000007
282 #define GPIO ((volatile GpioControl * const) GPIO_BASE)
284 /* Number to mask conversion macro used for GPIODir and GPIOio */
285 #define GPIO_NUM_TOTAL_BITS_MASK 0x3f
286 #define GPIO_NUM_MAX_BITS_MASK 0x1f
287 #define GPIO_NUM_TO_MASK(X) ( (((X) & GPIO_NUM_TOTAL_BITS_MASK) < 32) ? (1 << ((X) & GPIO_NUM_MAX_BITS_MASK)) : (0) )
289 /* Number to mask conversion macro used for GPIODir_high and GPIOio_high */
290 #define GPIO_NUM_MAX_BITS_MASK_HIGH 0x07
291 #define GPIO_NUM_TO_MASK_HIGH(X) ( (((X) & GPIO_NUM_TOTAL_BITS_MASK) >= 32) ? (1 << ((X-32) & GPIO_NUM_MAX_BITS_MASK_HIGH)) : (0) )
295 ** External Bus Interface
297 typedef struct EbiChipSelect {
298 uint32 base; /* base address in upper 24 bits */
299 #define EBI_SIZE_8K 0
300 #define EBI_SIZE_16K 1
301 #define EBI_SIZE_32K 2
302 #define EBI_SIZE_64K 3
303 #define EBI_SIZE_128K 4
304 #define EBI_SIZE_256K 5
305 #define EBI_SIZE_512K 6
306 #define EBI_SIZE_1M 7
307 #define EBI_SIZE_2M 8
308 #define EBI_SIZE_4M 9
309 #define EBI_SIZE_8M 10
310 #define EBI_SIZE_16M 11
311 #define EBI_SIZE_32M 12
312 #define EBI_SIZE_64M 13
313 #define EBI_SIZE_128M 14
314 #define EBI_SIZE_256M 15
316 #define EBI_ENABLE 0x00000001 /* .. enable this range */
317 #define EBI_WAIT_STATES 0x0000000e /* .. mask for wait states */
318 #define EBI_WTST_SHIFT 1 /* .. for shifting wait states */
319 #define EBI_WORD_WIDE 0x00000010 /* .. 16-bit peripheral, else 8 */
320 #define EBI_WREN 0x00000020 /* enable posted writes */
321 #define EBI_POLARITY 0x00000040 /* .. set to invert something,
322 ** don't know what yet */
323 #define EBI_TS_TA_MODE 0x00000080 /* .. use TS/TA mode */
324 #define EBI_TS_SEL 0x00000100 /* .. drive tsize, not bs_b */
325 #define EBI_FIFO 0x00000200 /* .. use fifo */
326 #define EBI_RE 0x00000400 /* .. Reverse Endian */
329 typedef struct MpiRegisters {
330 EbiChipSelect cs[7]; /* size chip select configuration */
331 #define EBI_CS0_BASE 0
332 #define EBI_CS1_BASE 1
333 #define EBI_CS2_BASE 2
334 #define EBI_CS3_BASE 3
335 #define PCMCIA_COMMON_BASE 4
336 #define PCMCIA_ATTRIBUTE_BASE 5
337 #define PCMCIA_IO_BASE 6
338 uint32 unused0[2]; /* reserved */
339 uint32 ebi_control; /* ebi control */
340 uint32 unused1[4]; /* reserved */
341 #define EBI_ACCESS_TIMEOUT 0x000007FF
342 uint32 pcmcia_cntl1; /* pcmcia control 1 */
343 #define PCCARD_CARD_RESET 0x00040000
344 #define CARDBUS_ENABLE 0x00008000
345 #define PCMCIA_ENABLE 0x00004000
346 #define PCMCIA_GPIO_ENABLE 0x00002000
347 #define CARDBUS_IDSEL 0x00001F00
348 #define VS2_OEN 0x00000080
349 #define VS1_OEN 0x00000040
350 #define VS2_OUT 0x00000020
351 #define VS1_OUT 0x00000010
352 #define VS2_IN 0x00000008
353 #define VS1_IN 0x00000004
354 #define CD2_IN 0x00000002
355 #define CD1_IN 0x00000001
356 #define VS_MASK 0x0000000C
357 #define CD_MASK 0x00000003
358 uint32 unused2; /* reserved */
359 uint32 pcmcia_cntl2; /* pcmcia control 2 */
360 #define PCMCIA_BYTESWAP_DIS 0x00000002
361 #define PCMCIA_HALFWORD_EN 0x00000001
362 #define RW_ACTIVE_CNT_BIT 2
363 #define INACTIVE_CNT_BIT 8
364 #define CE_SETUP_CNT_BIT 16
365 #define CE_HOLD_CNT_BIT 24
366 uint32 unused3[40]; /* reserved */
368 uint32 sp0range; /* PCI to internal system bus address space */
377 uint32 l2pcfgctl; /* internal system bus to PCI IO/Cfg control */
378 #define DIR_CFG_SEL 0x80000000 /* change from PCI I/O access to PCI config access */
379 #define DIR_CFG_USEREG 0x40000000 /* use this register info for PCI configuration access */
380 #define DEVICE_NUMBER 0x00007C00 /* device number for the PCI configuration access */
381 #define FUNC_NUMBER 0x00000300 /* function number for the PCI configuration access */
382 #define REG_NUMBER 0x000000FC /* register number for the PCI configuration access */
383 #define CONFIG_TYPE 0x00000003 /* configuration type for the PCI configuration access */
385 uint32 l2pmrange1; /* internal system bus to PCI memory space */
386 #define PCI_SIZE_64K 0xFFFF0000
387 #define PCI_SIZE_128K 0xFFFE0000
388 #define PCI_SIZE_256K 0xFFFC0000
389 #define PCI_SIZE_512K 0xFFF80000
390 #define PCI_SIZE_1M 0xFFF00000
391 #define PCI_SIZE_2M 0xFFE00000
392 #define PCI_SIZE_4M 0xFFC00000
393 #define PCI_SIZE_8M 0xFF800000
394 #define PCI_SIZE_16M 0xFF000000
395 #define PCI_SIZE_32M 0xFE000000
396 uint32 l2pmbase1; /* kseg0 or kseg1 address & 0x1FFFFFFF */
398 #define CARDBUS_MEM 0x00000004
399 #define MEM_WINDOW_EN 0x00000001
403 uint32 l2piorange; /* internal system bus to PCI I/O space */
408 #define PCI2_INT_BUS_RD_PREFECH 0x000000F0
409 #define PCI_BAR2_NOSWAP 0x00000002 /* BAR at offset 0x20 */
410 #define PCI_BAR1_NOSWAP 0x00000001 /* BAR at affset 0x1c */
412 uint32 pciintstat; /* PCI interrupt mask/status */
413 #define MAILBOX1_SENT 0x08
414 #define MAILBOX0_SENT 0x04
415 #define MAILBOX1_MSG_RCV 0x02
416 #define MAILBOX0_MSG_RCV 0x01
417 uint32 locbuscntrl; /* internal system bus control */
418 #define DIR_U2P_NOSWAP 0x00000002
419 #define EN_PCI_GPIO 0x00000001
420 uint32 locintstat; /* internal system bus interrupt mask/status */
423 #define EXT_PCI_INT 0x0080
424 #define DIR_FAILED 0x0040
425 #define DIR_COMPLETE 0x0020
426 #define PCI_CFG 0x0010
432 uint32 pcicfgcntrl; /* internal system bus PCI configuration control */
433 #define PCI_CFG_REG_WRITE_EN 0x00000080
434 #define PCI_CFG_ADDR 0x0000003C
435 uint32 pcicfgdata; /* internal system bus PCI configuration data */
437 uint32 locch2ctl; /* PCI to interrnal system bus DMA (downstream) local control */
438 #define MPI_DMA_HALT 0x00000008 /* idle after finish current memory burst */
439 #define MPI_DMA_PKT_HALT 0x00000004 /* idle after an EOP flag is detected */
440 #define MPI_DMA_STALL 0x00000002 /* idle after an EOP flag is detected */
441 #define MPI_DMA_ENABLE 0x00000001 /* set to enable channel */
442 uint32 locch2intStat;
443 #define MPI_DMA_NO_DESC 0x00000004 /* no valid descriptors */
444 #define MPI_DMA_DONE 0x00000002 /* packet xfer complete */
445 #define MPI_DMA_BUFF_DONE 0x00000001 /* buffer done */
446 uint32 locch2intMask;
448 uint32 locch2descaddr;
449 uint32 locch2status1;
450 #define LOCAL_DESC_STATE 0xE0000000
451 #define PCI_DESC_STATE 0x1C000000
452 #define BYTE_DONE 0x03FFC000
453 #define RING_ADDR 0x00003FFF
454 uint32 locch2status2;
455 #define BUFPTR_OFFSET 0x1FFF0000
456 #define PCI_MASTER_STATE 0x000000C0
457 #define LOC_MASTER_STATE 0x00000038
458 #define CONTROL_STATE 0x00000007
461 uint32 locch1Ctl; /*internal system bus to PCI DMA (upstream) local control */
462 #define DMA_U2P_LE 0x00000200 /* local bus is little endian */
463 #define DMA_U2P_NOSWAP 0x00000100 /* lccal bus is little endian but no data swapped */
464 uint32 locch1intstat;
465 uint32 locch1intmask;
467 uint32 locch1descaddr;
468 uint32 locch1status1;
469 uint32 locch1status2;
472 uint32 pcich1ctl; /* internal system bus to PCI DMA PCI control */
473 uint32 pcich1intstat;
474 uint32 pcich1intmask;
475 uint32 pcich1descaddr;
476 uint32 pcich1status1;
477 uint32 pcich1status2;
479 uint32 pcich2Ctl; /* PCI to internal system bus DMA PCI control */
480 uint32 pcich2intstat;
481 uint32 pcich2intmask;
482 uint32 pcich2descaddr;
483 uint32 pcich2status1;
484 uint32 pcich2status2;
486 uint32 perm_id; /* permanent device and vendor id */
487 uint32 perm_rev; /* permanent revision id */
490 #define MPI ((volatile MpiRegisters * const) MPI_BASE)
492 /* PCI configuration address space start offset 0x40 */
493 #define BRCM_PCI_CONFIG_TIMER 0x40
494 #define BRCM_PCI_CONFIG_TIMER_RETRY_MASK 0x0000FF00
495 #define BRCM_PCI_CONFIG_TIMER_TRDY_MASK 0x000000FF
497 /* USB host non-Open HCI register, USB_HOST_NON_OHCI, bit definitions. */
498 #define NON_OHCI_ENABLE_PORT1 0x00000001 /* Use USB port 1 for host, not dev */
499 #define NON_OHCI_BYTE_SWAP 0x00000008 /* Swap USB host registers */
501 #define USBH_NON_OHCI ((volatile unsigned long * const) USB_HOST_NON_OHCI)