1 /******************************************************************************
3 * Name: actbl2.h - ACPI Specification Revision 2.0 Tables
6 *****************************************************************************/
9 * Copyright (C) 2000, 2001 R. Byron Moore
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 * Prefered Power Management Profiles
32 #define PM_UNSPECIFIED 0
35 #define PM_WORKSTATION 3
36 #define PM_ENTERPRISE_SERVER 4
37 #define PM_SOHO_SERVER 5
38 #define PM_APPLIANCE_PC 6
41 * ACPI Boot Arch Flags
43 #define BAF_LEGACY_DEVICES 0x0001
44 #define BAF_8042_KEYBOARD_CONTROLLER 0x0002
46 #define FADT2_REVISION_ID 3
52 * ACPI Specification Rev 2.0 for the Root System Description Table
56 acpi_table_header header; /* Table header */
57 u32 table_offset_entry [1]; /* Array of pointers to */
58 /* other tables' headers */
59 } RSDT_DESCRIPTOR_REV2;
63 * ACPI Specification Rev 2.0 for the Extended System Description Table (XSDT)
67 acpi_table_header header; /* Table header */
68 u64 table_offset_entry [1]; /* Array of pointers to */
69 /* other tables' headers */
70 } XSDT_DESCRIPTOR_REV2;
74 * ACPI Specification Rev 2.0 for the Firmware ACPI Control Structure
78 NATIVE_CHAR signature[4]; /* signature "FACS" */
79 u32 length; /* length of structure, in bytes */
80 u32 hardware_signature; /* hardware configuration signature */
81 u32 firmware_waking_vector; /* 32bit physical address of the Firmware Waking Vector. */
82 u32 global_lock; /* Global Lock used to synchronize access to shared hardware resources */
83 u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
84 u32 reserved1 : 31; /* must be 0 */
85 u64 Xfirmware_waking_vector; /* 64bit physical address of the Firmware Waking Vector. */
86 u8 version; /* Version of this table */
87 u8 reserved3 [31]; /* reserved - must be zero */
89 } facs_descriptor_rev2;
93 * ACPI Specification Rev 2.0 for the Generic Address Structure (GAS)
97 u8 address_space_id; /* Address space where struct or register exists. */
98 u8 register_bit_width; /* Size in bits of given register */
99 u8 register_bit_offset; /* Bit offset within the register */
100 u8 reserved; /* Must be 0 */
101 u64 address; /* 64-bit address of struct or register */
103 } acpi_generic_address;
107 * ACPI Specification Rev 2.0 for the Fixed ACPI Description Table
111 acpi_table_header header; /* table header */
112 u32 V1_firmware_ctrl; /* 32-bit physical address of FACS */
113 u32 V1_dsdt; /* 32-bit physical address of DSDT */
114 u8 reserved1; /* System Interrupt Model isn't used in ACPI 2.0*/
115 u8 prefer_PM_profile; /* Conveys preferred power management profile to OSPM. */
116 u16 sci_int; /* System vector of SCI interrupt */
117 u32 smi_cmd; /* Port address of SMI command port */
118 u8 acpi_enable; /* value to write to smi_cmd to enable ACPI */
119 u8 acpi_disable; /* value to write to smi_cmd to disable ACPI */
120 u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
121 u8 pstate_cnt; /* processor performance state control*/
122 u32 V1_pm1a_evt_blk; /* Port address of Power Mgt 1a Acpi_event Reg Blk */
123 u32 V1_pm1b_evt_blk; /* Port address of Power Mgt 1b Acpi_event Reg Blk */
124 u32 V1_pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
125 u32 V1_pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
126 u32 V1_pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
127 u32 V1_pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
128 u32 V1_gpe0blk; /* Port addr of General Purpose Acpi_event 0 Reg Blk */
129 u32 V1_gpe1_blk; /* Port addr of General Purpose Acpi_event 1 Reg Blk */
130 u8 pm1_evt_len; /* Byte Length of ports at pm1_x_evt_blk */
131 u8 pm1_cnt_len; /* Byte Length of ports at pm1_x_cnt_blk */
132 u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
133 u8 pm_tm_len; /* Byte Length of ports at pm_tm_blk */
134 u8 gpe0blk_len; /* Byte Length of ports at gpe0_blk */
135 u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
136 u8 gpe1_base; /* offset in gpe model where gpe1 events start */
137 u8 cst_cnt; /* Support for the _CST object and C States change notification.*/
138 u16 plvl2_lat; /* worst case HW latency to enter/exit C2 state */
139 u16 plvl3_lat; /* worst case HW latency to enter/exit C3 state */
140 u16 flush_size; /* number of flush strides that need to be read */
141 u16 flush_stride; /* Processor's memory cache line width, in bytes */
142 u8 duty_offset; /* Processor_
\92s duty cycle index in processor's P_CNT reg*/
143 u8 duty_width; /* Processor_
\92s duty cycle value bit width in P_CNT register.*/
144 u8 day_alrm; /* index to day-of-month alarm in RTC CMOS RAM */
145 u8 mon_alrm; /* index to month-of-year alarm in RTC CMOS RAM */
146 u8 century; /* index to century in RTC CMOS RAM */
147 u16 iapc_boot_arch; /* IA-PC Boot Architecture Flags. See Table 5-10 for description*/
148 u8 reserved2; /* reserved */
149 u32 wb_invd : 1; /* wbinvd instruction works properly */
150 u32 wb_invd_flush : 1; /* wbinvd flushes but does not invalidate */
151 u32 proc_c1 : 1; /* all processors support C1 state */
152 u32 plvl2_up : 1; /* C2 state works on MP system */
153 u32 pwr_button : 1; /* Power button is handled as a generic feature */
154 u32 sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
155 u32 fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
156 u32 rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
157 u32 tmr_val_ext : 1; /* tmr_val is 32 bits */
158 u32 dock_cap : 1; /* Supports Docking */
159 u32 reset_reg_sup : 1; /* Indicates system supports system reset via the FADT RESET_REG*/
160 u32 sealed_case : 1; /* Indicates system has no internal expansion capabilities and case is sealed. */
161 u32 headless : 1; /* Indicates system does not have local video capabilities or local input devices.*/
162 u32 cpu_sw_sleep : 1; /* Indicates to OSPM that a processor native instruction */
163 /* must be executed after writing the SLP_TYPx register. */
164 u32 reserved6 : 18; /* reserved - must be zero */
166 acpi_generic_address reset_register; /* Reset register address in GAS format */
167 u8 reset_value; /* Value to write to the Reset_register port to reset the system. */
168 u8 reserved7[3]; /* These three bytes must be zero */
169 u64 Xfirmware_ctrl; /* 64-bit physical address of FACS */
170 u64 Xdsdt; /* 64-bit physical address of DSDT */
171 acpi_generic_address Xpm1a_evt_blk; /* Extended Power Mgt 1a Acpi_event Reg Blk address */
172 acpi_generic_address Xpm1b_evt_blk; /* Extended Power Mgt 1b Acpi_event Reg Blk address */
173 acpi_generic_address Xpm1a_cnt_blk; /* Extended Power Mgt 1a Control Reg Blk address */
174 acpi_generic_address Xpm1b_cnt_blk; /* Extended Power Mgt 1b Control Reg Blk address */
175 acpi_generic_address Xpm2_cnt_blk; /* Extended Power Mgt 2 Control Reg Blk address */
176 acpi_generic_address Xpm_tmr_blk; /* Extended Power Mgt Timer Ctrl Reg Blk address */
177 acpi_generic_address Xgpe0blk; /* Extended General Purpose Acpi_event 0 Reg Blk address */
178 acpi_generic_address Xgpe1_blk; /* Extended General Purpose Acpi_event 1 Reg Blk address */
180 } fadt_descriptor_rev2;
185 #endif /* __ACTBL2_H__ */