1 /******************************************************************************
3 * Name: actbl71.h - IA-64 Extensions to the ACPI Spec Rev. 0.71
4 * This file includes tables specific to this
5 * specification revision.
8 *****************************************************************************/
11 * Copyright (C) 2000, 2001 R. Byron Moore
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 /* 0.71 FADT Address_space data item bitmasks defines */
33 /* If the associated bit is zero then it is in memory space else in io space */
35 #define SMI_CMD_ADDRESS_SPACE 0x01
36 #define PM1_BLK_ADDRESS_SPACE 0x02
37 #define PM2_CNT_BLK_ADDRESS_SPACE 0x04
38 #define PM_TMR_BLK_ADDRESS_SPACE 0x08
39 #define GPE0_BLK_ADDRESS_SPACE 0x10
40 #define GPE1_BLK_ADDRESS_SPACE 0x20
42 /* Only for clarity in declarations */
44 typedef u64 IO_ADDRESS;
48 typedef struct /* Root System Descriptor Pointer */
50 NATIVE_CHAR signature [8]; /* contains "RSD PTR " */
51 u8 checksum; /* to make sum of struct == 0 */
52 NATIVE_CHAR oem_id [6]; /* OEM identification */
53 u8 reserved; /* Must be 0 for 1.0, 2 for 2.0 */
54 u64 rsdt_physical_address; /* 64-bit physical address of RSDT */
55 } RSDP_DESCRIPTOR_REV071;
58 /*****************************************/
59 /* IA64 Extensions to ACPI Spec Rev 0.71 */
60 /* for the Root System Description Table */
61 /*****************************************/
64 acpi_table_header header; /* Table header */
65 u32 reserved_pad; /* IA64 alignment, must be 0 */
66 u64 table_offset_entry [1]; /* Array of pointers to other */
68 } RSDT_DESCRIPTOR_REV071;
71 /*******************************************/
72 /* IA64 Extensions to ACPI Spec Rev 0.71 */
73 /* for the Firmware ACPI Control Structure */
74 /*******************************************/
77 NATIVE_CHAR signature[4]; /* signature "FACS" */
78 u32 length; /* length of structure, in bytes */
79 u32 hardware_signature; /* hardware configuration signature */
80 u32 reserved4; /* must be 0 */
81 u64 firmware_waking_vector; /* ACPI OS waking vector */
82 u64 global_lock; /* Global Lock */
83 u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
84 u32 reserved1 : 31; /* must be 0 */
85 u8 reserved3 [28]; /* reserved - must be zero */
87 } facs_descriptor_rev071;
90 /******************************************/
91 /* IA64 Extensions to ACPI Spec Rev 0.71 */
92 /* for the Fixed ACPI Description Table */
93 /******************************************/
96 acpi_table_header header; /* table header */
97 u32 reserved_pad; /* IA64 alignment, must be 0 */
98 u64 firmware_ctrl; /* 64-bit Physical address of FACS */
99 u64 dsdt; /* 64-bit Physical address of DSDT */
100 u8 model; /* System Interrupt Model */
101 u8 address_space; /* Address Space Bitmask */
102 u16 sci_int; /* System vector of SCI interrupt */
103 u8 acpi_enable; /* value to write to smi_cmd to enable ACPI */
104 u8 acpi_disable; /* value to write to smi_cmd to disable ACPI */
105 u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
106 u8 reserved2; /* reserved - must be zero */
107 u64 smi_cmd; /* Port address of SMI command port */
108 u64 pm1a_evt_blk; /* Port address of Power Mgt 1a Acpi_event Reg Blk */
109 u64 pm1b_evt_blk; /* Port address of Power Mgt 1b Acpi_event Reg Blk */
110 u64 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
111 u64 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
112 u64 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
113 u64 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
114 u64 gpe0blk; /* Port addr of General Purpose Acpi_event 0 Reg Blk */
115 u64 gpe1_blk; /* Port addr of General Purpose Acpi_event 1 Reg Blk */
116 u8 pm1_evt_len; /* Byte Length of ports at pm1_x_evt_blk */
117 u8 pm1_cnt_len; /* Byte Length of ports at pm1_x_cnt_blk */
118 u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
119 u8 pm_tm_len; /* Byte Length of ports at pm_tm_blk */
120 u8 gpe0blk_len; /* Byte Length of ports at gpe0_blk */
121 u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
122 u8 gpe1_base; /* offset in gpe model where gpe1 events start */
123 u8 reserved3; /* reserved */
124 u16 plvl2_lat; /* worst case HW latency to enter/exit C2 state */
125 u16 plvl3_lat; /* worst case HW latency to enter/exit C3 state */
126 u8 day_alrm; /* index to day-of-month alarm in RTC CMOS RAM */
127 u8 mon_alrm; /* index to month-of-year alarm in RTC CMOS RAM */
128 u8 century; /* index to century in RTC CMOS RAM */
129 u8 reserved4; /* reserved */
130 u32 flush_cash : 1; /* PAL_FLUSH_CACHE is correctly supported */
131 u32 reserved5 : 1; /* reserved - must be zero */
132 u32 proc_c1 : 1; /* all processors support C1 state */
133 u32 plvl2_up : 1; /* C2 state works on MP system */
134 u32 pwr_button : 1; /* Power button is handled as a generic feature */
135 u32 sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
136 u32 fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
137 u32 rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
138 u32 tmr_val_ext : 1; /* tmr_val is 32 bits */
139 u32 dock_cap : 1; /* Supports Docking */
140 u32 reserved6 : 22; /* reserved - must be zero */
142 } fadt_descriptor_rev071;
146 #endif /* __ACTBL71_H__ */