2 Madge Horizon ATM Adapter driver.
3 Copyright (C) 1995-1999 Madge Networks Ltd.
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian
20 system and in the file COPYING in the Linux kernel source.
24 IMPORTANT NOTE: Madge Networks no longer makes the adapters
25 supported by this driver and makes no commitment to maintain it.
28 #include <linux/module.h>
29 #include <linux/kernel.h>
31 #include <linux/pci.h>
32 #include <linux/errno.h>
33 #include <linux/atm.h>
34 #include <linux/atmdev.h>
35 #include <linux/sonet.h>
36 #include <linux/skbuff.h>
37 #include <linux/time.h>
38 #include <linux/delay.h>
39 #include <linux/uio.h>
40 #include <linux/init.h>
41 #include <linux/ioport.h>
43 #include <asm/system.h>
45 #include <asm/atomic.h>
46 #include <asm/uaccess.h>
47 #include <asm/string.h>
48 #include <asm/byteorder.h>
52 #define maintainer_string "Giuliano Procida at Madge Networks <gprocida@madge.com>"
53 #define description_string "Madge ATM Horizon [Ultra] driver"
54 #define version_string "1.2.1"
56 static inline void __init show_version (void) {
57 printk ("%s version %s\n", description_string, version_string);
64 Driver and documentation by:
66 Chris Aston Madge Networks
67 Giuliano Procida Madge Networks
68 Simon Benham Madge Networks
69 Simon Johnson Madge Networks
70 Various Others Madge Networks
72 Some inspiration taken from other drivers by:
75 Kari Mettinen University of Helsinki
76 Werner Almesberger EPFL LRC
80 I Hardware, detection, initialisation and shutdown.
84 This driver should handle all variants of the PCI Madge ATM adapters
85 with the Horizon chipset. These are all PCI cards supporting PIO, BM
86 DMA and a form of MMIO (registers only, not internal RAM).
88 The driver is only known to work with SONET and UTP Horizon Ultra
89 cards at 155Mb/s. However, code is in place to deal with both the
90 original Horizon and 25Mb/s operation.
92 There are two revisions of the Horizon ASIC: the original and the
93 Ultra. Details of hardware bugs are in section III.
95 The ASIC version can be distinguished by chip markings but is NOT
96 indicated by the PCI revision (all adapters seem to have PCI rev 1).
100 Horizon => Collage 25 PCI Adapter (UTP and STP)
101 Horizon Ultra => Collage 155 PCI Client (UTP or SONET)
102 Ambassador x => Collage 155 PCI Server (completely different)
104 Horizon (25Mb/s) is fitted with UTP and STP connectors. It seems to
105 have a Madge B154 plus glue logic serializer. I have also found a
106 really ancient version of this with slightly different glue. It
107 comes with the revision 0 (140-025-01) ASIC.
109 Horizon Ultra (155Mb/s) is fitted with either a Pulse Medialink
110 output (UTP) or an HP HFBR 5205 output (SONET). It has either
111 Madge's SAMBA framer or a SUNI-lite device (early versions). It
112 comes with the revision 1 (140-027-01) ASIC.
116 All Horizon-based cards present with the same PCI Vendor and Device
117 IDs. The standard Linux 2.2 PCI API is used to locate any cards and
118 to enable bus-mastering (with appropriate latency).
120 ATM_LAYER_STATUS in the control register distinguishes between the
121 two possible physical layers (25 and 155). It is not clear whether
122 the 155 cards can also operate at 25Mbps. We rely on the fact that a
123 card operates at 155 if and only if it has the newer Horizon Ultra
126 For 155 cards the two possible framers are probed for and then set
131 The card is reset and then put into a known state. The physical
132 layer is configured for normal operation at the appropriate speed;
133 in the case of the 155 cards, the framer is initialised with
134 line-based timing; the internal RAM is zeroed and the allocation of
135 buffers for RX and TX is made; the Burnt In Address is read and
136 copied to the ATM ESI; various policy settings for RX (VPI bits,
137 unknown VCs, oam cells) are made. Ideally all policy items should be
138 configurable at module load (if not actually on-demand), however,
139 only the vpi vs vci bit allocation can be specified at insmod.
143 This is in response to module_cleaup. No VCs are in use and the card
144 should be idle; it is reset.
146 II Driver software (as it should be)
148 0. Traffic Parameters
150 The traffic classes (not an enumeration) are currently: ATM_NONE (no
151 traffic), ATM_UBR, ATM_CBR, ATM_VBR and ATM_ABR, ATM_ANYCLASS
152 (compatible with everything). Together with (perhaps only some of)
153 the following items they make up the traffic specification.
156 unsigned char traffic_class; traffic class (ATM_UBR, ...)
157 int max_pcr; maximum PCR in cells per second
158 int pcr; desired PCR in cells per second
159 int min_pcr; minimum PCR in cells per second
160 int max_cdv; maximum CDV in microseconds
161 int max_sdu; maximum SDU in bytes
164 Note that these denote bandwidth available not bandwidth used; the
165 possibilities according to ATMF are:
167 Real Time (cdv and max CDT given)
169 CBR(pcr) pcr bandwidth always available
170 rtVBR(pcr,scr,mbs) scr bandwidth always available, upto pcr at mbs too
174 nrtVBR(pcr,scr,mbs) scr bandwidth always available, upto pcr at mbs too
176 ABR(mcr,pcr) mcr bandwidth always available, upto pcr (depending) too
178 mbs is max burst size (bucket)
179 pcr and scr have associated cdvt values
180 mcr is like scr but has no cdtv
181 cdtv may differ at each hop
183 Some of the above items are qos items (as opposed to traffic
184 parameters). We have nothing to do with qos. All except ABR can have
185 their traffic parameters converted to GCRA parameters. The GCRA may
186 be implemented as a (real-number) leaky bucket. The GCRA can be used
187 in complicated ways by switches and in simpler ways by end-stations.
188 It can be used both to filter incoming cells and shape out-going
191 ATM Linux actually supports:
193 ATM_NONE() (no traffic in this direction)
194 ATM_UBR(max_frame_size)
195 ATM_CBR(max/min_pcr, max_cdv, max_frame_size)
197 0 or ATM_MAX_PCR are used to indicate maximum available PCR
199 A traffic specification consists of the AAL type and separate
200 traffic specifications for either direction. In ATM Linux it is:
203 struct atm_trafprm txtp;
204 struct atm_trafprm rxtp;
210 ATM_NO_AAL AAL not specified
211 ATM_AAL0 "raw" ATM cells
214 ATM_AAL34 AAL3/4 (data)
216 ATM_SAAL signaling AAL
218 The Horizon has support for AAL frame types: 0, 3/4 and 5. However,
219 it does not implement AAL 3/4 SAR and it has a different notion of
220 "raw cell" to ATM Linux's (48 bytes vs. 52 bytes) so neither are
221 supported by this driver.
223 The Horizon has limited support for ABR (including UBR), VBR and
224 CBR. Each TX channel has a bucket (containing up to 31 cell units)
225 and two timers (PCR and SCR) associated with it that can be used to
226 govern cell emissions and host notification (in the case of ABR this
227 is presumably so that RM cells may be emitted at appropriate times).
228 The timers may either be disabled or may be set to any of 240 values
229 (determined by the clock crystal, a fixed (?) per-device divider, a
230 configurable divider and a configurable timer preload value).
232 At the moment only UBR and CBR are supported by the driver. VBR will
233 be supported as soon as ATM for Linux supports it. ABR support is
234 very unlikely as RM cell handling is completely up to the driver.
236 1. TX (TX channel setup and TX transfer)
238 The TX half of the driver owns the TX Horizon registers. The TX
239 component in the IRQ handler is the BM completion handler. This can
240 only be entered when tx_busy is true (enforced by hardware). The
241 other TX component can only be entered when tx_busy is false
242 (enforced by driver). So TX is single-threaded.
244 Apart from a minor optimisation to not re-select the last channel,
245 the TX send component works as follows:
247 Atomic test and set tx_busy until we succeed; we should implement
248 some sort of timeout so that tx_busy will never be stuck at true.
250 If no TX channel is set up for this VC we wait for an idle one (if
251 necessary) and set it up.
253 At this point we have a TX channel ready for use. We wait for enough
254 buffers to become available then start a TX transmit (set the TX
255 descriptor, schedule transfer, exit).
257 The IRQ component handles TX completion (stats, free buffer, tx_busy
258 unset, exit). We also re-schedule further transfers for the same
261 TX setup in more detail:
263 TX open is a nop, the relevant information is held in the hrz_vcc
264 (vcc->dev_data) structure and is "cached" on the card.
266 TX close gets the TX lock and clears the channel from the "cache".
268 2. RX (Data Available and RX transfer)
270 The RX half of the driver owns the RX registers. There are two RX
271 components in the IRQ handler: the data available handler deals with
272 fresh data that has arrived on the card, the BM completion handler
273 is very similar to the TX completion handler. The data available
274 handler grabs the rx_lock and it is only released once the data has
275 been discarded or completely transferred to the host. The BM
276 completion handler only runs when the lock is held; the data
277 available handler is locked out over the same period.
279 Data available on the card triggers an interrupt. If the data is not
280 suitable for our existing RX channels or we cannot allocate a buffer
281 it is flushed. Otherwise an RX receive is scheduled. Multiple RX
282 transfers may be scheduled for the same frame.
284 RX setup in more detail:
291 0. Byte vs Word addressing of adapter RAM.
293 A design feature; see the .h file (especially the memory map).
295 1. Bus Master Data Transfers (original Horizon only, fixed in Ultra)
297 The host must not start a transmit direction transfer at a
298 non-four-byte boundary in host memory. Instead the host should
299 perform a byte, or a two byte, or one byte followed by two byte
300 transfer in order to start the rest of the transfer on a four byte
303 Simultaneous transmit and receive direction bus master transfers are
306 The simplest solution to these two is to always do PIO (never DMA)
307 in the TX direction on the original Horizon. More complicated
308 solutions are likely to hurt my brain.
310 2. Loss of buffer on close VC
312 When a VC is being closed, the buffer associated with it is not
313 returned to the pool. The host must store the reference to this
314 buffer and when opening a new VC then give it to that new VC.
316 The host intervention currently consists of stacking such a buffer
317 pointer at VC close and checking the stack at VC open.
319 3. Failure to close a VC
321 If a VC is currently receiving a frame then closing the VC may fail
322 and the frame continues to be received.
324 The solution is to make sure any received frames are flushed when
325 ready. This is currently done just before the solution to 2.
327 4. PCI bus (original Horizon only, fixed in Ultra)
329 Reading from the data port prior to initialisation will hang the PCI
330 bus. Just don't do that then! We don't.
334 . Timer code may be broken.
336 . Allow users to specify buffer allocation split for TX and RX.
338 . Deal once and for all with buggy VC close.
340 . Handle interrupted and/or non-blocking operations.
342 . Change some macros to functions and move from .h to .c.
344 . Try to limit the number of TX frames each VC may have queued, in
345 order to reduce the chances of TX buffer exhaustion.
347 . Implement VBR (bucket and timers not understood) and ABR (need to
348 do RM cells manually); also no Linux support for either.
350 . Implement QoS changes on open VCs (involves extracting parts of VC open
351 and close into separate functions and using them to make changes).
355 /********** globals **********/
357 static hrz_dev * hrz_devs = NULL;
358 static struct timer_list housekeeping;
360 static unsigned short debug = 0;
361 static unsigned short vpi_bits = 0;
362 static int max_tx_size = 9000;
363 static int max_rx_size = 9000;
364 static unsigned char pci_lat = 0;
366 /********** access functions **********/
368 /* Read / Write Horizon registers */
369 static inline void wr_regl (const hrz_dev * dev, unsigned char reg, u32 data) {
370 outl (cpu_to_le32 (data), dev->iobase + reg);
373 static inline u32 rd_regl (const hrz_dev * dev, unsigned char reg) {
374 return le32_to_cpu (inl (dev->iobase + reg));
377 static inline void wr_regw (const hrz_dev * dev, unsigned char reg, u16 data) {
378 outw (cpu_to_le16 (data), dev->iobase + reg);
381 static inline u16 rd_regw (const hrz_dev * dev, unsigned char reg) {
382 return le16_to_cpu (inw (dev->iobase + reg));
385 static inline void wrs_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) {
386 outsb (dev->iobase + reg, addr, len);
389 static inline void rds_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) {
390 insb (dev->iobase + reg, addr, len);
393 /* Read / Write to a given address in Horizon buffer memory.
394 Interrupts must be disabled between the address register and data
395 port accesses as these must form an atomic operation. */
396 static inline void wr_mem (const hrz_dev * dev, HDW * addr, u32 data) {
397 // wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr);
398 wr_regl (dev, MEM_WR_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW));
399 wr_regl (dev, MEMORY_PORT_OFF, data);
402 static inline u32 rd_mem (const hrz_dev * dev, HDW * addr) {
403 // wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr);
404 wr_regl (dev, MEM_RD_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW));
405 return rd_regl (dev, MEMORY_PORT_OFF);
408 static inline void wr_framer (const hrz_dev * dev, u32 addr, u32 data) {
409 wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr | 0x80000000);
410 wr_regl (dev, MEMORY_PORT_OFF, data);
413 static inline u32 rd_framer (const hrz_dev * dev, u32 addr) {
414 wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr | 0x80000000);
415 return rd_regl (dev, MEMORY_PORT_OFF);
418 /********** specialised access functions **********/
422 static inline void FLUSH_RX_CHANNEL (hrz_dev * dev, u16 channel) {
423 wr_regw (dev, RX_CHANNEL_PORT_OFF, FLUSH_CHANNEL | channel);
427 static inline void WAIT_FLUSH_RX_COMPLETE (hrz_dev * dev) {
428 while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & FLUSH_CHANNEL)
433 static inline void SELECT_RX_CHANNEL (hrz_dev * dev, u16 channel) {
434 wr_regw (dev, RX_CHANNEL_PORT_OFF, channel);
438 static inline void WAIT_UPDATE_COMPLETE (hrz_dev * dev) {
439 while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & RX_CHANNEL_UPDATE_IN_PROGRESS)
446 static inline void SELECT_TX_CHANNEL (hrz_dev * dev, u16 tx_channel) {
447 wr_regl (dev, TX_CHANNEL_PORT_OFF, tx_channel);
451 /* Update or query one configuration parameter of a particular channel. */
453 static inline void update_tx_channel_config (hrz_dev * dev, short chan, u8 mode, u16 value) {
454 wr_regw (dev, TX_CHANNEL_CONFIG_COMMAND_OFF,
455 chan * TX_CHANNEL_CONFIG_MULT | mode);
456 wr_regw (dev, TX_CHANNEL_CONFIG_DATA_OFF, value);
460 static inline u16 query_tx_channel_config (hrz_dev * dev, short chan, u8 mode) {
461 wr_regw (dev, TX_CHANNEL_CONFIG_COMMAND_OFF,
462 chan * TX_CHANNEL_CONFIG_MULT | mode);
463 return rd_regw (dev, TX_CHANNEL_CONFIG_DATA_OFF);
466 /********** dump functions **********/
468 static inline void dump_skb (char * prefix, unsigned int vc, struct sk_buff * skb) {
471 unsigned char * data = skb->data;
472 PRINTDB (DBG_DATA, "%s(%u) ", prefix, vc);
473 for (i=0; i<skb->len && i < 256;i++)
474 PRINTDM (DBG_DATA, "%02x ", data[i]);
475 PRINTDE (DBG_DATA,"");
484 #if 0 /* unused and in conflict with <asm-ppc/system.h> */
485 static inline void dump_regs (hrz_dev * dev) {
487 PRINTD (DBG_REGS, "CONTROL 0: %#x", rd_regl (dev, CONTROL_0_REG));
488 PRINTD (DBG_REGS, "RX CONFIG: %#x", rd_regw (dev, RX_CONFIG_OFF));
489 PRINTD (DBG_REGS, "TX CONFIG: %#x", rd_regw (dev, TX_CONFIG_OFF));
490 PRINTD (DBG_REGS, "TX STATUS: %#x", rd_regw (dev, TX_STATUS_OFF));
491 PRINTD (DBG_REGS, "IRQ ENBLE: %#x", rd_regl (dev, INT_ENABLE_REG_OFF));
492 PRINTD (DBG_REGS, "IRQ SORCE: %#x", rd_regl (dev, INT_SOURCE_REG_OFF));
500 static inline void dump_framer (hrz_dev * dev) {
503 PRINTDB (DBG_REGS, "framer registers:");
504 for (i = 0; i < 0x10; ++i)
505 PRINTDM (DBG_REGS, " %02x", rd_framer (dev, i));
506 PRINTDE (DBG_REGS,"");
513 /********** VPI/VCI <-> (RX) channel conversions **********/
515 /* RX channels are 10 bit integers, these fns are quite paranoid */
517 static inline int channel_to_vpivci (const u16 channel, short * vpi, int * vci) {
518 unsigned short vci_bits = 10 - vpi_bits;
519 if ((channel & RX_CHANNEL_MASK) == channel) {
520 *vci = channel & ((~0)<<vci_bits);
521 *vpi = channel >> vci_bits;
522 return channel ? 0 : -EINVAL;
527 static inline int vpivci_to_channel (u16 * channel, const short vpi, const int vci) {
528 unsigned short vci_bits = 10 - vpi_bits;
529 if (0 <= vpi && vpi < 1<<vpi_bits && 0 <= vci && vci < 1<<vci_bits) {
530 *channel = vpi<<vci_bits | vci;
531 return *channel ? 0 : -EINVAL;
536 /********** decode RX queue entries **********/
538 static inline u16 rx_q_entry_to_length (u32 x) {
539 return x & RX_Q_ENTRY_LENGTH_MASK;
542 static inline u16 rx_q_entry_to_rx_channel (u32 x) {
543 return (x>>RX_Q_ENTRY_CHANNEL_SHIFT) & RX_CHANNEL_MASK;
546 /* Cell Transmit Rate Values
548 * the cell transmit rate (cells per sec) can be set to a variety of
549 * different values by specifying two parameters: a timer preload from
550 * 1 to 16 (stored as 0 to 15) and a clock divider (2 to the power of
551 * an exponent from 0 to 14; the special value 15 disables the timer).
553 * cellrate = baserate / (preload * 2^divider)
555 * The maximum cell rate that can be specified is therefore just the
556 * base rate. Halving the preload is equivalent to adding 1 to the
557 * divider and so values 1 to 8 of the preload are redundant except
558 * in the case of a maximal divider (14).
560 * Given a desired cell rate, an algorithm to determine the preload
563 * a) x = baserate / cellrate, want p * 2^d = x (as far as possible)
564 * b) if x > 16 * 2^14 then set p = 16, d = 14 (min rate), done
565 * if x <= 16 then set p = x, d = 0 (high rates), done
566 * c) now have 16 < x <= 2^18, or 1 < x/16 <= 2^14 and we want to
567 * know n such that 2^(n-1) < x/16 <= 2^n, so slide a bit until
568 * we find the range (n will be between 1 and 14), set d = n
569 * d) Also have 8 < x/2^n <= 16, so set p nearest x/2^n
571 * The algorithm used below is a minor variant of the above.
573 * The base rate is derived from the oscillator frequency (Hz) using a
576 * baserate = freq / 32 in the case of some Unknown Card
577 * baserate = freq / 8 in the case of the Horizon 25
578 * baserate = freq / 8 in the case of the Horizon Ultra 155
580 * The Horizon cards have oscillators and base rates as follows:
582 * Card Oscillator Base Rate
583 * Unknown Card 33 MHz 1.03125 MHz (33 MHz = PCI freq)
584 * Horizon 25 32 MHz 4 MHz
585 * Horizon Ultra 155 40 MHz 5 MHz
587 * The following defines give the base rates in Hz. These were
588 * previously a factor of 100 larger, no doubt someone was using
592 #define BR_UKN 1031250l
593 #define BR_HRZ 4000000l
594 #define BR_ULT 5000000l
600 // p ranges from 1 to a power of 2
603 static int make_rate (const hrz_dev * dev, u32 c, rounding r,
604 u16 * bits, unsigned int * actual) {
606 // note: rounding the rate down means rounding 'p' up
608 const unsigned long br = test_bit (ultra, (hrz_flags *) &dev->flags) ?
614 // local fn to build the timer bits
617 if (div > CR_MAXD || (!pre) || pre > 1<<CR_MAXPEXP) {
618 PRINTD (DBG_QOS, "set_cr internal failure: d=%u p=%u",
623 *bits = (div<<CLOCK_SELECT_SHIFT) | (pre-1);
625 *actual = (br + (pre<<div) - 1) / (pre<<div);
626 PRINTD (DBG_QOS, "actual rate: %u", *actual);
632 // br_exp and br_man are used to avoid overflowing (c*maxp*2^d) in
633 // the tests below. We could think harder about exact possibilities
636 unsigned long br_man = br;
637 unsigned int br_exp = 0;
639 PRINTD (DBG_QOS|DBG_FLOW, "make_rate b=%lu, c=%u, %s", br, c,
640 (r == round_up) ? "up" : (r == round_down) ? "down" : "nearest");
644 PRINTD (DBG_QOS|DBG_ERR, "zero rate is not allowed!");
648 while (br_exp < CR_MAXPEXP + CR_MIND && (br_man % 2 == 0)) {
649 br_man = br_man >> 1;
652 // (br >>br_exp) <<br_exp == br and
653 // br_exp <= CR_MAXPEXP+CR_MIND
655 if (br_man <= (c << (CR_MAXPEXP+CR_MIND-br_exp))) {
656 // Equivalent to: B <= (c << (MAXPEXP+MIND))
657 // take care of rounding
660 pre = (br+(c<<div)-1)/(c<<div);
661 // but p must be non-zero
666 pre = (br+(c<<div)/2)/(c<<div);
667 // but p must be non-zero
673 // but p must be non-zero
678 PRINTD (DBG_QOS, "A: p=%u, d=%u", pre, div);
682 // at this point we have
683 // d == MIND and (c << (MAXPEXP+MIND)) < B
684 while (div < CR_MAXD) {
686 if (br_man <= (c << (CR_MAXPEXP+div-br_exp))) {
687 // Equivalent to: B <= (c << (MAXPEXP+d))
688 // c << (MAXPEXP+d-1) < B <= c << (MAXPEXP+d)
689 // 1 << (MAXPEXP-1) < B/2^d/c <= 1 << MAXPEXP
690 // MAXP/2 < B/c2^d <= MAXP
691 // take care of rounding
694 pre = (br+(c<<div)-1)/(c<<div);
697 pre = (br+(c<<div)/2)/(c<<div);
703 PRINTD (DBG_QOS, "B: p=%u, d=%u", pre, div);
707 // at this point we have
708 // d == MAXD and (c << (MAXPEXP+MAXD)) < B
709 // but we cannot go any higher
710 // take care of rounding
720 pre = 1 << CR_MAXPEXP;
721 PRINTD (DBG_QOS, "C: p=%u, d=%u", pre, div);
725 static int make_rate_with_tolerance (const hrz_dev * dev, u32 c, rounding r, unsigned int tol,
726 u16 * bit_pattern, unsigned int * actual) {
727 unsigned int my_actual;
729 PRINTD (DBG_QOS|DBG_FLOW, "make_rate_with_tolerance c=%u, %s, tol=%u",
730 c, (r == round_up) ? "up" : (r == round_down) ? "down" : "nearest", tol);
733 // actual rate is not returned
736 if (make_rate (dev, c, round_nearest, bit_pattern, actual))
737 // should never happen as round_nearest always succeeds
740 if (c - tol <= *actual && *actual <= c + tol)
744 // intolerant, try rounding instead
745 return make_rate (dev, c, r, bit_pattern, actual);
748 /********** Listen on a VC **********/
750 static int hrz_open_rx (hrz_dev * dev, u16 channel) {
751 // is there any guarantee that we don't get two simulataneous
752 // identical calls of this function from different processes? yes
755 u32 channel_type; // u16?
757 u16 buf_ptr = RX_CHANNEL_IDLE;
759 rx_ch_desc * rx_desc = &memmap->rx_descs[channel];
761 PRINTD (DBG_FLOW, "hrz_open_rx %x", channel);
763 spin_lock_irqsave (&dev->mem_lock, flags);
764 channel_type = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK;
765 spin_unlock_irqrestore (&dev->mem_lock, flags);
767 // very serious error, should never occur
768 if (channel_type != RX_CHANNEL_DISABLED) {
769 PRINTD (DBG_ERR|DBG_VCC, "RX channel for VC already open");
770 return -EBUSY; // clean up?
773 // Give back spare buffer
774 if (dev->noof_spare_buffers) {
775 buf_ptr = dev->spare_buffers[--dev->noof_spare_buffers];
776 PRINTD (DBG_VCC, "using a spare buffer: %u", buf_ptr);
777 // should never occur
778 if (buf_ptr == RX_CHANNEL_DISABLED || buf_ptr == RX_CHANNEL_IDLE) {
779 // but easy to recover from
780 PRINTD (DBG_ERR|DBG_VCC, "bad spare buffer pointer, using IDLE");
781 buf_ptr = RX_CHANNEL_IDLE;
784 PRINTD (DBG_VCC, "using IDLE buffer pointer");
787 // Channel is currently disabled so change its status to idle
789 // do we really need to save the flags again?
790 spin_lock_irqsave (&dev->mem_lock, flags);
792 wr_mem (dev, &rx_desc->wr_buf_type,
793 buf_ptr | CHANNEL_TYPE_AAL5 | FIRST_CELL_OF_AAL5_FRAME);
794 if (buf_ptr != RX_CHANNEL_IDLE)
795 wr_mem (dev, &rx_desc->rd_buf_type, buf_ptr);
797 spin_unlock_irqrestore (&dev->mem_lock, flags);
799 // rxer->rate = make_rate (qos->peak_cells);
801 PRINTD (DBG_FLOW, "hrz_open_rx ok");
807 /********** change vc rate for a given vc **********/
809 static void hrz_change_vc_qos (ATM_RXER * rxer, MAAL_QOS * qos) {
810 rxer->rate = make_rate (qos->peak_cells);
814 /********** free an skb (as per ATM device driver documentation) **********/
816 static inline void hrz_kfree_skb (struct sk_buff * skb) {
817 if (ATM_SKB(skb)->vcc->pop) {
818 ATM_SKB(skb)->vcc->pop (ATM_SKB(skb)->vcc, skb);
820 dev_kfree_skb_any (skb);
824 /********** cancel listen on a VC **********/
826 static void hrz_close_rx (hrz_dev * dev, u16 vc) {
833 rx_ch_desc * rx_desc = &memmap->rx_descs[vc];
837 spin_lock_irqsave (&dev->mem_lock, flags);
838 value = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK;
839 spin_unlock_irqrestore (&dev->mem_lock, flags);
841 if (value == RX_CHANNEL_DISABLED) {
842 // I suppose this could happen once we deal with _NONE traffic properly
843 PRINTD (DBG_VCC, "closing VC: RX channel %u already disabled", vc);
846 if (value == RX_CHANNEL_IDLE)
849 spin_lock_irqsave (&dev->mem_lock, flags);
852 wr_mem (dev, &rx_desc->wr_buf_type, RX_CHANNEL_DISABLED);
854 if ((rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK) == RX_CHANNEL_DISABLED)
861 spin_unlock_irqrestore (&dev->mem_lock, flags);
865 WAIT_FLUSH_RX_COMPLETE(dev);
867 // XXX Is this all really necessary? We can rely on the rx_data_av
868 // handler to discard frames that remain queued for delivery. If the
869 // worry is that immediately reopening the channel (perhaps by a
870 // different process) may cause some data to be mis-delivered then
871 // there may still be a simpler solution (such as busy-waiting on
872 // rx_busy once the channel is disabled or before a new one is
873 // opened - does this leave any holes?). Arguably setting up and
874 // tearing down the TX and RX halves of each virtual circuit could
875 // most safely be done within ?x_busy protected regions.
877 // OK, current changes are that Simon's marker is disabled and we DO
878 // look for NULL rxer elsewhere. The code here seems flush frames
879 // and then remember the last dead cell belonging to the channel
880 // just disabled - the cell gets relinked at the next vc_open.
881 // However, when all VCs are closed or only a few opened there are a
882 // handful of buffers that are unusable.
884 // Does anyone feel like documenting spare_buffers properly?
885 // Does anyone feel like fixing this in a nicer way?
887 // Flush any data which is left in the channel
889 // Change the rx channel port to something different to the RX
890 // channel we are trying to close to force Horizon to flush the rx
891 // channel read and write pointers.
893 u16 other = vc^(RX_CHANS/2);
895 SELECT_RX_CHANNEL (dev, other);
896 WAIT_UPDATE_COMPLETE (dev);
898 r1 = rd_mem (dev, &rx_desc->rd_buf_type);
900 // Select this RX channel. Flush doesn't seem to work unless we
901 // select an RX channel before hand
903 SELECT_RX_CHANNEL (dev, vc);
904 WAIT_UPDATE_COMPLETE (dev);
906 // Attempt to flush a frame on this RX channel
908 FLUSH_RX_CHANNEL (dev, vc);
909 WAIT_FLUSH_RX_COMPLETE (dev);
911 // Force Horizon to flush rx channel read and write pointers as before
913 SELECT_RX_CHANNEL (dev, other);
914 WAIT_UPDATE_COMPLETE (dev);
916 r2 = rd_mem (dev, &rx_desc->rd_buf_type);
918 PRINTD (DBG_VCC|DBG_RX, "r1 = %u, r2 = %u", r1, r2);
921 dev->spare_buffers[dev->noof_spare_buffers++] = (u16)r1;
928 rx_q_entry * wr_ptr = &memmap->rx_q_entries[rd_regw (dev, RX_QUEUE_WR_PTR_OFF)];
929 rx_q_entry * rd_ptr = dev->rx_q_entry;
931 PRINTD (DBG_VCC|DBG_RX, "rd_ptr = %u, wr_ptr = %u", rd_ptr, wr_ptr);
933 while (rd_ptr != wr_ptr) {
934 u32 x = rd_mem (dev, (HDW *) rd_ptr);
936 if (vc == rx_q_entry_to_rx_channel (x)) {
937 x |= SIMONS_DODGEY_MARKER;
939 PRINTD (DBG_RX|DBG_VCC|DBG_WARN, "marking a frame as dodgey");
941 wr_mem (dev, (HDW *) rd_ptr, x);
944 if (rd_ptr == dev->rx_q_wrap)
945 rd_ptr = dev->rx_q_reset;
952 spin_unlock_irqrestore (&dev->mem_lock, flags);
957 /********** schedule RX transfers **********/
959 // Note on tail recursion: a GCC developer said that it is not likely
960 // to be fixed soon, so do not define TAILRECUSRIONWORKS unless you
961 // are sure it does as you may otherwise overflow the kernel stack.
963 // giving this fn a return value would help GCC, alledgedly
965 static void rx_schedule (hrz_dev * dev, int irq) {
966 unsigned int rx_bytes;
969 #ifndef TAILRECURSIONWORKS
971 while (pio_instead) {
973 // bytes waiting for RX transfer
974 rx_bytes = dev->rx_bytes;
978 while (rd_regl (dev, MASTER_RX_COUNT_REG_OFF)) {
979 PRINTD (DBG_RX|DBG_WARN, "RX error: other PCI Bus Master RX still in progress!");
980 if (++spin_count > 10) {
981 PRINTD (DBG_RX|DBG_ERR, "spun out waiting PCI Bus Master RX completion");
982 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
983 clear_bit (rx_busy, &dev->flags);
984 hrz_kfree_skb (dev->rx_skb);
990 // this code follows the TX code but (at the moment) there is only
991 // one region - the skb itself. I don't know if this will change,
992 // but it doesn't hurt to have the code here, disabled.
995 // start next transfer within same region
996 if (rx_bytes <= MAX_PIO_COUNT) {
997 PRINTD (DBG_RX|DBG_BUS, "(pio)");
1000 if (rx_bytes <= MAX_TRANSFER_COUNT) {
1001 PRINTD (DBG_RX|DBG_BUS, "(simple or last multi)");
1004 PRINTD (DBG_RX|DBG_BUS, "(continuing multi)");
1005 dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT;
1006 rx_bytes = MAX_TRANSFER_COUNT;
1009 // rx_bytes == 0 -- we're between regions
1010 // regions remaining to transfer
1012 unsigned int rx_regions = dev->rx_regions;
1014 unsigned int rx_regions = 0;
1019 // start a new region
1020 dev->rx_addr = dev->rx_iovec->iov_base;
1021 rx_bytes = dev->rx_iovec->iov_len;
1023 dev->rx_regions = rx_regions - 1;
1025 if (rx_bytes <= MAX_PIO_COUNT) {
1026 PRINTD (DBG_RX|DBG_BUS, "(pio)");
1029 if (rx_bytes <= MAX_TRANSFER_COUNT) {
1030 PRINTD (DBG_RX|DBG_BUS, "(full region)");
1033 PRINTD (DBG_RX|DBG_BUS, "(start multi region)");
1034 dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT;
1035 rx_bytes = MAX_TRANSFER_COUNT;
1040 // that's all folks - end of frame
1041 struct sk_buff * skb = dev->rx_skb;
1042 // dev->rx_iovec = 0;
1044 FLUSH_RX_CHANNEL (dev, dev->rx_channel);
1046 dump_skb ("<<<", dev->rx_channel, skb);
1048 PRINTD (DBG_RX|DBG_SKB, "push %p %u", skb->data, skb->len);
1051 struct atm_vcc * vcc = ATM_SKB(skb)->vcc;
1053 atomic_inc(&vcc->stats->rx);
1055 // end of our responsability
1056 vcc->push (vcc, skb);
1061 // note: writing RX_COUNT clears any interrupt condition
1065 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1066 rds_regb (dev, DATA_PORT_OFF, dev->rx_addr, rx_bytes);
1068 wr_regl (dev, MASTER_RX_ADDR_REG_OFF, virt_to_bus (dev->rx_addr));
1069 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, rx_bytes);
1071 dev->rx_addr += rx_bytes;
1074 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1075 // allow another RX thread to start
1077 clear_bit (rx_busy, &dev->flags);
1078 PRINTD (DBG_RX, "cleared rx_busy for dev %p", dev);
1081 #ifdef TAILRECURSIONWORKS
1082 // and we all bless optimised tail calls
1084 return rx_schedule (dev, 0);
1094 /********** handle RX bus master complete events **********/
1096 static inline void rx_bus_master_complete_handler (hrz_dev * dev) {
1097 if (test_bit (rx_busy, &dev->flags)) {
1098 rx_schedule (dev, 1);
1100 PRINTD (DBG_RX|DBG_ERR, "unexpected RX bus master completion");
1101 // clear interrupt condition on adapter
1102 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1107 /********** (queue to) become the next TX thread **********/
1109 static inline int tx_hold (hrz_dev * dev) {
1110 while (test_and_set_bit (tx_busy, &dev->flags)) {
1111 PRINTD (DBG_TX, "sleeping at tx lock %p %u", dev, dev->flags);
1112 interruptible_sleep_on (&dev->tx_queue);
1113 PRINTD (DBG_TX, "woken at tx lock %p %u", dev, dev->flags);
1114 if (signal_pending (current))
1117 PRINTD (DBG_TX, "set tx_busy for dev %p", dev);
1121 /********** allow another TX thread to start **********/
1123 static inline void tx_release (hrz_dev * dev) {
1124 clear_bit (tx_busy, &dev->flags);
1125 PRINTD (DBG_TX, "cleared tx_busy for dev %p", dev);
1126 wake_up_interruptible (&dev->tx_queue);
1129 /********** schedule TX transfers **********/
1131 static void tx_schedule (hrz_dev * const dev, int irq) {
1132 unsigned int tx_bytes;
1134 int append_desc = 0;
1136 int pio_instead = 0;
1137 #ifndef TAILRECURSIONWORKS
1139 while (pio_instead) {
1141 // bytes in current region waiting for TX transfer
1142 tx_bytes = dev->tx_bytes;
1146 while (rd_regl (dev, MASTER_TX_COUNT_REG_OFF)) {
1147 PRINTD (DBG_TX|DBG_WARN, "TX error: other PCI Bus Master TX still in progress!");
1148 if (++spin_count > 10) {
1149 PRINTD (DBG_TX|DBG_ERR, "spun out waiting PCI Bus Master TX completion");
1150 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1152 hrz_kfree_skb (dev->tx_skb);
1159 // start next transfer within same region
1160 if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) {
1161 PRINTD (DBG_TX|DBG_BUS, "(pio)");
1164 if (tx_bytes <= MAX_TRANSFER_COUNT) {
1165 PRINTD (DBG_TX|DBG_BUS, "(simple or last multi)");
1166 if (!dev->tx_iovec) {
1167 // end of last region
1172 PRINTD (DBG_TX|DBG_BUS, "(continuing multi)");
1173 dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT;
1174 tx_bytes = MAX_TRANSFER_COUNT;
1177 // tx_bytes == 0 -- we're between regions
1178 // regions remaining to transfer
1179 unsigned int tx_regions = dev->tx_regions;
1182 // start a new region
1183 dev->tx_addr = dev->tx_iovec->iov_base;
1184 tx_bytes = dev->tx_iovec->iov_len;
1186 dev->tx_regions = tx_regions - 1;
1188 if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) {
1189 PRINTD (DBG_TX|DBG_BUS, "(pio)");
1192 if (tx_bytes <= MAX_TRANSFER_COUNT) {
1193 PRINTD (DBG_TX|DBG_BUS, "(full region)");
1196 PRINTD (DBG_TX|DBG_BUS, "(start multi region)");
1197 dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT;
1198 tx_bytes = MAX_TRANSFER_COUNT;
1202 // that's all folks - end of frame
1203 struct sk_buff * skb = dev->tx_skb;
1207 atomic_inc(&ATM_SKB(skb)->vcc->stats->tx);
1210 hrz_kfree_skb (skb);
1214 // note: writing TX_COUNT clears any interrupt condition
1218 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1219 wrs_regb (dev, DATA_PORT_OFF, dev->tx_addr, tx_bytes);
1221 wr_regl (dev, TX_DESCRIPTOR_PORT_OFF, cpu_to_be32 (dev->tx_skb->len));
1223 wr_regl (dev, MASTER_TX_ADDR_REG_OFF, virt_to_bus (dev->tx_addr));
1225 wr_regl (dev, TX_DESCRIPTOR_REG_OFF, cpu_to_be32 (dev->tx_skb->len));
1226 wr_regl (dev, MASTER_TX_COUNT_REG_OFF,
1228 ? tx_bytes | MASTER_TX_AUTO_APPEND_DESC
1231 dev->tx_addr += tx_bytes;
1234 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1239 #ifdef TAILRECURSIONWORKS
1240 // and we all bless optimised tail calls
1242 return tx_schedule (dev, 0);
1252 /********** handle TX bus master complete events **********/
1254 static inline void tx_bus_master_complete_handler (hrz_dev * dev) {
1255 if (test_bit (tx_busy, &dev->flags)) {
1256 tx_schedule (dev, 1);
1258 PRINTD (DBG_TX|DBG_ERR, "unexpected TX bus master completion");
1259 // clear interrupt condition on adapter
1260 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1265 /********** move RX Q pointer to next item in circular buffer **********/
1267 // called only from IRQ sub-handler
1268 static inline u32 rx_queue_entry_next (hrz_dev * dev) {
1270 spin_lock (&dev->mem_lock);
1271 rx_queue_entry = rd_mem (dev, &dev->rx_q_entry->entry);
1272 if (dev->rx_q_entry == dev->rx_q_wrap)
1273 dev->rx_q_entry = dev->rx_q_reset;
1276 wr_regw (dev, RX_QUEUE_RD_PTR_OFF, dev->rx_q_entry - dev->rx_q_reset);
1277 spin_unlock (&dev->mem_lock);
1278 return rx_queue_entry;
1281 /********** handle RX disabled by device **********/
1283 static inline void rx_disabled_handler (hrz_dev * dev) {
1284 wr_regw (dev, RX_CONFIG_OFF, rd_regw (dev, RX_CONFIG_OFF) | RX_ENABLE);
1286 PRINTK (KERN_WARNING, "RX was disabled!");
1289 /********** handle RX data received by device **********/
1291 // called from IRQ handler
1292 static inline void rx_data_av_handler (hrz_dev * dev) {
1294 u32 rx_queue_entry_flags;
1298 PRINTD (DBG_FLOW, "hrz_data_av_handler");
1300 // try to grab rx lock (not possible during RX bus mastering)
1301 if (test_and_set_bit (rx_busy, &dev->flags)) {
1302 PRINTD (DBG_RX, "locked out of rx lock");
1305 PRINTD (DBG_RX, "set rx_busy for dev %p", dev);
1306 // lock is cleared if we fail now, o/w after bus master completion
1308 YELLOW_LED_OFF(dev);
1310 rx_queue_entry = rx_queue_entry_next (dev);
1312 rx_len = rx_q_entry_to_length (rx_queue_entry);
1313 rx_channel = rx_q_entry_to_rx_channel (rx_queue_entry);
1315 WAIT_FLUSH_RX_COMPLETE (dev);
1317 SELECT_RX_CHANNEL (dev, rx_channel);
1319 PRINTD (DBG_RX, "rx_queue_entry is: %#x", rx_queue_entry);
1320 rx_queue_entry_flags = rx_queue_entry & (RX_CRC_32_OK|RX_COMPLETE_FRAME|SIMONS_DODGEY_MARKER);
1323 // (at least) bus-mastering breaks if we try to handle a
1324 // zero-length frame, besides AAL5 does not support them
1325 PRINTK (KERN_ERR, "zero-length frame!");
1326 rx_queue_entry_flags &= ~RX_COMPLETE_FRAME;
1329 if (rx_queue_entry_flags & SIMONS_DODGEY_MARKER) {
1330 PRINTD (DBG_RX|DBG_ERR, "Simon's marker detected!");
1332 if (rx_queue_entry_flags == (RX_CRC_32_OK | RX_COMPLETE_FRAME)) {
1333 struct atm_vcc * atm_vcc;
1335 PRINTD (DBG_RX, "got a frame on rx_channel %x len %u", rx_channel, rx_len);
1337 atm_vcc = dev->rxer[rx_channel];
1338 // if no vcc is assigned to this channel, we should drop the frame
1339 // (is this what SIMONS etc. was trying to achieve?)
1343 if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) {
1345 if (rx_len <= atm_vcc->qos.rxtp.max_sdu) {
1347 struct sk_buff * skb = atm_alloc_charge (atm_vcc, rx_len, GFP_ATOMIC);
1349 // remember this so we can push it later
1351 // remember this so we can flush it later
1352 dev->rx_channel = rx_channel;
1354 // prepare socket buffer
1355 skb_put (skb, rx_len);
1356 ATM_SKB(skb)->vcc = atm_vcc;
1359 // dev->rx_regions = 0;
1360 // dev->rx_iovec = 0;
1361 dev->rx_bytes = rx_len;
1362 dev->rx_addr = skb->data;
1363 PRINTD (DBG_RX, "RX start simple transfer (addr %p, len %d)",
1367 rx_schedule (dev, 0);
1371 PRINTD (DBG_SKB|DBG_WARN, "failed to get skb");
1375 PRINTK (KERN_INFO, "frame received on TX-only VC %x", rx_channel);
1376 // do we count this?
1380 PRINTK (KERN_WARNING, "dropped over-size frame");
1381 // do we count this?
1385 PRINTD (DBG_WARN|DBG_VCC|DBG_RX, "no VCC for this frame (VC closed)");
1386 // do we count this?
1390 // Wait update complete ? SPONG
1396 FLUSH_RX_CHANNEL (dev,rx_channel);
1397 clear_bit (rx_busy, &dev->flags);
1402 /********** interrupt handler **********/
1404 static void interrupt_handler (int irq, void * dev_id, struct pt_regs * pt_regs) {
1405 hrz_dev * dev = hrz_devs;
1407 unsigned int irq_ok;
1410 PRINTD (DBG_FLOW, "interrupt_handler: %p", dev_id);
1413 PRINTD (DBG_IRQ|DBG_ERR, "irq with NULL dev_id: %d", irq);
1416 // Did one of our cards generate the interrupt?
1423 PRINTD (DBG_IRQ, "irq not for me: %d", irq);
1426 if (irq != dev->irq) {
1427 PRINTD (DBG_IRQ|DBG_ERR, "irq mismatch: %d", irq);
1431 // definitely for us
1433 while ((int_source = rd_regl (dev, INT_SOURCE_REG_OFF)
1434 & INTERESTING_INTERRUPTS)) {
1435 // In the interests of fairness, the (inline) handlers below are
1436 // called in sequence and without immediate return to the head of
1437 // the while loop. This is only of issue for slow hosts (or when
1438 // debugging messages are on). Really slow hosts may find a fast
1439 // sender keeps them permanently in the IRQ handler. :(
1441 // (only an issue for slow hosts) RX completion goes before
1442 // rx_data_av as the former implies rx_busy and so the latter
1443 // would just abort. If it reschedules another transfer
1444 // (continuing the same frame) then it will not clear rx_busy.
1446 // (only an issue for slow hosts) TX completion goes before RX
1447 // data available as it is a much shorter routine - there is the
1448 // chance that any further transfers it schedules will be complete
1449 // by the time of the return to the head of the while loop
1451 if (int_source & RX_BUS_MASTER_COMPLETE) {
1453 PRINTD (DBG_IRQ|DBG_BUS|DBG_RX, "rx_bus_master_complete asserted");
1454 rx_bus_master_complete_handler (dev);
1456 if (int_source & TX_BUS_MASTER_COMPLETE) {
1458 PRINTD (DBG_IRQ|DBG_BUS|DBG_TX, "tx_bus_master_complete asserted");
1459 tx_bus_master_complete_handler (dev);
1461 if (int_source & RX_DATA_AV) {
1463 PRINTD (DBG_IRQ|DBG_RX, "rx_data_av asserted");
1464 rx_data_av_handler (dev);
1468 PRINTD (DBG_IRQ, "work done: %u", irq_ok);
1470 PRINTD (DBG_IRQ|DBG_WARN, "spurious interrupt source: %#x", int_source);
1473 PRINTD (DBG_IRQ|DBG_FLOW, "interrupt_handler done: %p", dev_id);
1476 /********** housekeeping **********/
1478 static void set_timer (struct timer_list * timer, unsigned int delay) {
1479 timer->expires = jiffies + delay;
1484 static void do_housekeeping (unsigned long arg) {
1485 // just stats at the moment
1486 hrz_dev * dev = hrz_devs;
1488 // data is set to zero at module unload
1489 if (housekeeping.data) {
1491 // collect device-specific (not driver/atm-linux) stats here
1492 dev->tx_cell_count += rd_regw (dev, TX_CELL_COUNT_OFF);
1493 dev->rx_cell_count += rd_regw (dev, RX_CELL_COUNT_OFF);
1494 dev->hec_error_count += rd_regw (dev, HEC_ERROR_COUNT_OFF);
1495 dev->unassigned_cell_count += rd_regw (dev, UNASSIGNED_CELL_COUNT_OFF);
1498 set_timer (&housekeeping, HZ/10);
1503 /********** find an idle channel for TX and set it up **********/
1505 // called with tx_busy set
1506 static inline short setup_idle_tx_channel (hrz_dev * dev, hrz_vcc * vcc) {
1507 unsigned short idle_channels;
1508 short tx_channel = -1;
1509 unsigned int spin_count;
1510 PRINTD (DBG_FLOW|DBG_TX, "setup_idle_tx_channel %p", dev);
1512 // better would be to fail immediately, the caller can then decide whether
1513 // to wait or drop (depending on whether this is UBR etc.)
1515 while (!(idle_channels = rd_regw (dev, TX_STATUS_OFF) & IDLE_CHANNELS_MASK)) {
1516 PRINTD (DBG_TX|DBG_WARN, "waiting for idle TX channel");
1518 if (++spin_count > 100) {
1519 PRINTD (DBG_TX|DBG_ERR, "spun out waiting for idle TX channel");
1524 // got an idle channel
1526 // tx_idle ensures we look for idle channels in RR order
1527 int chan = dev->tx_idle;
1530 while (keep_going) {
1531 if (idle_channels & (1<<chan)) {
1536 if (chan == TX_CHANS)
1540 dev->tx_idle = chan;
1543 // set up the channel we found
1545 // Initialise the cell header in the transmit channel descriptor
1546 // a.k.a. prepare the channel and remember that we have done so.
1548 tx_ch_desc * tx_desc = &memmap->tx_descs[tx_channel];
1551 u16 channel = vcc->channel;
1553 unsigned long flags;
1554 spin_lock_irqsave (&dev->mem_lock, flags);
1556 // Update the transmit channel record.
1557 dev->tx_channel_record[tx_channel] = channel;
1560 update_tx_channel_config (dev, tx_channel, RATE_TYPE_ACCESS,
1563 // Update the PCR counter preload value etc.
1564 update_tx_channel_config (dev, tx_channel, PCR_TIMER_ACCESS,
1568 if (vcc->tx_xbr_bits == VBR_RATE_TYPE) {
1570 update_tx_channel_config (dev, tx_channel, SCR_TIMER_ACCESS,
1574 update_tx_channel_config (dev, tx_channel, BUCKET_CAPACITY_ACCESS,
1575 vcc->tx_bucket_bits);
1578 update_tx_channel_config (dev, tx_channel, BUCKET_FULLNESS_ACCESS,
1579 vcc->tx_bucket_bits);
1583 // Initialise the read and write buffer pointers
1584 rd_ptr = rd_mem (dev, &tx_desc->rd_buf_type) & BUFFER_PTR_MASK;
1585 wr_ptr = rd_mem (dev, &tx_desc->wr_buf_type) & BUFFER_PTR_MASK;
1587 // idle TX channels should have identical pointers
1588 if (rd_ptr != wr_ptr) {
1589 PRINTD (DBG_TX|DBG_ERR, "TX buffer pointers are broken!");
1590 // spin_unlock... return -E...
1591 // I wonder if gcc would get rid of one of the pointer aliases
1593 PRINTD (DBG_TX, "TX buffer pointers are: rd %x, wr %x.",
1598 PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal0");
1599 rd_ptr |= CHANNEL_TYPE_RAW_CELLS;
1600 wr_ptr |= CHANNEL_TYPE_RAW_CELLS;
1603 PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal34");
1604 rd_ptr |= CHANNEL_TYPE_AAL3_4;
1605 wr_ptr |= CHANNEL_TYPE_AAL3_4;
1608 rd_ptr |= CHANNEL_TYPE_AAL5;
1609 wr_ptr |= CHANNEL_TYPE_AAL5;
1610 // Initialise the CRC
1611 wr_mem (dev, &tx_desc->partial_crc, INITIAL_CRC);
1615 wr_mem (dev, &tx_desc->rd_buf_type, rd_ptr);
1616 wr_mem (dev, &tx_desc->wr_buf_type, wr_ptr);
1618 // Write the Cell Header
1619 // Payload Type, CLP and GFC would go here if non-zero
1620 wr_mem (dev, &tx_desc->cell_header, channel);
1622 spin_unlock_irqrestore (&dev->mem_lock, flags);
1628 /********** send a frame **********/
1630 static int hrz_send (struct atm_vcc * atm_vcc, struct sk_buff * skb) {
1631 unsigned int spin_count;
1633 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
1634 hrz_vcc * vcc = HRZ_VCC(atm_vcc);
1635 u16 channel = vcc->channel;
1637 u32 buffers_required;
1639 /* signed for error return */
1642 PRINTD (DBG_FLOW|DBG_TX, "hrz_send vc %x data %p len %u",
1643 channel, skb->data, skb->len);
1645 dump_skb (">>>", channel, skb);
1647 if (atm_vcc->qos.txtp.traffic_class == ATM_NONE) {
1648 PRINTK (KERN_ERR, "attempt to send on RX-only VC %x", channel);
1649 hrz_kfree_skb (skb);
1653 // don't understand this
1654 ATM_SKB(skb)->vcc = atm_vcc;
1656 if (skb->len > atm_vcc->qos.txtp.max_sdu) {
1657 PRINTK (KERN_ERR, "sk_buff length greater than agreed max_sdu, dropping...");
1658 hrz_kfree_skb (skb);
1663 PRINTD (DBG_ERR|DBG_TX, "attempt to transmit on zero (rx_)channel");
1664 hrz_kfree_skb (skb);
1670 // where would be a better place for this? housekeeping?
1672 pci_read_config_word (dev->pci_dev, PCI_STATUS, &status);
1673 if (status & PCI_STATUS_REC_MASTER_ABORT) {
1674 PRINTD (DBG_BUS|DBG_ERR, "Clearing PCI Master Abort (and cleaning up)");
1675 status &= ~PCI_STATUS_REC_MASTER_ABORT;
1676 pci_write_config_word (dev->pci_dev, PCI_STATUS, status);
1677 if (test_bit (tx_busy, &dev->flags)) {
1678 hrz_kfree_skb (dev->tx_skb);
1685 #ifdef DEBUG_HORIZON
1687 if (channel == 1023) {
1689 unsigned short d = 0;
1690 char * s = skb->data;
1692 for (i = 0; i < 4; ++i) {
1693 d = (d<<4) | ((*s <= '9') ? (*s - '0') : (*s - 'a' + 10));
1696 PRINTK (KERN_INFO, "debug bitmap is now %hx", debug = d);
1701 // wait until TX is free and grab lock
1702 if (tx_hold (dev)) {
1703 hrz_kfree_skb (skb);
1704 return -ERESTARTSYS;
1707 // Wait for enough space to be available in transmit buffer memory.
1709 // should be number of cells needed + 2 (according to hardware docs)
1710 // = ((framelen+8)+47) / 48 + 2
1711 // = (framelen+7) / 48 + 3, hmm... faster to put addition inside XXX
1712 buffers_required = (skb->len+(ATM_AAL5_TRAILER-1)) / ATM_CELL_PAYLOAD + 3;
1714 // replace with timer and sleep, add dev->tx_buffers_queue (max 1 entry)
1716 while ((free_buffers = rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF)) < buffers_required) {
1717 PRINTD (DBG_TX, "waiting for free TX buffers, got %d of %d",
1718 free_buffers, buffers_required);
1719 // what is the appropriate delay? implement a timeout? (depending on line speed?)
1721 // what happens if we kill (current_pid, SIGKILL) ?
1723 if (++spin_count > 1000) {
1724 PRINTD (DBG_TX|DBG_ERR, "spun out waiting for tx buffers, got %d of %d",
1725 free_buffers, buffers_required);
1727 hrz_kfree_skb (skb);
1728 return -ERESTARTSYS;
1732 // Select a channel to transmit the frame on.
1733 if (channel == dev->last_vc) {
1734 PRINTD (DBG_TX, "last vc hack: hit");
1735 tx_channel = dev->tx_last;
1737 PRINTD (DBG_TX, "last vc hack: miss");
1738 // Are we currently transmitting this VC on one of the channels?
1739 for (tx_channel = 0; tx_channel < TX_CHANS; ++tx_channel)
1740 if (dev->tx_channel_record[tx_channel] == channel) {
1741 PRINTD (DBG_TX, "vc already on channel: hit");
1744 if (tx_channel == TX_CHANS) {
1745 PRINTD (DBG_TX, "vc already on channel: miss");
1746 // Find and set up an idle channel.
1747 tx_channel = setup_idle_tx_channel (dev, vcc);
1748 if (tx_channel < 0) {
1749 PRINTD (DBG_TX|DBG_ERR, "failed to get channel");
1755 PRINTD (DBG_TX, "got channel");
1756 SELECT_TX_CHANNEL(dev, tx_channel);
1758 dev->last_vc = channel;
1759 dev->tx_last = tx_channel;
1762 PRINTD (DBG_TX, "using channel %u", tx_channel);
1764 YELLOW_LED_OFF(dev);
1766 // TX start transfer
1769 unsigned int tx_len = skb->len;
1770 unsigned int tx_iovcnt = skb_shinfo(skb)->nr_frags;
1771 // remember this so we can free it later
1775 // scatter gather transfer
1776 dev->tx_regions = tx_iovcnt;
1777 dev->tx_iovec = 0; /* @@@ needs rewritten */
1779 PRINTD (DBG_TX|DBG_BUS, "TX start scatter-gather transfer (iovec %p, len %d)",
1782 hrz_kfree_skb (skb);
1786 dev->tx_regions = 0;
1788 dev->tx_bytes = tx_len;
1789 dev->tx_addr = skb->data;
1790 PRINTD (DBG_TX|DBG_BUS, "TX start simple transfer (addr %p, len %d)",
1794 // and do the business
1795 tx_schedule (dev, 0);
1802 /********** reset a card **********/
1804 static void __init hrz_reset (const hrz_dev * dev) {
1805 u32 control_0_reg = rd_regl (dev, CONTROL_0_REG);
1807 // why not set RESET_HORIZON to one and wait for the card to
1808 // reassert that bit as zero? Like so:
1809 control_0_reg = control_0_reg & RESET_HORIZON;
1810 wr_regl (dev, CONTROL_0_REG, control_0_reg);
1811 while (control_0_reg & RESET_HORIZON)
1812 control_0_reg = rd_regl (dev, CONTROL_0_REG);
1814 // old reset code retained:
1815 wr_regl (dev, CONTROL_0_REG, control_0_reg |
1816 RESET_ATM | RESET_RX | RESET_TX | RESET_HOST);
1817 // just guessing here
1820 wr_regl (dev, CONTROL_0_REG, control_0_reg);
1823 /********** read the burnt in address **********/
1825 static u16 __init read_bia (const hrz_dev * dev, u16 addr) {
1827 u32 ctrl = rd_regl (dev, CONTROL_0_REG);
1829 void WRITE_IT_WAIT (void) {
1830 wr_regl (dev, CONTROL_0_REG, ctrl);
1834 void CLOCK_IT (void) {
1835 // DI must be valid around rising SK edge
1836 ctrl &= ~SEEPROM_SK;
1842 const unsigned int addr_bits = 6;
1843 const unsigned int data_bits = 16;
1849 ctrl &= ~(SEEPROM_CS | SEEPROM_SK | SEEPROM_DI);
1852 // wake Serial EEPROM and send 110 (READ) command
1853 ctrl |= (SEEPROM_CS | SEEPROM_DI);
1859 ctrl &= ~SEEPROM_DI;
1862 for (i=0; i<addr_bits; i++) {
1863 if (addr & (1 << (addr_bits-1)))
1866 ctrl &= ~SEEPROM_DI;
1873 // we could check that we have DO = 0 here
1874 ctrl &= ~SEEPROM_DI;
1877 for (i=0;i<data_bits;i++) {
1882 if (rd_regl (dev, CONTROL_0_REG) & SEEPROM_DO)
1883 res |= (1 << (data_bits-1));
1886 ctrl &= ~(SEEPROM_SK | SEEPROM_CS);
1892 /********** initialise a card **********/
1894 static int __init hrz_init (hrz_dev * dev) {
1908 ctrl = rd_regl (dev, CONTROL_0_REG);
1909 PRINTD (DBG_INFO, "ctrl0reg is %#x", ctrl);
1910 onefivefive = ctrl & ATM_LAYER_STATUS;
1913 printk (DEV_LABEL ": Horizon Ultra (at 155.52 MBps)");
1915 printk (DEV_LABEL ": Horizon (at 25 MBps)");
1918 // Reset the card to get everything in a known state
1923 // Clear all the buffer memory
1925 printk (" clearing memory");
1927 for (mem = (HDW *) memmap; mem < (HDW *) (memmap + 1); ++mem)
1928 wr_mem (dev, mem, 0);
1930 printk (" tx channels");
1932 // All transmit eight channels are set up as AAL5 ABR channels with
1933 // a 16us cell spacing. Why?
1935 // Channel 0 gets the free buffer at 100h, channel 1 gets the free
1936 // buffer at 110h etc.
1938 for (chan = 0; chan < TX_CHANS; ++chan) {
1939 tx_ch_desc * tx_desc = &memmap->tx_descs[chan];
1940 cell_buf * buf = &memmap->inittxbufs[chan];
1942 // initialise the read and write buffer pointers
1943 wr_mem (dev, &tx_desc->rd_buf_type, BUF_PTR(buf));
1944 wr_mem (dev, &tx_desc->wr_buf_type, BUF_PTR(buf));
1946 // set the status of the initial buffers to empty
1947 wr_mem (dev, &buf->next, BUFF_STATUS_EMPTY);
1950 // Use space bufn3 at the moment for tx buffers
1952 printk (" tx buffers");
1954 tx_desc = memmap->bufn3;
1956 wr_mem (dev, &memmap->txfreebufstart.next, BUF_PTR(tx_desc) | BUFF_STATUS_EMPTY);
1958 for (buff_count = 0; buff_count < BUFN3_SIZE-1; buff_count++) {
1959 wr_mem (dev, &tx_desc->next, BUF_PTR(tx_desc+1) | BUFF_STATUS_EMPTY);
1963 wr_mem (dev, &tx_desc->next, BUF_PTR(&memmap->txfreebufend) | BUFF_STATUS_EMPTY);
1965 // Initialise the transmit free buffer count
1966 wr_regw (dev, TX_FREE_BUFFER_COUNT_OFF, BUFN3_SIZE);
1968 printk (" rx channels");
1970 // Initialise all of the receive channels to be AAL5 disabled with
1971 // an interrupt threshold of 0
1973 for (chan = 0; chan < RX_CHANS; ++chan) {
1974 rx_ch_desc * rx_desc = &memmap->rx_descs[chan];
1976 wr_mem (dev, &rx_desc->wr_buf_type, CHANNEL_TYPE_AAL5 | RX_CHANNEL_DISABLED);
1979 printk (" rx buffers");
1981 // Use space bufn4 at the moment for rx buffers
1983 rx_desc = memmap->bufn4;
1985 wr_mem (dev, &memmap->rxfreebufstart.next, BUF_PTR(rx_desc) | BUFF_STATUS_EMPTY);
1987 for (buff_count = 0; buff_count < BUFN4_SIZE-1; buff_count++) {
1988 wr_mem (dev, &rx_desc->next, BUF_PTR(rx_desc+1) | BUFF_STATUS_EMPTY);
1993 wr_mem (dev, &rx_desc->next, BUF_PTR(&memmap->rxfreebufend) | BUFF_STATUS_EMPTY);
1995 // Initialise the receive free buffer count
1996 wr_regw (dev, RX_FREE_BUFFER_COUNT_OFF, BUFN4_SIZE);
1998 // Initialize Horizons registers
2001 wr_regw (dev, TX_CONFIG_OFF,
2002 ABR_ROUND_ROBIN | TX_NORMAL_OPERATION | DRVR_DRVRBAR_ENABLE);
2004 // RX config. Use 10-x VC bits, x VP bits, non user cells in channel 0.
2005 wr_regw (dev, RX_CONFIG_OFF,
2006 DISCARD_UNUSED_VPI_VCI_BITS_SET | NON_USER_CELLS_IN_ONE_CHANNEL | vpi_bits);
2009 wr_regw (dev, RX_LINE_CONFIG_OFF,
2010 LOCK_DETECT_ENABLE | FREQUENCY_DETECT_ENABLE | GXTALOUT_SELECT_DIV4);
2012 // Set the max AAL5 cell count to be just enough to contain the
2013 // largest AAL5 frame that the user wants to receive
2014 wr_regw (dev, MAX_AAL5_CELL_COUNT_OFF,
2015 (max_rx_size + ATM_AAL5_TRAILER + ATM_CELL_PAYLOAD - 1) / ATM_CELL_PAYLOAD);
2018 wr_regw (dev, RX_CONFIG_OFF, rd_regw (dev, RX_CONFIG_OFF) | RX_ENABLE);
2020 printk (" control");
2022 // Drive the OE of the LEDs then turn the green LED on
2023 ctrl |= GREEN_LED_OE | YELLOW_LED_OE | GREEN_LED | YELLOW_LED;
2024 wr_regl (dev, CONTROL_0_REG, ctrl);
2026 // Test for a 155-capable card
2029 // Select 155 mode... make this a choice (or: how do we detect
2030 // external line speed and switch?)
2031 ctrl |= ATM_LAYER_SELECT;
2032 wr_regl (dev, CONTROL_0_REG, ctrl);
2034 // test SUNI-lite vs SAMBA
2036 // Register 0x00 in the SUNI will have some of bits 3-7 set, and
2037 // they will always be zero for the SAMBA. Ha! Bloody hardware
2038 // engineers. It'll never work.
2040 if (rd_framer (dev, 0) & 0x00f0) {
2044 // Reset, just in case
2045 wr_framer (dev, 0x00, 0x0080);
2046 wr_framer (dev, 0x00, 0x0000);
2048 // Configure transmit FIFO
2049 wr_framer (dev, 0x63, rd_framer (dev, 0x63) | 0x0002);
2051 // Set line timed mode
2052 wr_framer (dev, 0x05, rd_framer (dev, 0x05) | 0x0001);
2057 // Reset, just in case
2058 wr_framer (dev, 0, rd_framer (dev, 0) | 0x0001);
2059 wr_framer (dev, 0, rd_framer (dev, 0) &~ 0x0001);
2061 // Turn off diagnostic loopback and enable line-timed mode
2062 wr_framer (dev, 0, 0x0002);
2064 // Turn on transmit outputs
2065 wr_framer (dev, 2, 0x0B80);
2069 ctrl &= ~ATM_LAYER_SELECT;
2085 u8 * esi = dev->atm_dev->esi;
2087 // in the card I have, EEPROM
2088 // addresses 0, 1, 2 contain 0
2089 // addresess 5, 6 etc. contain ffff
2090 // NB: Madge prefix is 00 00 f6 (which is 00 00 6f in Ethernet bit order)
2091 // the read_bia routine gets the BIA in Ethernet bit order
2093 for (i=0; i < ESI_LEN; ++i) {
2095 b = read_bia (dev, i/2 + 2);
2099 printk ("%02x", esi[i]);
2103 // Enable RX_Q and ?X_COMPLETE interrupts only
2104 wr_regl (dev, INT_ENABLE_REG_OFF, INTERESTING_INTERRUPTS);
2112 /********** check max_sdu **********/
2114 static int check_max_sdu (hrz_aal aal, struct atm_trafprm * tp, unsigned int max_frame_size) {
2115 PRINTD (DBG_FLOW|DBG_QOS, "check_max_sdu");
2119 if (!(tp->max_sdu)) {
2120 PRINTD (DBG_QOS, "defaulting max_sdu");
2121 tp->max_sdu = ATM_AAL0_SDU;
2122 } else if (tp->max_sdu != ATM_AAL0_SDU) {
2123 PRINTD (DBG_QOS|DBG_ERR, "rejecting max_sdu");
2128 if (tp->max_sdu == 0 || tp->max_sdu > ATM_MAX_AAL34_PDU) {
2129 PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default");
2130 tp->max_sdu = ATM_MAX_AAL34_PDU;
2134 if (tp->max_sdu == 0 || tp->max_sdu > max_frame_size) {
2135 PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default");
2136 tp->max_sdu = max_frame_size;
2143 /********** check pcr **********/
2145 // something like this should be part of ATM Linux
2146 static int atm_pcr_check (struct atm_trafprm * tp, unsigned int pcr) {
2147 // we are assuming non-UBR, and non-special values of pcr
2148 if (tp->min_pcr == ATM_MAX_PCR)
2149 PRINTD (DBG_QOS, "luser gave min_pcr = ATM_MAX_PCR");
2150 else if (tp->min_pcr < 0)
2151 PRINTD (DBG_QOS, "luser gave negative min_pcr");
2152 else if (tp->min_pcr && tp->min_pcr > pcr)
2153 PRINTD (DBG_QOS, "pcr less than min_pcr");
2155 // !! max_pcr = UNSPEC (0) is equivalent to max_pcr = MAX (-1)
2156 // easier to #define ATM_MAX_PCR 0 and have all rates unsigned?
2157 // [this would get rid of next two conditionals]
2158 if ((0) && tp->max_pcr == ATM_MAX_PCR)
2159 PRINTD (DBG_QOS, "luser gave max_pcr = ATM_MAX_PCR");
2160 else if ((tp->max_pcr != ATM_MAX_PCR) && tp->max_pcr < 0)
2161 PRINTD (DBG_QOS, "luser gave negative max_pcr");
2162 else if (tp->max_pcr && tp->max_pcr != ATM_MAX_PCR && tp->max_pcr < pcr)
2163 PRINTD (DBG_QOS, "pcr greater than max_pcr");
2165 // each limit unspecified or not violated
2166 PRINTD (DBG_QOS, "xBR(pcr) OK");
2169 PRINTD (DBG_QOS, "pcr=%u, tp: min_pcr=%d, pcr=%d, max_pcr=%d",
2170 pcr, tp->min_pcr, tp->pcr, tp->max_pcr);
2174 /********** open VC **********/
2176 static int hrz_open (struct atm_vcc * atm_vcc, short vpi, int vci) {
2180 struct atm_qos * qos;
2181 struct atm_trafprm * txtp;
2182 struct atm_trafprm * rxtp;
2184 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2186 hrz_vcc * vccp; // allocated late
2187 PRINTD (DBG_FLOW|DBG_VCC, "hrz_open %x %x", vpi, vci);
2189 #ifdef ATM_VPI_UNSPEC
2190 // UNSPEC is deprecated, remove this code eventually
2191 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) {
2192 PRINTK (KERN_WARNING, "rejecting open with unspecified VPI/VCI (deprecated)");
2197 // deal with possibly wildcarded VCs
2198 error = atm_find_ci (atm_vcc, &vpi, &vci);
2200 PRINTD (DBG_WARN|DBG_VCC, "atm_find_ci failed!");
2203 PRINTD (DBG_VCC, "atm_find_ci gives %x %x", vpi, vci);
2205 error = vpivci_to_channel (&channel, vpi, vci);
2207 PRINTD (DBG_WARN|DBG_VCC, "VPI/VCI out of range: %hd/%d", vpi, vci);
2211 vcc.channel = channel;
2212 // max speed for the moment
2215 qos = &atm_vcc->qos;
2217 // check AAL and remember it
2220 // we would if it were 48 bytes and not 52!
2221 PRINTD (DBG_QOS|DBG_VCC, "AAL0");
2225 // we would if I knew how do the SAR!
2226 PRINTD (DBG_QOS|DBG_VCC, "AAL3/4");
2230 PRINTD (DBG_QOS|DBG_VCC, "AAL5");
2234 PRINTD (DBG_QOS|DBG_VCC, "Bad AAL!");
2239 // TX traffic parameters
2241 // there are two, interrelated problems here: 1. the reservation of
2242 // PCR is not a binary choice, we are given bounds and/or a
2243 // desirable value; 2. the device is only capable of certain values,
2244 // most of which are not integers. It is almost certainly acceptable
2245 // to be off by a maximum of 1 to 10 cps.
2247 // Pragmatic choice: always store an integral PCR as that which has
2248 // been allocated, even if we allocate a little (or a lot) less,
2249 // after rounding. The actual allocation depends on what we can
2250 // manage with our rate selection algorithm. The rate selection
2251 // algorithm is given an integral PCR and a tolerance and told
2252 // whether it should round the value up or down if the tolerance is
2253 // exceeded; it returns: a) the actual rate selected (rounded up to
2254 // the nearest integer), b) a bit pattern to feed to the timer
2255 // register, and c) a failure value if no applicable rate exists.
2257 // Part of the job is done by atm_pcr_goal which gives us a PCR
2258 // specification which says: EITHER grab the maximum available PCR
2259 // (and perhaps a lower bound which we musn't pass), OR grab this
2260 // amount, rounding down if you have to (and perhaps a lower bound
2261 // which we musn't pass) OR grab this amount, rounding up if you
2262 // have to (and perhaps an upper bound which we musn't pass). If any
2263 // bounds ARE passed we fail. Note that rounding is only rounding to
2264 // match device limitations, we do not round down to satisfy
2265 // bandwidth availability even if this would not violate any given
2268 // Note: telephony = 64kb/s = 48 byte cell payload @ 500/3 cells/s
2269 // (say) so this is not even a binary fixpoint cell rate (but this
2270 // device can do it). To avoid this sort of hassle we use a
2271 // tolerance parameter (currently fixed at 10 cps).
2273 PRINTD (DBG_QOS, "TX:");
2277 // set up defaults for no traffic
2279 // who knows what would actually happen if you try and send on this?
2280 vcc.tx_xbr_bits = IDLE_RATE_TYPE;
2281 vcc.tx_pcr_bits = CLOCK_DISABLE;
2283 vcc.tx_scr_bits = CLOCK_DISABLE;
2284 vcc.tx_bucket_bits = 0;
2287 if (txtp->traffic_class != ATM_NONE) {
2288 error = check_max_sdu (vcc.aal, txtp, max_tx_size);
2290 PRINTD (DBG_QOS, "TX max_sdu check failed");
2294 switch (txtp->traffic_class) {
2296 // we take "the PCR" as a rate-cap
2299 make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, 0);
2300 vcc.tx_xbr_bits = ABR_RATE_TYPE;
2305 // reserve min, allow up to max
2306 vcc.tx_rate = 0; // ?
2307 make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, 0);
2308 vcc.tx_xbr_bits = ABR_RATE_TYPE;
2313 int pcr = atm_pcr_goal (txtp);
2316 // down vs. up, remaining bandwidth vs. unlimited bandwidth!!
2317 // should really have: once someone gets unlimited bandwidth
2318 // that no more non-UBR channels can be opened until the
2319 // unlimited one closes?? For the moment, round_down means
2320 // greedy people actually get something and not nothing
2322 // slight race (no locking) here so we may get -EAGAIN
2323 // later; the greedy bastards would deserve it :)
2324 PRINTD (DBG_QOS, "snatching all remaining TX bandwidth");
2325 pcr = dev->tx_avail;
2326 } else if (pcr < 0) {
2332 error = make_rate_with_tolerance (dev, pcr, r, 10,
2333 &vcc.tx_pcr_bits, &vcc.tx_rate);
2335 PRINTD (DBG_QOS, "could not make rate from TX PCR");
2338 // not really clear what further checking is needed
2339 error = atm_pcr_check (txtp, vcc.tx_rate);
2341 PRINTD (DBG_QOS, "TX PCR failed consistency check");
2344 vcc.tx_xbr_bits = CBR_RATE_TYPE;
2349 int pcr = atm_pcr_goal (txtp);
2350 // int scr = atm_scr_goal (txtp);
2351 int scr = pcr/2; // just for fun
2352 unsigned int mbs = 60; // just for fun
2355 unsigned int bucket;
2359 } else if (pcr < 0) {
2365 error = make_rate_with_tolerance (dev, pcr, pr, 10,
2366 &vcc.tx_pcr_bits, 0);
2368 // see comments for PCR with CBR above
2370 // slight race (no locking) here so we may get -EAGAIN
2371 // later; the greedy bastards would deserve it :)
2372 PRINTD (DBG_QOS, "snatching all remaining TX bandwidth");
2373 scr = dev->tx_avail;
2374 } else if (scr < 0) {
2380 error = make_rate_with_tolerance (dev, scr, sr, 10,
2381 &vcc.tx_scr_bits, &vcc.tx_rate);
2383 PRINTD (DBG_QOS, "could not make rate from TX SCR");
2386 // not really clear what further checking is needed
2387 // error = atm_scr_check (txtp, vcc.tx_rate);
2389 PRINTD (DBG_QOS, "TX SCR failed consistency check");
2392 // bucket calculations (from a piece of paper...) cell bucket
2393 // capacity must be largest integer smaller than m(p-s)/p + 1
2394 // where m = max burst size, p = pcr, s = scr
2395 bucket = mbs*(pcr-scr)/pcr;
2396 if (bucket*pcr != mbs*(pcr-scr))
2398 if (bucket > BUCKET_MAX_SIZE) {
2399 PRINTD (DBG_QOS, "shrinking bucket from %u to %u",
2400 bucket, BUCKET_MAX_SIZE);
2401 bucket = BUCKET_MAX_SIZE;
2403 vcc.tx_xbr_bits = VBR_RATE_TYPE;
2404 vcc.tx_bucket_bits = bucket;
2409 PRINTD (DBG_QOS, "unsupported TX traffic class");
2416 // RX traffic parameters
2418 PRINTD (DBG_QOS, "RX:");
2422 // set up defaults for no traffic
2425 if (rxtp->traffic_class != ATM_NONE) {
2426 error = check_max_sdu (vcc.aal, rxtp, max_rx_size);
2428 PRINTD (DBG_QOS, "RX max_sdu check failed");
2431 switch (rxtp->traffic_class) {
2439 vcc.rx_rate = 0; // ?
2444 int pcr = atm_pcr_goal (rxtp);
2446 // slight race (no locking) here so we may get -EAGAIN
2447 // later; the greedy bastards would deserve it :)
2448 PRINTD (DBG_QOS, "snatching all remaining RX bandwidth");
2449 pcr = dev->rx_avail;
2450 } else if (pcr < 0) {
2454 // not really clear what further checking is needed
2455 error = atm_pcr_check (rxtp, vcc.rx_rate);
2457 PRINTD (DBG_QOS, "RX PCR failed consistency check");
2464 // int scr = atm_scr_goal (rxtp);
2465 int scr = 1<<16; // just for fun
2467 // slight race (no locking) here so we may get -EAGAIN
2468 // later; the greedy bastards would deserve it :)
2469 PRINTD (DBG_QOS, "snatching all remaining RX bandwidth");
2470 scr = dev->rx_avail;
2471 } else if (scr < 0) {
2475 // not really clear what further checking is needed
2476 // error = atm_scr_check (rxtp, vcc.rx_rate);
2478 PRINTD (DBG_QOS, "RX SCR failed consistency check");
2485 PRINTD (DBG_QOS, "unsupported RX traffic class");
2493 // late abort useful for diagnostics
2494 if (vcc.aal != aal5) {
2495 PRINTD (DBG_QOS, "AAL not supported");
2499 // get space for our vcc stuff and copy parameters into it
2500 vccp = kmalloc (sizeof(hrz_vcc), GFP_KERNEL);
2502 PRINTK (KERN_ERR, "out of memory!");
2507 // clear error and grab cell rate resource lock
2509 spin_lock (&dev->rate_lock);
2511 if (vcc.tx_rate > dev->tx_avail) {
2512 PRINTD (DBG_QOS, "not enough TX PCR left");
2516 if (vcc.rx_rate > dev->rx_avail) {
2517 PRINTD (DBG_QOS, "not enough RX PCR left");
2522 // really consume cell rates
2523 dev->tx_avail -= vcc.tx_rate;
2524 dev->rx_avail -= vcc.rx_rate;
2525 PRINTD (DBG_QOS|DBG_VCC, "reserving %u TX PCR and %u RX PCR",
2526 vcc.tx_rate, vcc.rx_rate);
2529 // release lock and exit on error
2530 spin_unlock (&dev->rate_lock);
2532 PRINTD (DBG_QOS|DBG_VCC, "insufficient cell rate resources");
2537 // this is "immediately before allocating the connection identifier
2538 // in hardware" - so long as the next call does not fail :)
2539 set_bit(ATM_VF_ADDR,&atm_vcc->flags);
2541 // any errors here are very serious and should never occur
2543 if (rxtp->traffic_class != ATM_NONE) {
2544 if (dev->rxer[channel]) {
2545 PRINTD (DBG_ERR|DBG_VCC, "VC already open for RX");
2549 error = hrz_open_rx (dev, channel);
2554 // this link allows RX frames through
2555 dev->rxer[channel] = atm_vcc;
2558 // success, set elements of atm_vcc
2561 atm_vcc->dev_data = (void *) vccp;
2563 // indicate readiness
2564 set_bit(ATM_VF_READY,&atm_vcc->flags);
2569 /********** close VC **********/
2571 static void hrz_close (struct atm_vcc * atm_vcc) {
2572 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2573 hrz_vcc * vcc = HRZ_VCC(atm_vcc);
2574 u16 channel = vcc->channel;
2575 PRINTD (DBG_VCC|DBG_FLOW, "hrz_close");
2577 // indicate unreadiness
2578 clear_bit(ATM_VF_READY,&atm_vcc->flags);
2580 if (atm_vcc->qos.txtp.traffic_class != ATM_NONE) {
2583 // let any TX on this channel that has started complete
2584 // no restart, just keep trying
2585 while (tx_hold (dev))
2587 // remove record of any tx_channel having been setup for this channel
2588 for (i = 0; i < TX_CHANS; ++i)
2589 if (dev->tx_channel_record[i] == channel) {
2590 dev->tx_channel_record[i] = -1;
2593 if (dev->last_vc == channel)
2598 if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) {
2599 // disable RXing - it tries quite hard
2600 hrz_close_rx (dev, channel);
2601 // forget the vcc - no more skbs will be pushed
2602 if (atm_vcc != dev->rxer[channel])
2603 PRINTK (KERN_ERR, "%s atm_vcc=%p rxer[channel]=%p",
2604 "arghhh! we're going to die!",
2605 atm_vcc, dev->rxer[channel]);
2606 dev->rxer[channel] = 0;
2609 // atomically release our rate reservation
2610 spin_lock (&dev->rate_lock);
2611 PRINTD (DBG_QOS|DBG_VCC, "releasing %u TX PCR and %u RX PCR",
2612 vcc->tx_rate, vcc->rx_rate);
2613 dev->tx_avail += vcc->tx_rate;
2614 dev->rx_avail += vcc->rx_rate;
2615 spin_unlock (&dev->rate_lock);
2617 // free our structure
2619 // say the VPI/VCI is free again
2620 clear_bit(ATM_VF_ADDR,&atm_vcc->flags);
2624 static int hrz_getsockopt (struct atm_vcc * atm_vcc, int level, int optname,
2625 void *optval, int optlen) {
2626 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2627 PRINTD (DBG_FLOW|DBG_VCC, "hrz_getsockopt");
2636 return -ENOPROTOOPT;
2644 static int hrz_setsockopt (struct atm_vcc * atm_vcc, int level, int optname,
2645 void *optval, int optlen) {
2646 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2647 PRINTD (DBG_FLOW|DBG_VCC, "hrz_setsockopt");
2656 return -ENOPROTOOPT;
2665 static int hrz_sg_send (struct atm_vcc * atm_vcc,
2666 unsigned long start,
2667 unsigned long size) {
2668 if (atm_vcc->qos.aal == ATM_AAL5) {
2669 PRINTD (DBG_FLOW|DBG_VCC, "hrz_sg_send: yes");
2672 PRINTD (DBG_FLOW|DBG_VCC, "hrz_sg_send: no");
2678 static int hrz_ioctl (struct atm_dev * atm_dev, unsigned int cmd, void *arg) {
2679 hrz_dev * dev = HRZ_DEV(atm_dev);
2680 PRINTD (DBG_FLOW, "hrz_ioctl");
2684 unsigned char hrz_phy_get (struct atm_dev * atm_dev, unsigned long addr) {
2685 hrz_dev * dev = HRZ_DEV(atm_dev);
2686 PRINTD (DBG_FLOW, "hrz_phy_get");
2690 static void hrz_phy_put (struct atm_dev * atm_dev, unsigned char value,
2691 unsigned long addr) {
2692 hrz_dev * dev = HRZ_DEV(atm_dev);
2693 PRINTD (DBG_FLOW, "hrz_phy_put");
2696 static int hrz_change_qos (struct atm_vcc * atm_vcc, struct atm_qos *qos, int flgs) {
2697 hrz_dev * dev = HRZ_DEV(vcc->dev);
2698 PRINTD (DBG_FLOW, "hrz_change_qos");
2703 /********** proc file contents **********/
2705 static int hrz_proc_read (struct atm_dev * atm_dev, loff_t * pos, char * page) {
2706 hrz_dev * dev = HRZ_DEV(atm_dev);
2708 PRINTD (DBG_FLOW, "hrz_proc_read");
2710 /* more diagnostics here? */
2714 unsigned int count = sprintf (page, "vbr buckets:");
2716 for (i = 0; i < TX_CHANS; ++i)
2717 count += sprintf (page, " %u/%u",
2718 query_tx_channel_config (dev, i, BUCKET_FULLNESS_ACCESS),
2719 query_tx_channel_config (dev, i, BUCKET_CAPACITY_ACCESS));
2720 count += sprintf (page+count, ".\n");
2726 return sprintf (page,
2727 "cells: TX %lu, RX %lu, HEC errors %lu, unassigned %lu.\n",
2728 dev->tx_cell_count, dev->rx_cell_count,
2729 dev->hec_error_count, dev->unassigned_cell_count);
2732 return sprintf (page,
2733 "free cell buffers: TX %hu, RX %hu+%hu.\n",
2734 rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF),
2735 rd_regw (dev, RX_FREE_BUFFER_COUNT_OFF),
2736 dev->noof_spare_buffers);
2739 return sprintf (page,
2740 "cps remaining: TX %u, RX %u\n",
2741 dev->tx_avail, dev->rx_avail);
2746 static const struct atmdev_ops hrz_ops = {
2750 sg_send: hrz_sg_send,
2751 proc_read: hrz_proc_read,
2755 static int __init hrz_probe (void) {
2756 struct pci_dev * pci_dev;
2759 PRINTD (DBG_FLOW, "hrz_probe");
2763 while ((pci_dev = pci_find_device
2764 (PCI_VENDOR_ID_MADGE, PCI_DEVICE_ID_MADGE_HORIZON, pci_dev)
2768 // adapter slot free, read resources from PCI configuration space
2769 u32 iobase = pci_resource_start (pci_dev, 0);
2770 u32 * membase = bus_to_virt (pci_resource_start (pci_dev, 1));
2771 u8 irq = pci_dev->irq;
2773 /* XXX DEV_LABEL is a guess */
2774 if (!request_region (iobase, HRZ_IO_EXTENT, DEV_LABEL))
2777 if (pci_enable_device (pci_dev))
2780 dev = kmalloc (sizeof(hrz_dev), GFP_KERNEL);
2782 // perhaps we should be nice: deregister all adapters and abort?
2783 PRINTD (DBG_ERR, "out of memory");
2787 memset (dev, 0, sizeof(hrz_dev));
2789 // grab IRQ and install handler - move this someplace more sensible
2790 if (request_irq (irq,
2792 SA_SHIRQ, /* irqflags guess */
2793 DEV_LABEL, /* name guess */
2795 PRINTD (DBG_WARN, "request IRQ failed!");
2796 // free_irq is at "endif"
2799 PRINTD (DBG_INFO, "found Madge ATM adapter (hrz) at: IO %x, IRQ %u, MEM %p",
2800 iobase, irq, membase);
2802 dev->atm_dev = atm_dev_register (DEV_LABEL, &hrz_ops, -1, NULL);
2803 if (!(dev->atm_dev)) {
2804 PRINTD (DBG_ERR, "failed to register Madge ATM adapter");
2808 PRINTD (DBG_INFO, "registered Madge ATM adapter (no. %d) (%p) at %p",
2809 dev->atm_dev->number, dev, dev->atm_dev);
2810 dev->atm_dev->dev_data = (void *) dev;
2811 dev->pci_dev = pci_dev;
2813 // enable bus master accesses
2814 pci_set_master (pci_dev);
2816 // frobnicate latency (upwards, usually)
2817 pci_read_config_byte (pci_dev, PCI_LATENCY_TIMER, &lat);
2819 PRINTD (DBG_INFO, "%s PCI latency timer from %hu to %hu",
2820 "changing", lat, pci_lat);
2821 pci_write_config_byte (pci_dev, PCI_LATENCY_TIMER, pci_lat);
2822 } else if (lat < MIN_PCI_LATENCY) {
2823 PRINTK (KERN_INFO, "%s PCI latency timer from %hu to %hu",
2824 "increasing", lat, MIN_PCI_LATENCY);
2825 pci_write_config_byte (pci_dev, PCI_LATENCY_TIMER, MIN_PCI_LATENCY);
2828 dev->iobase = iobase;
2830 dev->membase = membase;
2832 dev->rx_q_entry = dev->rx_q_reset = &memmap->rx_q_entries[0];
2833 dev->rx_q_wrap = &memmap->rx_q_entries[RX_CHANS-1];
2835 // these next three are performance hacks
2840 dev->tx_regions = 0;
2845 dev->tx_cell_count = 0;
2846 dev->rx_cell_count = 0;
2847 dev->hec_error_count = 0;
2848 dev->unassigned_cell_count = 0;
2850 dev->noof_spare_buffers = 0;
2854 for (i = 0; i < TX_CHANS; ++i)
2855 dev->tx_channel_record[i] = -1;
2860 // Allocate cell rates and remember ASIC version
2861 // Fibre: ATM_OC3_PCR = 1555200000/8/270*260/53 - 29/53
2862 // Copper: (WRONG) we want 6 into the above, close to 25Mb/s
2863 // Copper: (plagarise!) 25600000/8/270*260/53 - n/53
2865 if (hrz_init (dev)) {
2866 // to be really pedantic, this should be ATM_OC3c_PCR
2867 dev->tx_avail = ATM_OC3_PCR;
2868 dev->rx_avail = ATM_OC3_PCR;
2869 set_bit (ultra, &dev->flags); // NOT "|= ultra" !
2871 dev->tx_avail = ((25600000/8)*26)/(27*53);
2872 dev->rx_avail = ((25600000/8)*26)/(27*53);
2873 PRINTD (DBG_WARN, "Buggy ASIC: no TX bus-mastering.");
2876 // rate changes spinlock
2877 spin_lock_init (&dev->rate_lock);
2879 // on-board memory access spinlock; we want atomic reads and
2880 // writes to adapter memory (handles IRQ and SMP)
2881 spin_lock_init (&dev->mem_lock);
2883 #if LINUX_VERSION_CODE >= 0x20303
2884 init_waitqueue_head (&dev->tx_queue);
2889 // vpi in 0..4, vci in 6..10
2890 dev->atm_dev->ci_range.vpi_bits = vpi_bits;
2891 dev->atm_dev->ci_range.vci_bits = 10-vpi_bits;
2893 // update count and linked list
2895 dev->prev = hrz_devs;
2900 /* not currently reached */
2901 atm_dev_deregister (dev->atm_dev);
2902 } /* atm_dev_register */
2903 free_irq (irq, dev);
2907 release_region(iobase, HRZ_IO_EXTENT);
2908 } /* kmalloc and while */
2912 static void __init hrz_check_args (void) {
2913 #ifdef DEBUG_HORIZON
2914 PRINTK (KERN_NOTICE, "debug bitmap is %hx", debug &= DBG_MASK);
2917 PRINTK (KERN_NOTICE, "no debug support in this image");
2920 if (vpi_bits > HRZ_MAX_VPI)
2921 PRINTK (KERN_ERR, "vpi_bits has been limited to %hu",
2922 vpi_bits = HRZ_MAX_VPI);
2924 if (max_tx_size < 0 || max_tx_size > TX_AAL5_LIMIT)
2925 PRINTK (KERN_NOTICE, "max_tx_size has been limited to %hu",
2926 max_tx_size = TX_AAL5_LIMIT);
2928 if (max_rx_size < 0 || max_rx_size > RX_AAL5_LIMIT)
2929 PRINTK (KERN_NOTICE, "max_rx_size has been limited to %hu",
2930 max_rx_size = RX_AAL5_LIMIT);
2938 MODULE_AUTHOR(maintainer_string);
2939 MODULE_DESCRIPTION(description_string);
2940 MODULE_LICENSE("GPL");
2941 MODULE_PARM(debug, "h");
2942 MODULE_PARM(vpi_bits, "h");
2943 MODULE_PARM(max_tx_size, "i");
2944 MODULE_PARM(max_rx_size, "i");
2945 MODULE_PARM(pci_lat, "b");
2946 MODULE_PARM_DESC(debug, "debug bitmap, see .h file");
2947 MODULE_PARM_DESC(vpi_bits, "number of bits (0..4) to allocate to VPIs");
2948 MODULE_PARM_DESC(max_tx_size, "maximum size of TX AAL5 frames");
2949 MODULE_PARM_DESC(max_rx_size, "maximum size of RX AAL5 frames");
2950 MODULE_PARM_DESC(pci_lat, "PCI latency in bus cycles");
2952 /********** module entry **********/
2954 int init_module (void) {
2957 // sanity check - cast is needed since printk does not support %Zu
2958 if (sizeof(struct MEMMAP) != 128*1024/4) {
2959 PRINTK (KERN_ERR, "Fix struct MEMMAP (is %lu fakewords).",
2960 (unsigned long) sizeof(struct MEMMAP));
2973 init_timer (&housekeeping);
2974 housekeeping.function = do_housekeeping;
2976 housekeeping.data = 1;
2977 set_timer (&housekeeping, 0);
2979 PRINTK (KERN_ERR, "no (usable) adapters found");
2982 return devs ? 0 : -ENODEV;
2985 /********** module exit **********/
2987 void cleanup_module (void) {
2989 PRINTD (DBG_FLOW, "cleanup_module");
2992 housekeeping.data = 0;
2993 del_timer (&housekeeping);
2997 hrz_devs = dev->prev;
2999 PRINTD (DBG_INFO, "closing %p (atm_dev = %p)", dev, dev->atm_dev);
3001 atm_dev_deregister (dev->atm_dev);
3002 free_irq (dev->irq, dev);
3003 release_region (dev->iobase, HRZ_IO_EXTENT);
3012 /********** monolithic entry **********/
3014 int __init hrz_detect (void) {
3017 // sanity check - cast is needed since printk does not support %Zu
3018 if (sizeof(struct MEMMAP) != 128*1024/4) {
3019 PRINTK (KERN_ERR, "Fix struct MEMMAP (is %lu fakewords).",
3020 (unsigned long) sizeof(struct MEMMAP));
3026 // what about command line arguments?
3034 init_timer (&housekeeping);
3035 housekeeping.function = do_housekeeping;
3037 housekeeping.data = 1;
3038 set_timer (&housekeeping, 0);
3040 PRINTK (KERN_ERR, "no (usable) adapters found");