drivers/block/cciss.h

   1 #ifndef CCISS_H
   2 #define CCISS_H
   3
   4 #include <linux/genhd.h>
   5
   6 #include "cciss_cmd.h"
   7
   8
   9 #define NWD             16
  10 #define NWD_SHIFT       4
  11 #define MAX_PART        16
  12
  13 #define IO_OK           0
  14 #define IO_ERROR        1
  15
  16 #define MAJOR_NR COMPAQ_CISS_MAJOR
  17
  18 struct ctlr_info;
  19 typedef struct ctlr_info ctlr_info_t;
  20
  21 struct access_method {
  22         void (*submit_command)(ctlr_info_t *h, CommandList_struct *c);
  23         void (*set_intr_mask)(ctlr_info_t *h, unsigned long val);
  24         unsigned long (*fifo_full)(ctlr_info_t *h);
  25         unsigned long (*intr_pending)(ctlr_info_t *h);
  26         unsigned long (*command_completed)(ctlr_info_t *h);
  27 };
  28 typedef struct _drive_info_struct
  29 {
  30         __u32           LunID;
  31         int             usage_count;
  32         unsigned int    nr_blocks;
  33         int             block_size;
  34         int             heads;
  35         int             sectors;
  36         int             cylinders;
  37         int             raid_level;
  38 } drive_info_struct;
  39
  40 struct ctlr_info
  41 {
  42         int     ctlr;
  43         char    devname[8];
  44         char    *product_name;
  45         char    firm_ver[4]; // Firmware version
  46         struct pci_dev *pdev;
  47         __u32   board_id;
  48         ulong   vaddr;
  49         __u32   paddr;
  50         unsigned long io_mem_addr;
  51         unsigned long io_mem_length;
  52         CfgTable_struct *cfgtable;
  53         int     intr;
  54
  55         int     max_commands;
  56         int     commands_outstanding;
  57         int     max_outstanding; /* Debug */
  58         int     num_luns;
  59         int     highest_lun;
  60         int     usage_count;  /* number of opens all all minor devices */
  61
  62         // information about each logical volume
  63         drive_info_struct drv[CISS_MAX_LUN];
  64
  65         struct access_method access;
  66
  67         /* queue and queue Info */
  68         CommandList_struct *reqQ;
  69         CommandList_struct  *cmpQ;
  70         unsigned int Qdepth;
  71         unsigned int maxQsinceinit;
  72         unsigned int maxSG;
  73
  74         //* pointers to command and error info pool */
  75         CommandList_struct      *cmd_pool;
  76         dma_addr_t              cmd_pool_dhandle;
  77         ErrorInfo_struct        *errinfo_pool;
  78         dma_addr_t              errinfo_pool_dhandle;
  79         __u32                   *cmd_pool_bits;
  80         int                     nr_allocs;
  81         int                     nr_frees;
  82
  83         // Disk structures we need to pass back
  84         struct gendisk   gendisk;
  85            // indexed by minor numbers
  86         struct hd_struct hd[256];
  87         int              sizes[256];
  88         int              blocksizes[256];
  89         int              hardsizes[256];
  90         int busy_configuring;
  91 #ifdef CONFIG_CISS_SCSI_TAPE
  92         void *scsi_ctlr; /* ptr to structure containing scsi related stuff */
  93 #endif
  94 };
  95
  96 /*  Defining the diffent access_menthods */
  97 /*
  98  * Memory mapped FIFO interface (SMART 53xx cards)
  99  */
 100 #define SA5_DOORBELL    0x20
 101 #define SA5_REQUEST_PORT_OFFSET 0x40
 102 #define SA5_REPLY_INTR_MASK_OFFSET      0x34
 103 #define SA5_REPLY_PORT_OFFSET           0x44
 104 #define SA5_INTR_STATUS         0x30
 105
 106 #define SA5_CTCFG_OFFSET        0xB4
 107 #define SA5_CTMEM_OFFSET        0xB8
 108
 109 #define SA5_INTR_OFF            0x08
 110 #define SA5B_INTR_OFF           0x04
 111 #define SA5_INTR_PENDING        0x08
 112 #define SA5B_INTR_PENDING       0x04
 113 #define FIFO_EMPTY              0xffffffff
 114
 115 #define  CISS_ERROR_BIT         0x02
 116
 117 #define CCISS_INTR_ON   1
 118 #define CCISS_INTR_OFF  0
 119 /*
 120         Send the command to the hardware
 121 */
 122 static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c)
 123 {
 124 #ifdef CCISS_DEBUG
 125          printk("Sending %x - down to controller\n", c->busaddr );
 126 #endif /* CCISS_DEBUG */
 127          writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
 128          h->commands_outstanding++;
 129          if ( h->commands_outstanding > h->max_outstanding)
 130                 h->max_outstanding = h->commands_outstanding;
 131 }
 132
 133 /*
 134  *  This card is the opposite of the other cards.
 135  *   0 turns interrupts on...
 136  *   0x08 turns them off...
 137  */
 138 static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)
 139 {
 140         if (val)
 141         { /* Turn interrupts on */
 142                 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 143         } else /* Turn them off */
 144         {
 145                 writel( SA5_INTR_OFF,
 146                         h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 147         }
 148 }
 149 /*
 150  *  This card is the opposite of the other cards.
 151  *   0 turns interrupts on...
 152  *   0x04 turns them off...
 153  */
 154 static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)
 155 {
 156         if (val)
 157         { /* Turn interrupts on */
 158                 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 159         } else /* Turn them off */
 160         {
 161                 writel( SA5B_INTR_OFF,
 162                         h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 163         }
 164 }
 165 /*
 166  *  Returns true if fifo is full.
 167  *
 168  */
 169 static unsigned long SA5_fifo_full(ctlr_info_t *h)
 170 {
 171         if( h->commands_outstanding >= h->max_commands)
 172                 return(1);
 173         else
 174                 return(0);
 175
 176 }
 177 /*
 178  *   returns value read from hardware.
 179  *     returns FIFO_EMPTY if there is nothing to read
 180  */
 181 static unsigned long SA5_completed(ctlr_info_t *h)
 182 {
 183         unsigned long register_value
 184                 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
 185         if(register_value != FIFO_EMPTY)
 186         {
 187                 h->commands_outstanding--;
 188 #ifdef CCISS_DEBUG
 189                 printk("cciss:  Read %lx back from board\n", register_value);
 190 #endif /* CCISS_DEBUG */
 191         }
 192 #ifdef CCISS_DEBUG
 193         else
 194         {
 195                 printk("cciss:  FIFO Empty read\n");
 196         }
 197 #endif
 198         return ( register_value);
 199
 200 }
 201 /*
 202  *      Returns true if an interrupt is pending..
 203  */
 204 static unsigned long SA5_intr_pending(ctlr_info_t *h)
 205 {
 206         unsigned long register_value  =
 207                 readl(h->vaddr + SA5_INTR_STATUS);
 208 #ifdef CCISS_DEBUG
 209         printk("cciss: intr_pending %lx\n", register_value);
 210 #endif  /* CCISS_DEBUG */
 211         if( register_value &  SA5_INTR_PENDING)
 212                 return  1;
 213         return 0 ;
 214 }
 215
 216 /*
 217  *      Returns true if an interrupt is pending..
 218  */
 219 static unsigned long SA5B_intr_pending(ctlr_info_t *h)
 220 {
 221         unsigned long register_value  =
 222                 readl(h->vaddr + SA5_INTR_STATUS);
 223 #ifdef CCISS_DEBUG
 224         printk("cciss: intr_pending %lx\n", register_value);
 225 #endif  /* CCISS_DEBUG */
 226         if( register_value &  SA5B_INTR_PENDING)
 227                 return  1;
 228         return 0 ;
 229 }
 230
 231
 232 static struct access_method SA5_access = {
 233         SA5_submit_command,
 234         SA5_intr_mask,
 235         SA5_fifo_full,
 236         SA5_intr_pending,
 237         SA5_completed,
 238 };
 239
 240 static struct access_method SA5B_access = {
 241         SA5_submit_command,
 242         SA5B_intr_mask,
 243         SA5_fifo_full,
 244         SA5B_intr_pending,
 245         SA5_completed,
 246 };
 247
 248 struct board_type {
 249         __u32   board_id;
 250         char    *product_name;
 251         struct access_method *access;
 252 };
 253 #endif /* CCISS_H */
 254