drivers/i2c/i2c-ibm_iic.c

   1 /*
   2  * -------------------------------------------------------------------------
   3  * i2c-ibm_iic.c Support for the IIC peripheral on PPC 4xx
   4  * -------------------------------------------------------------------------
   5  *
   6  * Cleaned and unified by Matt Porter <mporter@mvista.com>
   7  *
   8  * Original driver by Ian DaSilva <idasilva@mvista.com> and Armin Kuster
   9  * <akuster@mvista.com>
  10  *
  11  * Copyright 2000-2003 MontaVista Software Inc.
  12  *
  13  * ----------------------------------------------------------------------------
  14  * This file was highly leveraged from i2c-elektor.c, which was created
  15  * by Simon G. Vogl and Hans Berglund:
  16  *
  17  *
  18  * Copyright 1995-97 Simon G. Vogl
  19  *           1998-99 Hans Berglund
  20  *
  21  * With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and even
  22  * Frodo Looijaard <frodol@dds.nl>
  23
  24  * This program is free software; you can redistribute it and/or modify
  25  * it under the terms of the GNU General Public License as published by
  26  * the Free Software Foundation; either version 2 of the License, or
  27  * (at your option) any later version.
  28  *
  29  * This program is distributed in the hope that it will be useful,
  30  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  31  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  32  * GNU General Public License for more details.
  33  *
  34  *  You should have received a copy of the GNU General Public License
  35  *  along with this program; if not, write to the Free Software
  36  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  37  * ----------------------------------------------------------------------------
  38  */
  39
  40 #include <linux/kernel.h>
  41 #include <linux/ioport.h>
  42 #include <linux/module.h>
  43 #include <linux/delay.h>
  44 #include <linux/slab.h>
  45 #include <linux/version.h>
  46 #include <linux/init.h>
  47 #include <asm/irq.h>
  48 #include <asm/io.h>
  49 #include <linux/i2c.h>
  50 #include <linux/i2c-id.h>
  51 #include <asm/ocp.h>
  52
  53 /*
  54  * This next section is configurable, and it is used to set the number
  55  * of i2c controllers in the system.  The default number of instances is 1,
  56  * however, this should be changed to reflect your system's configuration.
  57  */
  58
  59 static int i2c_debug = 0;
  60 static int iic_scan = 0;        /* have a look at what's hanging 'round */
  61 static wait_queue_head_t iic_wait[2];
  62 static int iic_pending;
  63
  64 #define DEB(x) if (i2c_debug>=1) x
  65 #define DEB2(x) if (i2c_debug>=2) x
  66 #define DEB3(x) if (i2c_debug>=3) x     /* print several statistical values */
  67 #define DEBPROTO(x) if (i2c_debug>=9) x;
  68 /* debug the protocol by showing transferred bits */
  69 #define DEF_TIMEOUT 5
  70
  71 #define IIC_DEV(x)      ((struct ocp_dev *)adap->data)->x
  72
  73 #define iic_outb( reg, val) writeb(val,&(reg))
  74 #define iic_inb( reg) readb(&(reg))
  75
  76 #define IIC_SINGLE_XFER         0
  77 #define IIC_COMBINED_XFER       1
  78
  79 #define IIC_ERR_LOST_ARB        -2
  80 #define IIC_ERR_INCOMPLETE_XFR  -3
  81 #define IIC_ERR_NACK            -1
  82 #define IIC_TIMEOUT             100
  83 #define IIC_RETRY               3
  84
  85 #define IIC_DEV(x)      ((struct ocp_dev *)adap->data)->x
  86
  87 /*
  88  * Determine if there was an error in the requested transaction.
  89  * If so, determine the cause.
  90  */
  91 int
  92 iic_analyze_status(struct i2c_adapter *adap, int *error_code)
  93 {
  94         int ret;
  95         struct iic_regs *iic;
  96
  97         iic = (struct iic_regs *) IIC_DEV(vaddr);
  98
  99         ret = iic_inb(iic->sts);
 100         if (ret & 0x04) {
 101                 /* Error occurred */
 102                 ret = iic_inb(iic->extsts);
 103                 if (ret & 0x04) {
 104                         /* Lost arbitration */
 105                         *error_code = IIC_ERR_LOST_ARB;
 106                 }
 107                 if (ret & 0x02) {
 108                         /* Incomplete transfer */
 109                         *error_code = IIC_ERR_INCOMPLETE_XFR;
 110                 }
 111                 if (ret & 0x01) {
 112                         /* Master transfer aborted by a NACK during the transfer of the address byte */
 113                         *error_code = IIC_ERR_NACK;
 114                 }
 115                 return -1;
 116         }
 117         return 0;
 118 }
 119
 120 /*
 121  * Generate I2C compliant 7-bit address.
 122  *
 123  * Note: 10 bit addresses are not supported in this driver, although they are
 124  * supported by the hardware.  This functionality needs to be implemented.
 125  */
 126 static inline int
 127 iic_do_address(struct i2c_adapter *adap, struct i2c_msg *msg, int retries)
 128 {
 129         struct iic_regs *iic;
 130         unsigned short flags = msg->flags;
 131         unsigned char addr;
 132
 133         iic = (struct iic_regs *) IIC_DEV(vaddr);
 134
 135 /*
 136  * The following segment for 10 bit addresses needs to be ported
 137  */
 138 #if 0
 139         /* Ten bit addresses not supported right now */
 140         if ((flags & I2C_M_TEN)) {
 141                 /* a ten bit address */
 142                 addr = 0xf0 | ((msg->addr >> 7) & 0x03);
 143                 DEB2(printk(KERN_DEBUG "addr0: %d\n", addr));
 144                 /* try extended address code... */
 145                 ret = try_address(adap, addr, retries);
 146                 if (ret != 1) {
 147                         printk(KERN_ERR
 148                                "iic_do_address: died at extended address code.\n");
 149                         return -EREMOTEIO;
 150                 }
 151                 /* the remaining 8 bit address */
 152                 iic_outb(msg->addr & 0x7f);
 153                 /* Status check comes here */
 154                 if (ret != 1) {
 155                         printk(KERN_ERR
 156                                "iic_do_address: died at 2nd address code.\n");
 157                         return -EREMOTEIO;
 158                 }
 159                 if (flags & I2C_M_RD) {
 160                         i2c_repstart(adap);
 161                         /* okay, now switch into reading mode */
 162                         addr |= 0x01;
 163                         ret = try_address(adap, addr, retries);
 164                         if (ret != 1) {
 165                                 printk(KERN_ERR
 166                                        "iic_do_address: died at extended address code.\n");
 167                                 return -EREMOTEIO;
 168                         }
 169                 }
 170         } else
 171                 /* ---------->  normal 7 bit address */
 172                 /*Ten bit addresses not supported yet */
 173 #endif
 174                 addr = (msg->addr << 1);
 175         if (flags & I2C_M_RD)
 176                 addr |= 1;
 177         if (flags & I2C_M_REV_DIR_ADDR)
 178                 addr ^= 1;
 179         /*
 180          * Write to the low slave address
 181          */
 182         iic_outb(iic->lmadr, addr);
 183         /*
 184          * Write zero to the high slave register since we are
 185          * only using 7 bit addresses
 186          */
 187         iic_outb(iic->hmadr, 0);
 188
 189         return 0;
 190 }
 191
 192 /*
 193  * Initialize IBM IIC.
 194  */
 195 static int
 196 iic_adap_init(struct i2c_adapter *adap)
 197 {
 198         struct iic_regs *iic;
 199         unsigned short retval;
 200
 201         iic = (struct iic_regs *) ((struct ocp_dev *) adap->data)->vaddr;
 202
 203         /* Clear master low master address */
 204         iic_outb(iic->lmadr, 0);
 205
 206         /* Clear high master address */
 207         iic_outb(iic->hmadr, 0);
 208
 209         /* Clear low slave address */
 210         iic_outb(iic->lsadr, 0);
 211
 212         /* Clear high slave address */
 213         iic_outb(iic->hsadr, 0);
 214
 215         /* Clear status */
 216         iic_outb(iic->sts, 0x0a);
 217
 218         /* Clear extended status */
 219         iic_outb(iic->extsts, 0x8f);
 220
 221         /* Set clock division */
 222         iic_outb(iic->clkdiv, 0x04);
 223
 224         retval = iic_inb(iic->clkdiv);
 225         DEB(printk("iic_adap_init: CLKDIV register = %x\n", retval));
 226
 227         /* Enable interrupts on Requested Master Transfer Complete */
 228         iic_outb(iic->intmsk, 0x01);
 229
 230         /* Clear transfer count */
 231         iic_outb(iic->xfrcnt, 0x0);
 232
 233         /* Clear extended control and status */
 234         iic_outb(iic->xtcntlss, 0xf0);
 235
 236         /* Set mode control (flush master data buf, enable hold SCL, exit */
 237         /* unknown state.                                                 */
 238         iic_outb(iic->mdcntl, 0x47);
 239
 240         /* Clear control register */
 241         iic_outb(iic->cntl, 0x0);
 242
 243         DEB2(printk(KERN_DEBUG "iic_adap_init: IBM IIC initialized.\n"));
 244         return 0;
 245 }
 246
 247 /*
 248  * Description: After we issue a transaction on the IIC bus, this function
 249  * is called.  It puts this process to sleep until we get an interrupt from
 250  * from the controller telling us that the transaction we requested in complete.
 251  */
 252 static int
 253 iic_wait_for_irq(struct i2c_adapter *adap, int *status)
 254 {
 255
 256         int timeout = DEF_TIMEOUT;
 257         int retval;
 258         struct iic_regs *iic;
 259
 260         iic = (struct iic_regs *) IIC_DEV(vaddr);
 261
 262         *status = iic_inb(iic->sts);
 263
 264         while (timeout-- && (*status & 0x01)) {
 265                 int timeout = 2;
 266                 struct ocp_dev *iic_dev;
 267
 268                 iic_dev = (struct ocp_dev *) adap->data;
 269
 270                 /*
 271                  * If interrupts are enabled (which they are),
 272                  * then put the process to sleep.  This process
 273                  * will be awakened by two events -- either the
 274                  * the IIC peripheral interrupts or the timeout
 275                  * expires.
 276                  */
 277                 if (iic_dev->irq > 0) {
 278                         cli();
 279                         if (iic_pending == 0) {
 280                                 interruptible_sleep_on_timeout(&
 281                                                                (iic_wait
 282                                                                 [iic_dev->num]),
 283                                                                timeout * HZ);
 284                         } else
 285                                 iic_pending = 0;
 286                         sti();
 287                 } else {
 288                         /*
 289                          * If interrupts are not enabled then
 290                          * delay for a reasonable amount of
 291                          * time and return.  We expect that by
 292                          * time we return to the calling function
 293                          * that the IIC has finished our requested
 294                          * transaction and the status bit reflects
 295                          * this.
 296                          *
 297                          * udelay is probably not the best choice
 298                          * for this since it is the equivalent of
 299                          * a busy wait.
 300                          */
 301                         udelay(100);
 302                 }
 303                 *status = iic_inb(iic->sts);
 304         }
 305
 306         if (timeout <= 0) {
 307                 /* Issue stop signal on the bus, and force an interrupt */
 308                 retval = iic_inb(iic->cntl);
 309                 iic_outb(iic->cntl, retval | 0x80);
 310                 /* Clear status register */
 311                 iic_outb(iic->sts, 0x0a);
 312                 /* Exit unknown bus state */
 313                 retval = iic_inb(iic->mdcntl);
 314                 iic_outb(iic->mdcntl, (retval | 0x02));
 315
 316                 /* Pending transfer bit cleared? */
 317                 retval = iic_inb(iic->sts);
 318                 retval = retval & 0x01;
 319                 if (retval) {
 320                         /*
 321                          * IIC has locked up. Perform a soft reset
 322                          * to regain control of the IIC and then
 323                          * reinitialize.
 324                          */
 325                         iic_outb(iic->xtcntlss, 0x01);
 326                         udelay(500);
 327                         iic_adap_init(adap);
 328                         /* Pending transfer bit cleared? */
 329                         retval = iic_inb(iic->sts);
 330                         retval = retval & 0x01;
 331                         if (retval) {
 332                                 printk(KERN_CRIT
 333                                        "IIC has locked up.  Processor reset is required.\n");
 334                         }
 335                         /*
 336                          * IIC sometimes needs the interrupt bit
 337                          * written again.  Sometimes it does not
 338                          * stick when written in iic_adap_init.
 339                          */
 340                         iic_outb(iic->intmsk, 0x01);
 341                 }
 342                 return (-1);
 343         } else
 344                 return (0);
 345 }
 346
 347 /*
 348  * Low level master send transaction.
 349  */
 350
 351 static int
 352 iic_sendbytes(struct i2c_adapter *adap, const char *buf,
 353               int count, int xfer_flag)
 354 {
 355         struct iic_regs *iic;
 356         int wrcount, status, timeout;
 357         int loops, remainder, i, j;
 358         int ret, error_code;
 359
 360         iic = (struct iic_regs *) IIC_DEV(vaddr);
 361
 362         if (count == 0)
 363                 return 0;
 364         wrcount = 0;
 365         loops = count / 4;
 366         remainder = count % 4;
 367
 368         if ((loops > 1) && (remainder == 0)) {
 369                 for (i = 0; i < (loops - 1); i++) {
 370
 371                         /* Write four bytes to master data buffer */
 372                         for (j = 0; j < 4; j++) {
 373                                 iic_outb(iic->mdbuf, buf[wrcount++]);
 374                         }
 375
 376                         /* Issue IIC command to begin transmission */
 377                         iic_outb(iic->cntl, 0x35);
 378
 379                         /*
 380                          * Wait for transmission to complete.  When
 381                          * complete, continue next loop iteration.
 382                          */
 383                         timeout = iic_wait_for_irq(adap, &status);
 384
 385                         if (timeout < 0) {
 386                                 /* Error handling */
 387                                 return wrcount;
 388                         }
 389
 390                         ret = iic_analyze_status(adap, &error_code);
 391
 392                         if (ret < 0) {
 393                                 if (error_code == IIC_ERR_INCOMPLETE_XFR) {
 394                                         /* Return bytes transferred */
 395                                         ret = iic_inb(iic->xfrcnt);
 396                                         ret = ret & 0x07;
 397                                         return (wrcount - 4 + ret);
 398                                 } else
 399                                         return error_code;
 400                         }
 401                 }
 402         } else if ((loops >= 1) && (remainder > 0)) {
 403                 for (i = 0; i < loops; i++) {
 404                         /* Write four bytes to master data buffer */
 405                         for (j = 0; j < 4; j++) {
 406                                 iic_outb(iic->mdbuf, buf[wrcount++]);
 407                         }
 408
 409                         /* Issue IIC command to begin transmission */
 410                         iic_outb(iic->cntl, 0x35);
 411
 412                         /*
 413                          * Wait for transmission to complete.  When
 414                          * complete, continue next loop iteration.
 415                          */
 416                         timeout = iic_wait_for_irq(adap, &status);
 417                         if (timeout < 0)
 418                                 return wrcount;
 419
 420                         ret = iic_analyze_status(adap, &error_code);
 421                         if (ret < 0) {
 422                                 if (error_code == IIC_ERR_INCOMPLETE_XFR) {
 423                                         /* Return bytes transferred */
 424                                         ret = iic_inb(iic->xfrcnt);
 425                                         ret = ret & 0x07;
 426                                         return (wrcount - 4 + ret);
 427                                 } else
 428                                         return error_code;
 429                         }
 430                 }
 431         }
 432
 433         if (remainder == 0)
 434                 remainder = 4;
 435
 436         /* Write the remaining bytes (<=4) */
 437         for (i = 0; i < remainder; i++)
 438                 iic_outb(iic->mdbuf, buf[wrcount++]);
 439
 440         if (xfer_flag == IIC_COMBINED_XFER) {
 441                 iic_outb(iic->cntl, (0x09 | ((remainder - 1) << 4)));
 442         } else {
 443                 iic_outb(iic->cntl, (0x01 | ((remainder - 1) << 4)));
 444         }
 445         DEB2(printk(KERN_DEBUG "iic_sendbytes: Waiting for interrupt\n"));
 446         timeout = iic_wait_for_irq(adap, &status);
 447         if (timeout < 0)
 448                 return wrcount;
 449
 450         ret = iic_analyze_status(adap, &error_code);
 451
 452         if (ret < 0) {
 453                 if (error_code == IIC_ERR_INCOMPLETE_XFR) {
 454                         /* Return bytes transferred */
 455                         ret = iic_inb(iic->xfrcnt);
 456                         ret = ret & 0x07;
 457                         return (wrcount - 4 + ret);
 458                 } else
 459                         return error_code;
 460         }
 461
 462         DEB2(printk(KERN_DEBUG "iic_sendbytes: Got interrupt\n"));
 463         return wrcount;
 464 }
 465
 466 /*
 467  * Low level master read transaction.
 468  */
 469 static int
 470 iic_readbytes(struct i2c_adapter *adap, char *buf, int count, int xfer_type)
 471 {
 472         struct iic_regs *iic;
 473         int rdcount = 0, i, status, timeout;
 474         int loops, remainder, j;
 475         int ret, error_code;
 476
 477         iic = (struct iic_regs *) IIC_DEV(vaddr);
 478
 479         if (count == 0)
 480                 return 0;
 481         loops = count / 4;
 482         remainder = count % 4;
 483
 484         if ((loops > 1) && (remainder == 0)) {
 485                 for (i = 0; i < (loops - 1); i++) {
 486                         /* Issue IIC master read command (<=4 bytes) */
 487                         iic_outb(iic->cntl, 0x37);
 488
 489                         /*
 490                          * Wait for transmission to complete.  When
 491                          * complete, continue next loop iteration.
 492                          */
 493                         timeout = iic_wait_for_irq(adap, &status);
 494                         if (timeout < 0)
 495                                 return rdcount;
 496
 497                         ret = iic_analyze_status(adap, &error_code);
 498
 499                         if (ret < 0) {
 500                                 if (error_code == IIC_ERR_INCOMPLETE_XFR)
 501                                         return rdcount;
 502                                 else
 503                                         return error_code;
 504                         }
 505
 506                         for (j = 0; j < 4; j++) {
 507                                 /*
 508                                  * Wait for data to shuffle to top of
 509                                  * data buffer. This value needs to be
 510                                  * optimized.
 511                                  */
 512                                 udelay(1);
 513                                 buf[rdcount] = iic_inb(iic->mdbuf);
 514                                 rdcount++;
 515                         }
 516                 }
 517         }
 518
 519         else if ((loops >= 1) && (remainder > 0)) {
 520                 for (i = 0; i < loops; i++) {
 521                         /* Issue IIC master read (<=4 bytes) */
 522                         iic_outb(iic->cntl, 0x37);
 523
 524                         /*
 525                          * Wait for transmission to complete.  When
 526                          * complete, continue next loop iteration.
 527                          */
 528                         timeout = iic_wait_for_irq(adap, &status);
 529                         if (timeout < 0)
 530                                 return rdcount;
 531
 532                         ret = iic_analyze_status(adap, &error_code);
 533
 534                         if (ret < 0) {
 535                                 if (error_code == IIC_ERR_INCOMPLETE_XFR)
 536                                         return rdcount;
 537                                 else
 538                                         return error_code;
 539                         }
 540
 541                         for (j = 0; j < 4; j++) {
 542                                 /*
 543                                  * Wait for data to shuffle to top of
 544                                  * data buffer. This value needs to be
 545                                  * optimized.
 546                                  */
 547                                 udelay(1);
 548                                 buf[rdcount] = iic_inb(iic->mdbuf);
 549                                 rdcount++;
 550                         }
 551                 }
 552         }
 553
 554         if (remainder == 0)
 555                 remainder = 4;
 556         DEB2(printk
 557              (KERN_DEBUG "iic_readbytes: writing %x to IIC0CNTL\n",
 558               (0x03 | ((remainder - 1) << 4))));
 559
 560         if (xfer_type == IIC_COMBINED_XFER) {
 561                 iic_outb(iic->cntl, (0x0b | ((remainder - 1) << 4)));
 562         } else {
 563                 iic_outb(iic->cntl, (0x03 | ((remainder - 1) << 4)));
 564         }
 565         DEB2(printk(KERN_DEBUG "iic_readbytes: Wait for pin\n"));
 566         timeout = iic_wait_for_irq(adap, &status);
 567         DEB2(printk(KERN_DEBUG "iic_readbytes: Got the interrupt\n"));
 568         if (timeout < 0)
 569                 return rdcount;
 570
 571         ret = iic_analyze_status(adap, &error_code);
 572
 573         if (ret < 0) {
 574                 if (error_code == IIC_ERR_INCOMPLETE_XFR)
 575                         return rdcount;
 576                 else
 577                         return error_code;
 578         }
 579
 580         for (i = 0; i < remainder; i++) {
 581                 buf[rdcount] = iic_inb(iic->mdbuf);
 582                 rdcount++;
 583         }
 584
 585         return rdcount;
 586 }
 587
 588 /*
 589  * Execute combined transations. Combined transactions consist
 590  * of combinations of reading and writing blocks of data. Each
 591  * transfer (i.e. a read or a write) is separated by a repeated
 592  * start condition.
 593  */
 594 static int
 595 iic_combined_transaction(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[],
 596                          int num)
 597 {
 598         int i;
 599         struct i2c_msg *pmsg;
 600         int ret;
 601
 602         DEB2(printk(KERN_DEBUG "Beginning combined transaction\n"));
 603         for (i = 0; i < num; i++) {
 604                 pmsg = &msgs[i];
 605                 if (pmsg->flags & I2C_M_RD) {
 606
 607                         /* Last segment needs to be terminated with a stop */
 608                         if (i < num - 1) {
 609                                 DEB2(printk(KERN_DEBUG "This one is a read\n"));
 610                         } else {
 611                                 DEB2(printk
 612                                      (KERN_DEBUG "Doing the last read\n"));
 613                         }
 614                         ret =
 615                             iic_readbytes(i2c_adap, pmsg->buf, pmsg->len,
 616                                           (i <
 617                                            num -
 618                                            1) ? IIC_COMBINED_XFER :
 619                                           IIC_SINGLE_XFER);
 620
 621                         if (ret != pmsg->len) {
 622                                 DEB2(printk("iic_combined_transation: fail: "
 623                                             "only read %d bytes.\n", ret));
 624                                 return i;
 625                         } else {
 626                                 DEB2(printk
 627                                      ("iic_combined_transaction: read %d bytes.\n",
 628                                       ret));
 629                         }
 630                 } else if (!(pmsg->flags & I2C_M_RD)) {
 631
 632                         /* Last segment needs to be terminated with a stop */
 633                         if (i < num - 1) {
 634                                 DEB2(printk
 635                                      (KERN_DEBUG "This one is a write\n"));
 636                         } else {
 637                                 DEB2(printk
 638                                      (KERN_DEBUG "Doing the last write\n"));
 639                         }
 640                         ret =
 641                             iic_sendbytes(i2c_adap, pmsg->buf, pmsg->len,
 642                                           (i <
 643                                            num -
 644                                            1) ? IIC_COMBINED_XFER :
 645                                           IIC_SINGLE_XFER);
 646
 647                         if (ret != pmsg->len) {
 648                                 DEB2(printk("iic_combined_transaction: fail: "
 649                                             "only wrote %d bytes.\n", ret));
 650                                 return i;
 651                         } else {
 652                                 DEB2(printk
 653                                      ("iic_combined_transaction: wrote %d bytes.\n",
 654                                       ret));
 655                         }
 656                 }
 657         }
 658
 659         return num;
 660 }
 661
 662 /*
 663  * Prepare controller for a transaction and call iic_sendbytes or
 664  * iic_readbytes to do the work.
 665  */
 666 static int
 667 iic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 668 {
 669         struct iic_regs *iic;
 670         struct i2c_msg *pmsg;
 671         int i = 0;
 672         int ret;
 673
 674         iic = (struct iic_regs *) IIC_DEV(vaddr);
 675
 676         pmsg = &msgs[i];
 677
 678         /*
 679          * Clear status register
 680          */
 681         DEB2(printk
 682              (KERN_DEBUG "iic_xfer: iic_xfer: Clearing status register\n"));
 683         iic_outb(iic->sts, 0x0a);
 684
 685         /* Wait for any pending transfers to complete */
 686         DEB2(printk
 687              (KERN_DEBUG
 688               "iic_xfer: Waiting for any pending transfers to complete\n"));
 689         while ((ret = iic_inb(iic->sts)) == 0x01) {
 690                 ;
 691         }
 692
 693         /* Flush master data buffer */
 694         DEB2(printk(KERN_DEBUG "iic_xfer: Clearing master data buffer\n"));
 695         ret = iic_inb(iic->mdcntl);
 696         iic_outb(iic->mdcntl, ret | 0x40);
 697
 698         /* Load slave address */
 699         DEB2(printk(KERN_DEBUG "iic_xfer: Loading slave address\n"));
 700         ret = iic_do_address(adap, pmsg, adap->retries);
 701
 702         /* Check to see if the bus is busy */
 703         ret = iic_inb(iic->extsts);
 704
 705         /* Mask off the irrelevent bits */
 706         ret = ret & 0x70;
 707
 708         /* Bus is free when BCS bits in the EXTSTS register are 0b100 */
 709         if (ret != 0x40)
 710                 return IIC_ERR_LOST_ARB;
 711
 712         /* Combined transaction (read/write) */
 713         if (num > 1) {
 714                 DEB2(printk
 715                      (KERN_DEBUG "iic_xfer: Call combined transaction\n"));
 716                 ret = iic_combined_transaction(adap, msgs, num);
 717         }
 718         /* Read only */
 719         else if ((num == 1) && (pmsg->flags & I2C_M_RD)) {
 720                 /* Tell device to begin reading data from the master data */
 721                 DEB2(printk(KERN_DEBUG "iic_xfer: Call adapter's read\n"));
 722                 ret =
 723                     iic_readbytes(adap, pmsg->buf, pmsg->len, IIC_SINGLE_XFER);
 724         }
 725         /* Write only */
 726         else if ((num == 1) && (!(pmsg->flags & I2C_M_RD))) {
 727                 /*
 728                  * Write data to master data buffers and tell our device
 729                  * to begin transmitting
 730                  */
 731                 DEB2(printk(KERN_DEBUG "iic_xfer: Call adapter's write\n"));
 732                 ret =
 733                     iic_sendbytes(adap, pmsg->buf, pmsg->len, IIC_SINGLE_XFER);
 734         }
 735
 736         return ret;
 737 }
 738
 739 static u32
 740 iic_func(struct i2c_adapter *adap)
 741 {
 742         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 743 }
 744
 745 static struct i2c_algorithm iic_algo = {
 746         "IBM IIC algorithm",
 747         I2C_ALGO_OCP,
 748         iic_xfer,
 749         NULL,
 750         NULL,                   /* slave_xmit           */
 751         NULL,                   /* slave_recv           */
 752         NULL,                   /* ioctl                */
 753         iic_func,               /* functionality        */
 754 };
 755
 756 /*
 757  * Register bus structure
 758  */
 759 int
 760 iic_add_bus(struct i2c_adapter *adap)
 761 {
 762
 763         DEB2(printk
 764              (KERN_DEBUG "iic_add_bus: hw routines for %s registered.\n",
 765               adap->name));
 766         adap->id |= iic_algo.id;
 767         adap->algo = &iic_algo;
 768         adap->timeout = IIC_TIMEOUT;
 769         adap->retries = IIC_RETRY;
 770
 771         iic_adap_init(adap);
 772         i2c_add_adapter(adap);
 773
 774         /*
 775          * Scan the I2C bus for valid 7 bit addresses
 776          * (ie things that ACK on 1byte read)
 777          * if i2c_debug is off we print everything on one line.
 778          * if i2c_debug is on we do a newline per print so we don't
 779          * clash too much with printk's in the other functions.
 780          * TODO: check for 10-bit mode and never run as a slave.
 781          */
 782         if (iic_scan) {
 783
 784                 int found = 0;
 785                 int i;
 786                 printk(KERN_INFO " iic_add_bus: scanning bus %s. Found ",
 787                        adap->name);
 788                 if (i2c_debug)
 789                         printk("\n");
 790                 for (i = 0; i < 0x7f; i++) {
 791                         int ret;
 792                         struct i2c_msg msg;
 793                         char data[1];
 794                         msg.addr = i;
 795                         msg.buf = data;
 796                         msg.len = 1;
 797                         msg.flags = I2C_M_RD;
 798                         if ((ret = iic_xfer(adap, &msg, 1)) == 1) {
 799                                 if (i2c_debug)
 800                                         printk
 801                                             ("I2C Found 0x%02x ret %d Data 0x%02x\n",
 802                                              i, ret, data[0]);
 803                                 else
 804                                         printk("0x%02x ", i);
 805                                 found++;
 806                         }
 807                 }
 808                 if (i2c_debug) {
 809                         if (!found)
 810                                 printk("I2C Found Nothing\n");
 811                 } else {
 812                         if (found)
 813                                 printk("\n");
 814                         else
 815                                 printk("Nothing\n");
 816                 }
 817
 818         }
 819         return 1;
 820 }
 821
 822 int
 823 iic_del_bus(struct i2c_adapter *adap)
 824 {
 825         int res;
 826         if ((res = i2c_del_adapter(adap)) < 0)
 827                 return res;
 828         DEB2(printk
 829              (KERN_DEBUG "iic_del_bus: adapter unregistered: %s\n",
 830               adap->name));
 831
 832         return 1;
 833 }
 834
 835 /*
 836  * IIC interrupt handler
 837  */
 838 static void
 839 iic_handler(int this_irq, void *dev_id, struct pt_regs *regs)
 840 {
 841         int ret;
 842         struct iic_regs *iic;
 843         struct ocp_dev *iic_dev;
 844
 845         iic_dev = (struct ocp_dev *) dev_id;
 846         iic = (struct iic_regs *) iic_dev->vaddr;
 847
 848         iic_pending = 1;
 849
 850         DEB2(printk("iic_handler: in interrupt handler\n"));
 851         /* Read status register */
 852         ret = readb((int) &(iic->sts));
 853         DEB2(printk("iic_handler: status = %x\n", ret));
 854         /* Clear status register */
 855         writeb(0x0a, (int) &(iic->sts));
 856         wake_up_interruptible(&(iic_wait[iic_dev->num]));
 857 }
 858
 859 /*
 860  * Release irq and memory
 861  */
 862 static void
 863 iic_release(void)
 864 {
 865         int i;
 866         struct ocp_dev *iic_drv;
 867
 868         for (i = 0; i < ocp_get_max(IIC); i++) {
 869                 iic_drv = ocp_get_dev(IIC, i);
 870                 if (iic_drv->irq > 0) {
 871                         disable_irq(iic_drv->irq);
 872                         free_irq(iic_drv->irq, 0);
 873                 }
 874         }
 875
 876 }
 877
 878 static int
 879 iic_reg(struct i2c_client *client)
 880 {
 881         return 0;
 882 }
 883
 884 static int
 885 iic_unreg(struct i2c_client *client)
 886 {
 887         return 0;
 888 }
 889
 890 /*
 891  * Increment module usage count
 892  */
 893 static void
 894 iic_inc_use(struct i2c_adapter *adap)
 895 {
 896 #ifdef MODULE
 897         MOD_INC_USE_COUNT;
 898 #endif
 899 }
 900
 901 /*
 902  * Decrement module usage count
 903  */
 904 static void
 905 iic_dec_use(struct i2c_adapter *adap)
 906 {
 907 #ifdef MODULE
 908         MOD_DEC_USE_COUNT;
 909 #endif
 910 }
 911
 912 /*
 913  * Called when the module is loaded.  This function starts the
 914  * cascade of calls up through the heirarchy of i2c modules
 915  * (i.e. up to the algorithm layer and into to the core layer)
 916  */
 917 static int __init
 918 iic_init(void)
 919 {
 920         struct ocp_dev *iic_drv;
 921         struct i2c_adapter *adap;
 922         int curr_iic = 0;
 923
 924         printk(KERN_INFO "IBM IIC driver\n");
 925
 926         while (curr_iic != -ENXIO) {
 927                 if (!(iic_drv = ocp_alloc_dev(sizeof (struct i2c_adapter))))
 928                         return -ENOMEM;
 929                 iic_drv->type = IIC;
 930                 if ((curr_iic = ocp_register(iic_drv)) != -ENXIO) {
 931                         adap = (struct i2c_adapter *) iic_drv->ocpdev;
 932                         iic_drv->vaddr = ioremap(iic_drv->paddr, 17);
 933                         strcpy(adap->name, "IBM IIC adapter");
 934                         adap->data = (void *) iic_drv;
 935                         adap->id = I2C_HW_OCP;
 936                         adap->algo = NULL;
 937                         adap->inc_use = iic_inc_use;
 938                         adap->dec_use = iic_dec_use;
 939                         adap->client_register = iic_reg;
 940                         adap->client_unregister = iic_unreg;
 941
 942                         init_waitqueue_head(&(iic_wait[curr_iic]));
 943
 944                         if (iic_drv->irq > 0) {
 945                                 if (request_irq
 946                                     (iic_drv->irq,
 947                                      iic_handler, 0, "IBM IIC", iic_drv)) {
 948                                         printk(KERN_ERR
 949                                                "iic_init: Request irq %d failed\n",
 950                                                iic_drv->irq);
 951                                         iic_drv->irq = 0;
 952                                 } else {
 953                                         DEB3(printk
 954                                              ("iic_init: Enabled interrupt\n"));
 955                                 }
 956                         }
 957
 958                         if (iic_add_bus(adap) < 0)
 959                                 return -ENODEV;
 960
 961                 } else {
 962                         ocp_free_dev(iic_drv);
 963                         break;
 964                 }               /* end if */
 965         }                       /* end while */
 966         return (curr_iic == -ENXIO) ? 0 : curr_iic;
 967 }
 968
 969 static void
 970 iic_exit(void)
 971 {
 972         int i;
 973         struct ocp_dev *iic_drv;
 974         struct i2c_adapter *adap;
 975
 976         for (i = 0; i < ocp_get_max(IIC); i++) {
 977                 iic_drv = ocp_get_dev(IIC, i);
 978                 adap = (struct i2c_adapter *) iic_drv->ocpdev;
 979                 iic_del_bus(adap);
 980         }
 981
 982         iic_release();
 983 }
 984
 985 /*
 986  * Put the process to sleep for a period equal to timeout
 987  */
 988 static inline void
 989 iic_sleep(unsigned long timeout)
 990 {
 991         schedule_timeout(timeout * HZ);
 992 }
 993
 994 MODULE_AUTHOR("MontaVista Software <www.mvista.com>");
 995 MODULE_DESCRIPTION("IBM IIC driver");
 996 MODULE_PARM(iic_scan, "i");
 997 MODULE_PARM(i2c_debug, "i");
 998 MODULE_PARM_DESC(iic_scan, "Scan for active chips on the bus");
 999 MODULE_PARM_DESC(i2c_debug,
1000                  "debug level - 0 off; 1 normal; 2,3 more verbose; 9 iic-protocol");
1001 MODULE_LICENSE("GPL");
1002
1003 module_init(iic_init);
1004 module_exit(iic_exit);