drivers/i2c/i2c-keywest.c

   1 /*
   2     i2c Support for Apple Keywest I2C Bus Controller
   3
   4     Copyright (c) 2001 Benjamin Herrenschmidt <benh@kernel.crashing.org>
   5
   6     Original work by
   7
   8     Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
   9
  10     This program is free software; you can redistribute it and/or modify
  11     it under the terms of the GNU General Public License as published by
  12     the Free Software Foundation; either version 2 of the License, or
  13     (at your option) any later version.
  14
  15     This program is distributed in the hope that it will be useful,
  16     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18     GNU General Public License for more details.
  19
  20     You should have received a copy of the GNU General Public License
  21     along with this program; if not, write to the Free Software
  22     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23
  24     Changes:
  25
  26     2001/12/13 BenH     New implementation
  27     2001/12/15 BenH     Add support for "byte" and "quick"
  28                         transfers. Add i2c_xfer routine.
  29
  30     My understanding of the various modes supported by keywest are:
  31
  32      - Dumb mode : not implemented, probably direct tweaking of lines
  33      - Standard mode : simple i2c transaction of type
  34          S Addr R/W A Data A Data ... T
  35      - Standard sub mode : combined 8 bit subaddr write with data read
  36          S Addr R/W A SubAddr A Data A Data ... T
  37      - Combined mode : Subaddress and Data sequences appended with no stop
  38          S Addr R/W A SubAddr S Addr R/W A Data A Data ... T
  39
  40     Currently, this driver uses only Standard mode for i2c xfer, and
  41     smbus byte & quick transfers ; and uses StandardSub mode for
  42     other smbus transfers instead of combined as we need that for the
  43     sound driver to be happy
  44 */
  45
  46 #include <linux/module.h>
  47 #include <linux/config.h>
  48 #include <linux/kernel.h>
  49 #include <linux/ioport.h>
  50 #include <linux/pci.h>
  51 #include <linux/types.h>
  52 #include <linux/delay.h>
  53 #include <linux/i2c.h>
  54 #include <linux/init.h>
  55 #include <linux/mm.h>
  56 #include <linux/timer.h>
  57 #include <linux/spinlock.h>
  58 #include <linux/completion.h>
  59
  60 #include <asm/io.h>
  61 #include <asm/prom.h>
  62 #include <asm/machdep.h>
  63 #include <asm/pmac_feature.h>
  64
  65 #include "i2c-keywest.h"
  66
  67 #define DBG(x...) do {\
  68         if (debug > 0) \
  69                 printk(KERN_DEBUG "KW:" x); \
  70         } while(0)
  71
  72
  73 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
  74 MODULE_DESCRIPTION("I2C driver for Apple's Keywest");
  75 MODULE_LICENSE("GPL");
  76 MODULE_PARM(probe, "i");
  77 MODULE_PARM(debug, "i");
  78 EXPORT_NO_SYMBOLS;
  79
  80 int probe = 0;
  81 int debug = 0;
  82
  83 static struct keywest_iface *ifaces = NULL;
  84
  85
  86 static void
  87 do_stop(struct keywest_iface* iface, int result)
  88 {
  89         write_reg(reg_control, read_reg(reg_control) | KW_I2C_CTL_STOP);
  90         iface->state = state_stop;
  91         iface->result = result;
  92 }
  93
  94 /* Main state machine for standard & standard sub mode */
  95 static int
  96 handle_interrupt(struct keywest_iface *iface, u8 isr)
  97 {
  98         int ack;
  99         int rearm_timer = 1;
 100
 101         DBG("handle_interrupt(), got: %x, status: %x, state: %d\n",
 102                 isr, read_reg(reg_status), iface->state);
 103         if (isr == 0 && iface->state != state_stop) {
 104                 do_stop(iface, -1);
 105                 return rearm_timer;
 106         }
 107         if (isr & KW_I2C_IRQ_STOP && iface->state != state_stop) {
 108                 iface->result = -1;
 109                 iface->state = state_stop;
 110         }
 111         switch(iface->state) {
 112         case state_addr:
 113                 if (!(isr & KW_I2C_IRQ_ADDR)) {
 114                         do_stop(iface, -1);
 115                         break;
 116                 }
 117                 ack = read_reg(reg_status);
 118                 DBG("ack on set address: %x\n", ack);
 119                 if ((ack & KW_I2C_STAT_LAST_AAK) == 0) {
 120                         do_stop(iface, -1);
 121                         break;
 122                 }
 123                 /* Handle rw "quick" mode */
 124                 if (iface->datalen == 0)
 125                         do_stop(iface, 0);
 126                 else if (iface->read_write == I2C_SMBUS_READ) {
 127                         iface->state = state_read;
 128                         if (iface->datalen > 1)
 129                                 write_reg(reg_control, read_reg(reg_control)
 130                                         | KW_I2C_CTL_AAK);
 131                 } else {
 132                         iface->state = state_write;
 133                         DBG("write byte: %x\n", *(iface->data));
 134                         write_reg(reg_data, *(iface->data++));
 135                         iface->datalen--;
 136                 }
 137
 138                 break;
 139         case state_read:
 140                 if (!(isr & KW_I2C_IRQ_DATA)) {
 141                         do_stop(iface, -1);
 142                         break;
 143                 }
 144                 *(iface->data++) = read_reg(reg_data);
 145                 DBG("read byte: %x\n", *(iface->data-1));
 146                 iface->datalen--;
 147                 if (iface->datalen == 0)
 148                         iface->state = state_stop;
 149                 else
 150                         write_reg(reg_control, 0);
 151                 break;
 152         case state_write:
 153                 if (!(isr & KW_I2C_IRQ_DATA)) {
 154                         do_stop(iface, -1);
 155                         break;
 156                 }
 157                 /* Check ack status */
 158                 ack = read_reg(reg_status);
 159                 DBG("ack on data write: %x\n", ack);
 160                 if ((ack & KW_I2C_STAT_LAST_AAK) == 0) {
 161                         do_stop(iface, -1);
 162                         break;
 163                 }
 164                 if (iface->datalen) {
 165                         DBG("write byte: %x\n", *(iface->data));
 166                         write_reg(reg_data, *(iface->data++));
 167                         iface->datalen--;
 168                 } else
 169                         do_stop(iface, 0);
 170                 break;
 171
 172         case state_stop:
 173                 if (!(isr & KW_I2C_IRQ_STOP) && (++iface->stopretry) < 10)
 174                         do_stop(iface, -1);
 175                 else {
 176                         rearm_timer = 0;
 177                         iface->state = state_idle;
 178                         write_reg(reg_control, 0x00);
 179                         write_reg(reg_ier, 0x00);
 180                         complete(&iface->complete);
 181                 }
 182                 break;
 183         }
 184
 185         write_reg(reg_isr, isr);
 186
 187         return rearm_timer;
 188 }
 189
 190 /* Interrupt handler */
 191 static void
 192 keywest_irq(int irq, void *dev_id, struct pt_regs *regs)
 193 {
 194         struct keywest_iface *iface = (struct keywest_iface *)dev_id;
 195
 196         spin_lock(&iface->lock);
 197         del_timer(&iface->timeout_timer);
 198         if (handle_interrupt(iface, read_reg(reg_isr))) {
 199                 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
 200                 add_timer(&iface->timeout_timer);
 201         }
 202         spin_unlock(&iface->lock);
 203 }
 204
 205 static void
 206 keywest_timeout(unsigned long data)
 207 {
 208         struct keywest_iface *iface = (struct keywest_iface *)data;
 209
 210         DBG("timeout !\n");
 211         spin_lock_irq(&iface->lock);
 212         if (handle_interrupt(iface, read_reg(reg_isr))) {
 213                 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
 214                 add_timer(&iface->timeout_timer);
 215         }
 216         spin_unlock(&iface->lock);
 217 }
 218
 219 /*
 220  * SMBUS-type transfer entrypoint
 221  */
 222 static s32
 223 keywest_smbus_xfer(     struct i2c_adapter*     adap,
 224                         u16                     addr,
 225                         unsigned short          flags,
 226                         char                    read_write,
 227                         u8                      command,
 228                         int                     size,
 229                         union i2c_smbus_data*   data)
 230 {
 231         struct keywest_chan* chan = (struct keywest_chan*)adap->data;
 232         struct keywest_iface* iface = chan->iface;
 233         int len;
 234         u8* buffer;
 235         u16 cur_word;
 236         int rc = 0;
 237
 238         if (iface->state == state_dead)
 239                 return -1;
 240
 241         /* Prepare datas & select mode */
 242         iface->cur_mode &= ~KW_I2C_MODE_MODE_MASK;
 243         switch (size) {
 244             case I2C_SMBUS_QUICK:
 245                 len = 0;
 246                 buffer = NULL;
 247                 iface->cur_mode |= KW_I2C_MODE_STANDARD;
 248                 break;
 249             case I2C_SMBUS_BYTE:
 250                 len = 1;
 251                 buffer = &data->byte;
 252                 iface->cur_mode |= KW_I2C_MODE_STANDARD;
 253                 break;
 254             case I2C_SMBUS_BYTE_DATA:
 255                 len = 1;
 256                 buffer = &data->byte;
 257                 iface->cur_mode |= KW_I2C_MODE_STANDARDSUB;
 258                 break;
 259             case I2C_SMBUS_WORD_DATA:
 260                 len = 2;
 261                 cur_word = cpu_to_le16(data->word);
 262                 buffer = (u8 *)&cur_word;
 263                 iface->cur_mode |= KW_I2C_MODE_STANDARDSUB;
 264                 break;
 265             case I2C_SMBUS_BLOCK_DATA:
 266                 len = data->block[0];
 267                 buffer = &data->block[1];
 268                 iface->cur_mode |= KW_I2C_MODE_STANDARDSUB;
 269                 break;
 270             default:
 271                 return -1;
 272         }
 273
 274         /* Original driver had this limitation */
 275         if (len > 32)
 276                 len = 32;
 277
 278         down(&iface->sem);
 279
 280         DBG("chan: %d, addr: 0x%x, transfer len: %d, read: %d\n",
 281                 chan->chan_no, addr, len, read_write == I2C_SMBUS_READ);
 282
 283         iface->data = buffer;
 284         iface->datalen = len;
 285         iface->state = state_addr;
 286         iface->result = 0;
 287         iface->stopretry = 0;
 288         iface->read_write = read_write;
 289
 290         /* Setup channel & clear pending irqs */
 291         write_reg(reg_mode, iface->cur_mode | (chan->chan_no << 4));
 292         write_reg(reg_isr, read_reg(reg_isr));
 293         write_reg(reg_status, 0);
 294
 295         /* Set up address and r/w bit */
 296         write_reg(reg_addr,
 297                 (addr << 1) | ((read_write == I2C_SMBUS_READ) ? 0x01 : 0x00));
 298
 299         /* Set up the sub address */
 300         if ((iface->cur_mode & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_STANDARDSUB
 301             || (iface->cur_mode & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_COMBINED)
 302                 write_reg(reg_subaddr, command);
 303
 304         /* Arm timeout */
 305         iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
 306         add_timer(&iface->timeout_timer);
 307
 308         /* Start sending address & enable interrupt*/
 309         write_reg(reg_control, read_reg(reg_control) | KW_I2C_CTL_XADDR);
 310         write_reg(reg_ier, KW_I2C_IRQ_MASK);
 311
 312         wait_for_completion(&iface->complete);
 313
 314         rc = iface->result;
 315         DBG("transfer done, result: %d\n", rc);
 316
 317         if (rc == 0 && size == I2C_SMBUS_WORD_DATA && read_write == I2C_SMBUS_READ)
 318                 data->word = le16_to_cpu(cur_word);
 319
 320         /* Release sem */
 321         up(&iface->sem);
 322
 323         return rc;
 324 }
 325
 326 /*
 327  * Generic i2c master transfer entrypoint
 328  */
 329 static int
 330 keywest_xfer(   struct i2c_adapter *adap,
 331                 struct i2c_msg msgs[],
 332                 int num)
 333 {
 334         struct keywest_chan* chan = (struct keywest_chan*)adap->data;
 335         struct keywest_iface* iface = chan->iface;
 336         struct i2c_msg *pmsg;
 337         int i, completed;
 338         int rc = 0;
 339
 340         down(&iface->sem);
 341
 342         /* Set adapter to standard mode */
 343         iface->cur_mode &= ~KW_I2C_MODE_MODE_MASK;
 344         iface->cur_mode |= KW_I2C_MODE_STANDARD;
 345
 346         completed = 0;
 347         for (i = 0; rc >= 0 && i < num;) {
 348                 u8 addr;
 349
 350                 pmsg = &msgs[i++];
 351                 addr = pmsg->addr;
 352                 if (pmsg->flags & I2C_M_TEN) {
 353                         printk(KERN_ERR "i2c-keywest: 10 bits addr not supported !\n");
 354                         rc = -EINVAL;
 355                         break;
 356                 }
 357                 DBG("xfer: chan: %d, doing %s %d bytes to 0x%02x - %d of %d messages\n",
 358                      chan->chan_no,
 359                      pmsg->flags & I2C_M_RD ? "read" : "write",
 360                      pmsg->len, addr, i, num);
 361
 362                 /* Setup channel & clear pending irqs */
 363                 write_reg(reg_mode, iface->cur_mode | (chan->chan_no << 4));
 364                 write_reg(reg_isr, read_reg(reg_isr));
 365                 write_reg(reg_status, 0);
 366
 367                 iface->data = pmsg->buf;
 368                 iface->datalen = pmsg->len;
 369                 iface->state = state_addr;
 370                 iface->result = 0;
 371                 iface->stopretry = 0;
 372                 if (pmsg->flags & I2C_M_RD)
 373                         iface->read_write = I2C_SMBUS_READ;
 374                 else
 375                         iface->read_write = I2C_SMBUS_WRITE;
 376
 377                 /* Set up address and r/w bit */
 378                 if (pmsg->flags & I2C_M_REV_DIR_ADDR)
 379                         addr ^= 1;
 380                 write_reg(reg_addr,
 381                         (addr << 1) |
 382                         ((iface->read_write == I2C_SMBUS_READ) ? 0x01 : 0x00));
 383
 384                 /* Arm timeout */
 385                 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
 386                 add_timer(&iface->timeout_timer);
 387
 388                 /* Start sending address & enable interrupt*/
 389                 write_reg(reg_control, read_reg(reg_control) | KW_I2C_CTL_XADDR);
 390                 write_reg(reg_ier, KW_I2C_IRQ_MASK);
 391
 392                 wait_for_completion(&iface->complete);
 393
 394                 rc = iface->result;
 395                 if (rc == 0)
 396                         completed++;
 397                 DBG("transfer done, result: %d\n", rc);
 398         }
 399
 400         /* Release sem */
 401         up(&iface->sem);
 402
 403         return completed;
 404 }
 405
 406 static u32
 407 keywest_func(struct i2c_adapter * adapter)
 408 {
 409         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 410                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 411                I2C_FUNC_SMBUS_BLOCK_DATA;
 412 }
 413
 414 static void
 415 keywest_inc(struct i2c_adapter *adapter)
 416 {
 417         MOD_INC_USE_COUNT;
 418 }
 419
 420 static void
 421 keywest_dec(struct i2c_adapter *adapter)
 422 {
 423         MOD_DEC_USE_COUNT;
 424 }
 425
 426 /* For now, we only handle combined mode (smbus) */
 427 static struct i2c_algorithm keywest_algorithm = {
 428         name:           "Keywest i2c",
 429         id:             I2C_ALGO_SMBUS,
 430         smbus_xfer:     keywest_smbus_xfer,
 431         master_xfer:    keywest_xfer,
 432         functionality:  keywest_func,
 433 };
 434
 435
 436 static int
 437 create_iface(struct device_node* np)
 438 {
 439         unsigned long steps, *psteps, *prate;
 440         unsigned bsteps, tsize, i, nchan, addroffset;
 441         struct keywest_iface* iface;
 442         int rc;
 443
 444         psteps = (unsigned long *)get_property(np, "AAPL,address-step", NULL);
 445         steps = psteps ? (*psteps) : 0x10;
 446
 447         /* Hrm... maybe we can be smarter here */
 448         for (bsteps = 0; (steps & 0x01) == 0; bsteps++)
 449                 steps >>= 1;
 450
 451         if (!strcmp(np->parent->name, "uni-n")) {
 452                 nchan = 2;
 453                 addroffset = 3;
 454         } else {
 455                 addroffset = 0;
 456                 nchan = 1;
 457         }
 458
 459         tsize = sizeof(struct keywest_iface) +
 460                 (sizeof(struct keywest_chan) + 4) * nchan;
 461         iface = (struct keywest_iface *) kmalloc(tsize, GFP_KERNEL);
 462         if (iface == NULL) {
 463                 printk(KERN_ERR "i2c-keywest: can't allocate inteface !\n");
 464                 return -ENOMEM;
 465         }
 466         memset(iface, 0, tsize);
 467         init_MUTEX(&iface->sem);
 468         spin_lock_init(&iface->lock);
 469         init_completion(&iface->complete);
 470         iface->bsteps = bsteps;
 471         iface->chan_count = nchan;
 472         iface->state = state_idle;
 473         iface->irq = np->intrs[0].line;
 474         iface->channels = (struct keywest_chan *)
 475                 (((unsigned long)(iface + 1) + 3UL) & ~3UL);
 476         iface->base = (unsigned long)ioremap(np->addrs[0].address + addroffset,
 477                                                 np->addrs[0].size);
 478         if (iface->base == 0) {
 479                 printk(KERN_ERR "i2c-keywest: can't map inteface !\n");
 480                 kfree(iface);
 481                 return -ENOMEM;
 482         }
 483
 484         init_timer(&iface->timeout_timer);
 485         iface->timeout_timer.function = keywest_timeout;
 486         iface->timeout_timer.data = (unsigned long)iface;
 487
 488         /* Select interface rate */
 489         iface->cur_mode = KW_I2C_MODE_100KHZ;
 490         prate = (unsigned long *)get_property(np, "AAPL,i2c-rate", NULL);
 491         if (prate) switch(*prate) {
 492         case 100:
 493                 iface->cur_mode = KW_I2C_MODE_100KHZ;
 494                 break;
 495         case 50:
 496                 iface->cur_mode = KW_I2C_MODE_50KHZ;
 497                 break;
 498         case 25:
 499                 iface->cur_mode = KW_I2C_MODE_25KHZ;
 500                 break;
 501         default:
 502                 printk(KERN_WARNING "i2c-keywest: unknown rate %ldKhz, using 100KHz\n",
 503                         *prate);
 504         }
 505
 506         /* Select standard mode by default */
 507         iface->cur_mode |= KW_I2C_MODE_STANDARD;
 508
 509         /* Write mode */
 510         write_reg(reg_mode, iface->cur_mode);
 511
 512         /* Switch interrupts off & clear them*/
 513         write_reg(reg_ier, 0x00);
 514         write_reg(reg_isr, KW_I2C_IRQ_MASK);
 515
 516         /* Request chip interrupt */
 517         rc = request_irq(iface->irq, keywest_irq, 0, "keywest i2c", iface);
 518         if (rc) {
 519                 printk(KERN_ERR "i2c-keywest: can't get IRQ %d !\n", iface->irq);
 520                 iounmap((void *)iface->base);
 521                 kfree(iface);
 522                 return -ENODEV;
 523         }
 524
 525         for (i=0; i<nchan; i++) {
 526                 struct keywest_chan* chan = &iface->channels[i];
 527                 u8 addr;
 528
 529                 sprintf(chan->adapter.name, "%s %d", np->parent->name, i);
 530                 chan->iface = iface;
 531                 chan->chan_no = i;
 532                 chan->adapter.id = I2C_ALGO_SMBUS;
 533                 chan->adapter.algo = &keywest_algorithm;
 534                 chan->adapter.algo_data = NULL;
 535                 chan->adapter.inc_use = keywest_inc;
 536                 chan->adapter.dec_use = keywest_dec;
 537                 chan->adapter.client_register = NULL;
 538                 chan->adapter.client_unregister = NULL;
 539                 chan->adapter.data = chan;
 540
 541                 rc = i2c_add_adapter(&chan->adapter);
 542                 if (rc) {
 543                         printk("i2c-keywest.c: Adapter %s registration failed\n",
 544                                 chan->adapter.name);
 545                         chan->adapter.data = NULL;
 546                 }
 547                 if (probe) {
 548                         printk("Probe: ");
 549                         for (addr = 0x00; addr <= 0x7f; addr++) {
 550                                 if (i2c_smbus_xfer(&chan->adapter,addr,
 551                                     0,0,0,I2C_SMBUS_QUICK,NULL) >= 0)
 552                                         printk("%02x ", addr);
 553                         }
 554                         printk("\n");
 555                 }
 556         }
 557
 558         printk(KERN_INFO "Found KeyWest i2c on \"%s\", %d channel%s, stepping: %d bits\n",
 559                 np->parent->name, nchan, nchan > 1 ? "s" : "", bsteps);
 560
 561         iface->next = ifaces;
 562         ifaces = iface;
 563         return 0;
 564 }
 565
 566 static void
 567 dispose_iface(struct keywest_iface *iface)
 568 {
 569         int i, rc;
 570
 571         ifaces = iface->next;
 572
 573         /* Make sure we stop all activity */
 574         down(&iface->sem);
 575         spin_lock_irq(&iface->lock);
 576         while (iface->state != state_idle) {
 577                 spin_unlock_irq(&iface->lock);
 578                 set_task_state(current,TASK_UNINTERRUPTIBLE);
 579                 schedule_timeout(HZ/10);
 580                 spin_lock_irq(&iface->lock);
 581         }
 582         iface->state = state_dead;
 583         spin_unlock_irq(&iface->lock);
 584         free_irq(iface->irq, iface);
 585         up(&iface->sem);
 586
 587         /* Release all channels */
 588         for (i=0; i<iface->chan_count; i++) {
 589                 struct keywest_chan* chan = &iface->channels[i];
 590                 if (!chan->adapter.data)
 591                         continue;
 592                 rc = i2c_del_adapter(&chan->adapter);
 593                 chan->adapter.data = NULL;
 594                 /* We aren't that prepared to deal with this... */
 595                 if (rc)
 596                         printk("i2c-keywest.c: i2c_del_adapter failed, that's bad !\n");
 597         }
 598         iounmap((void *)iface->base);
 599         kfree(iface);
 600 }
 601
 602 static int __init
 603 i2c_keywest_init(void)
 604 {
 605         struct device_node *np;
 606         int rc = -ENODEV;
 607
 608         np = find_compatible_devices("i2c", "keywest");
 609         while (np != 0) {
 610                 if (np->n_addrs >= 1 && np->n_intrs >= 1)
 611                         rc = create_iface(np);
 612                 np = np->next;
 613         }
 614         if (ifaces)
 615                 rc = 0;
 616         return rc;
 617 }
 618
 619 static void __exit
 620 i2c_keywest_cleanup(void)
 621 {
 622         while(ifaces)
 623                 dispose_iface(ifaces);
 624 }
 625
 626 module_init(i2c_keywest_init);
 627 module_exit(i2c_keywest_cleanup);