4 #include <linux/config.h>
8 #define DISPLAY_AEC62XX_TIMINGS
10 struct chipset_bus_clock_list_entry {
12 byte chipset_settings;
16 struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
17 { XFER_UDMA_6, 0x31, 0x07 },
18 { XFER_UDMA_5, 0x31, 0x06 },
19 { XFER_UDMA_4, 0x31, 0x05 },
20 { XFER_UDMA_3, 0x31, 0x04 },
21 { XFER_UDMA_2, 0x31, 0x03 },
22 { XFER_UDMA_1, 0x31, 0x02 },
23 { XFER_UDMA_0, 0x31, 0x01 },
25 { XFER_MW_DMA_2, 0x31, 0x00 },
26 { XFER_MW_DMA_1, 0x31, 0x00 },
27 { XFER_MW_DMA_0, 0x0a, 0x00 },
28 { XFER_PIO_4, 0x31, 0x00 },
29 { XFER_PIO_3, 0x33, 0x00 },
30 { XFER_PIO_2, 0x08, 0x00 },
31 { XFER_PIO_1, 0x0a, 0x00 },
32 { XFER_PIO_0, 0x00, 0x00 },
36 struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
37 { XFER_UDMA_6, 0x41, 0x06 },
38 { XFER_UDMA_5, 0x41, 0x05 },
39 { XFER_UDMA_4, 0x41, 0x04 },
40 { XFER_UDMA_3, 0x41, 0x03 },
41 { XFER_UDMA_2, 0x41, 0x02 },
42 { XFER_UDMA_1, 0x41, 0x01 },
43 { XFER_UDMA_0, 0x41, 0x01 },
45 { XFER_MW_DMA_2, 0x41, 0x00 },
46 { XFER_MW_DMA_1, 0x42, 0x00 },
47 { XFER_MW_DMA_0, 0x7a, 0x00 },
48 { XFER_PIO_4, 0x41, 0x00 },
49 { XFER_PIO_3, 0x43, 0x00 },
50 { XFER_PIO_2, 0x78, 0x00 },
51 { XFER_PIO_1, 0x7a, 0x00 },
52 { XFER_PIO_0, 0x70, 0x00 },
58 #define HIGH_4(H) ((H)=(H>>4))
61 #define LOW_4(L) ((L)=(L-((L>>4)<<4)))
64 #define SPLIT_BYTE(B,H,L) ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
67 #define MAKE_WORD(W,HB,LB) ((W)=((HB<<8)+LB))
71 ((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
73 #if defined(DISPLAY_AEC62XX_TIMINGS) && defined(CONFIG_PROC_FS)
74 #include <linux/stat.h>
75 #include <linux/proc_fs.h>
77 static u8 aec62xx_proc;
79 static int aec62xx_get_info(char *, char **, off_t, int);
81 static ide_pci_host_proc_t aec62xx_procs[] __initdata = {
85 .get_info = aec62xx_get_info,
89 #endif /* DISPLAY_AEC62XX_TIMINGS && CONFIG_PROC_FS */
91 static void init_setup_aec6x80(struct pci_dev *, ide_pci_device_t *);
92 static void init_setup_aec62xx(struct pci_dev *, ide_pci_device_t *);
93 static unsigned int init_chipset_aec62xx(struct pci_dev *, const char *);
94 static void init_hwif_aec62xx(ide_hwif_t *);
95 static void init_dma_aec62xx(ide_hwif_t *, unsigned long);
97 static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
99 .vendor = PCI_VENDOR_ID_ARTOP,
100 .device = PCI_DEVICE_ID_ARTOP_ATP850UF,
102 .init_setup = init_setup_aec62xx,
103 .init_chipset = init_chipset_aec62xx,
105 .init_hwif = init_hwif_aec62xx,
106 .init_dma = init_dma_aec62xx,
109 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
110 .bootable = OFF_BOARD,
113 .vendor = PCI_VENDOR_ID_ARTOP,
114 .device = PCI_DEVICE_ID_ARTOP_ATP860,
116 .init_setup = init_setup_aec62xx,
117 .init_chipset = init_chipset_aec62xx,
119 .init_hwif = init_hwif_aec62xx,
120 .init_dma = init_dma_aec62xx,
122 .autodma = NOAUTODMA,
123 .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
124 .bootable = OFF_BOARD,
127 .vendor = PCI_VENDOR_ID_ARTOP,
128 .device = PCI_DEVICE_ID_ARTOP_ATP860R,
130 .init_setup = init_setup_aec62xx,
131 .init_chipset = init_chipset_aec62xx,
133 .init_hwif = init_hwif_aec62xx,
134 .init_dma = init_dma_aec62xx,
137 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
138 .bootable = NEVER_BOARD,
141 .vendor = PCI_VENDOR_ID_ARTOP,
142 .device = PCI_DEVICE_ID_ARTOP_ATP865,
144 .init_setup = init_setup_aec6x80,
145 .init_chipset = init_chipset_aec62xx,
147 .init_hwif = init_hwif_aec62xx,
148 .init_dma = init_dma_aec62xx,
151 .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
152 .bootable = OFF_BOARD,
155 .vendor = PCI_VENDOR_ID_ARTOP,
156 .device = PCI_DEVICE_ID_ARTOP_ATP865R,
158 .init_setup = init_setup_aec6x80,
159 .init_chipset = init_chipset_aec62xx,
161 .init_hwif = init_hwif_aec62xx,
162 .init_dma = init_dma_aec62xx,
165 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
166 .bootable = OFF_BOARD,
171 #endif /* AEC62XX_H */