1 /* $Id: cmd64x.c,v 1.21 2000/01/30 23:23:16
3 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
5 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
6 * Note, this driver is not used at all on other systems because
7 * there the "BIOS" has done all of the following already.
8 * Due to massive hardware bugs, UltraDMA is only supported
9 * on the 646U2 and not on the 646U.
11 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
12 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
14 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
17 #include <linux/config.h>
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/pci.h>
21 #include <linux/delay.h>
22 #include <linux/hdreg.h>
23 #include <linux/ide.h>
24 #include <linux/init.h>
28 #include "ide_modes.h"
31 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
32 #include <linux/stat.h>
33 #include <linux/proc_fs.h>
35 static u8 cmd64x_proc = 0;
37 #define CMD_MAX_DEVS 5
39 static struct pci_dev *cmd_devs[CMD_MAX_DEVS];
40 static int n_cmd_devs;
44 static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
48 u8 reg53 = 0, reg54 = 0, reg55 = 0, reg56 = 0; /* primary */
49 u8 reg57 = 0, reg58 = 0, reg5b; /* secondary */
50 u8 reg72 = 0, reg73 = 0; /* primary */
51 u8 reg7a = 0, reg7b = 0; /* secondary */
52 u8 reg50 = 0, reg71 = 0; /* extra */
54 u8 hi_byte = 0, lo_byte = 0;
55 #endif /* DEBUG_CMD_REGS */
57 p += sprintf(p, "\nController: %d\n", index);
58 p += sprintf(p, "CMD%x Chipset.\n", dev->device);
59 (void) pci_read_config_byte(dev, CFR, ®50);
60 (void) pci_read_config_byte(dev, ARTTIM0, ®53);
61 (void) pci_read_config_byte(dev, DRWTIM0, ®54);
62 (void) pci_read_config_byte(dev, ARTTIM1, ®55);
63 (void) pci_read_config_byte(dev, DRWTIM1, ®56);
64 (void) pci_read_config_byte(dev, ARTTIM2, ®57);
65 (void) pci_read_config_byte(dev, DRWTIM2, ®58);
66 (void) pci_read_config_byte(dev, DRWTIM3, ®5b);
67 (void) pci_read_config_byte(dev, MRDMODE, ®71);
68 (void) pci_read_config_byte(dev, BMIDESR0, ®72);
69 (void) pci_read_config_byte(dev, UDIDETCR0, ®73);
70 (void) pci_read_config_byte(dev, BMIDESR1, ®7a);
71 (void) pci_read_config_byte(dev, UDIDETCR1, ®7b);
73 p += sprintf(p, "--------------- Primary Channel "
74 "---------------- Secondary Channel "
76 p += sprintf(p, " %sabled "
78 (reg72&0x80)?"dis":" en",
79 (reg7a&0x80)?"dis":" en");
80 p += sprintf(p, "--------------- drive0 "
81 "--------- drive1 -------- drive0 "
82 "---------- drive1 ------\n");
83 p += sprintf(p, "DMA enabled: %s %s"
85 (reg72&0x20)?"yes":"no ", (reg72&0x40)?"yes":"no ",
86 (reg7a&0x20)?"yes":"no ", (reg7a&0x40)?"yes":"no ");
88 p += sprintf(p, "DMA Mode: %s(%s) %s(%s)",
89 (reg72&0x20)?((reg73&0x01)?"UDMA":" DMA"):" PIO",
91 ((reg73&0x30)==0x30)?(((reg73&0x35)==0x35)?"3":"0"):
92 ((reg73&0x20)==0x20)?(((reg73&0x25)==0x25)?"3":"1"):
93 ((reg73&0x10)==0x10)?(((reg73&0x15)==0x15)?"4":"2"):
94 ((reg73&0x00)==0x00)?(((reg73&0x05)==0x05)?"5":"2"):
96 (reg72&0x40)?((reg73&0x02)?"UDMA":" DMA"):" PIO",
98 ((reg73&0xC0)==0xC0)?(((reg73&0xC5)==0xC5)?"3":"0"):
99 ((reg73&0x80)==0x80)?(((reg73&0x85)==0x85)?"3":"1"):
100 ((reg73&0x40)==0x40)?(((reg73&0x4A)==0x4A)?"4":"2"):
101 ((reg73&0x00)==0x00)?(((reg73&0x0A)==0x0A)?"5":"2"):
103 p += sprintf(p, " %s(%s) %s(%s)\n",
104 (reg7a&0x20)?((reg7b&0x01)?"UDMA":" DMA"):" PIO",
106 ((reg7b&0x30)==0x30)?(((reg7b&0x35)==0x35)?"3":"0"):
107 ((reg7b&0x20)==0x20)?(((reg7b&0x25)==0x25)?"3":"1"):
108 ((reg7b&0x10)==0x10)?(((reg7b&0x15)==0x15)?"4":"2"):
109 ((reg7b&0x00)==0x00)?(((reg7b&0x05)==0x05)?"5":"2"):
111 (reg7a&0x40)?((reg7b&0x02)?"UDMA":" DMA"):" PIO",
113 ((reg7b&0xC0)==0xC0)?(((reg7b&0xC5)==0xC5)?"3":"0"):
114 ((reg7b&0x80)==0x80)?(((reg7b&0x85)==0x85)?"3":"1"):
115 ((reg7b&0x40)==0x40)?(((reg7b&0x4A)==0x4A)?"4":"2"):
116 ((reg7b&0x00)==0x00)?(((reg7b&0x0A)==0x0A)?"5":"2"):
118 p += sprintf(p, "PIO Mode: %s %s"
121 p += sprintf(p, " %s %s\n",
122 (reg50 & CFR_INTR_CH0) ? "interrupting" : "polling ",
123 (reg57 & ARTTIM23_INTR_CH1) ? "interrupting" : "polling");
124 p += sprintf(p, " %s %s\n",
125 (reg71 & MRDMODE_INTR_CH0) ? "pending" : "clear ",
126 (reg71 & MRDMODE_INTR_CH1) ? "pending" : "clear");
127 p += sprintf(p, " %s %s\n",
128 (reg71 & MRDMODE_BLK_CH0) ? "blocked" : "enabled",
129 (reg71 & MRDMODE_BLK_CH1) ? "blocked" : "enabled");
131 #ifdef DEBUG_CMD_REGS
132 SPLIT_BYTE(reg50, hi_byte, lo_byte);
133 p += sprintf(p, "CFR = 0x%02x, HI = 0x%02x, "
134 "LOW = 0x%02x\n", reg50, hi_byte, lo_byte);
135 SPLIT_BYTE(reg57, hi_byte, lo_byte);
136 p += sprintf(p, "ARTTIM23 = 0x%02x, HI = 0x%02x, "
137 "LOW = 0x%02x\n", reg57, hi_byte, lo_byte);
138 SPLIT_BYTE(reg71, hi_byte, lo_byte);
139 p += sprintf(p, "MRDMODE = 0x%02x, HI = 0x%02x, "
140 "LOW = 0x%02x\n", reg71, hi_byte, lo_byte);
141 #endif /* DEBUG_CMD_REGS */
146 static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
151 p += sprintf(p, "\n");
152 for (i = 0; i < n_cmd_devs; i++) {
153 struct pci_dev *dev = cmd_devs[i];
154 p = print_cmd64x_get_info(p, dev, i);
156 return p-buffer; /* => must be less than 4k! */
159 #endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS) */
162 * Registers and masks for easy access by drive index:
165 static u8 prefetch_regs[4] = {CNTRL, CNTRL, ARTTIM23, ARTTIM23};
166 static u8 prefetch_masks[4] = {CNTRL_DIS_RA0, CNTRL_DIS_RA1, ARTTIM23_DIS_RA2, ARTTIM23_DIS_RA3};
170 * This routine writes the prepared setup/active/recovery counts
171 * for a drive into the cmd646 chipset registers to active them.
173 static void program_drive_counts (ide_drive_t *drive, int setup_count, int active_count, int recovery_count)
176 struct pci_dev *dev = HWIF(drive)->pci_dev;
177 ide_drive_t *drives = HWIF(drive)->drives;
179 static const u8 setup_counts[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
180 static const u8 recovery_counts[] =
181 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
182 static const u8 arttim_regs[2][2] = {
183 { ARTTIM0, ARTTIM1 },
184 { ARTTIM23, ARTTIM23 }
186 static const u8 drwtim_regs[2][2] = {
187 { DRWTIM0, DRWTIM1 },
190 int channel = (int) HWIF(drive)->channel;
191 int slave = (drives != drive); /* Is this really the best way to determine this?? */
193 cmdprintk("program_drive_count parameters = s(%d),a(%d),r(%d),p(%d)\n",
194 setup_count, active_count, recovery_count, drive->present);
196 * Set up address setup count registers.
197 * Primary interface has individual count/timing registers for
198 * each drive. Secondary interface has one common set of registers,
199 * for address setup so we merge these timings, using the slowest
203 drive->drive_data = setup_count;
204 setup_count = IDE_MAX(drives[0].drive_data,
205 drives[1].drive_data);
206 cmdprintk("Secondary interface, setup_count = %d\n",
211 * Convert values to internal chipset representation
213 setup_count = (setup_count > 5) ? 0xc0 : (int) setup_counts[setup_count];
214 active_count &= 0xf; /* Remember, max value is 16 */
215 recovery_count = (int) recovery_counts[recovery_count];
217 cmdprintk("Final values = %d,%d,%d\n",
218 setup_count, active_count, recovery_count);
221 * Now that everything is ready, program the new timings
223 local_irq_save(flags);
225 * Program the address_setup clocks into ARTTIM reg,
226 * and then the active/recovery counts into the DRWTIM reg
228 (void) pci_read_config_byte(dev, arttim_regs[channel][slave], &temp_b);
229 (void) pci_write_config_byte(dev, arttim_regs[channel][slave],
230 ((u8) setup_count) | (temp_b & 0x3f));
231 (void) pci_write_config_byte(dev, drwtim_regs[channel][slave],
232 (u8) ((active_count << 4) | recovery_count));
233 cmdprintk ("Write %x to %x\n",
234 ((u8) setup_count) | (temp_b & 0x3f),
235 arttim_regs[channel][slave]);
236 cmdprintk ("Write %x to %x\n",
237 (u8) ((active_count << 4) | recovery_count),
238 drwtim_regs[channel][slave]);
239 local_irq_restore(flags);
243 * Attempts to set the interface PIO mode.
244 * The preferred method of selecting PIO modes (e.g. mode 4) is
245 * "echo 'piomode:4' > /proc/ide/hdx/settings". Special cases are
246 * 8: prefetch off, 9: prefetch on, 255: auto-select best mode.
247 * Called with 255 at boot time.
250 static void cmd64x_tuneproc (ide_drive_t *drive, u8 mode_wanted)
252 int setup_time, active_time, recovery_time;
253 int clock_time, pio_mode, cycle_time;
254 u8 recovery_count2, cycle_count;
255 int setup_count, active_count, recovery_count;
256 int bus_speed = system_bus_clock();
260 switch (mode_wanted) {
261 case 8: /* set prefetch off */
262 case 9: /* set prefetch on */
264 /*set_prefetch_mode(index, mode_wanted);*/
265 cmdprintk("%s: %sabled cmd640 prefetch\n",
266 drive->name, mode_wanted ? "en" : "dis");
270 mode_wanted = ide_get_best_pio_mode (drive, mode_wanted, 5, &d);
271 pio_mode = d.pio_mode;
272 cycle_time = d.cycle_time;
275 * I copied all this complicated stuff from cmd640.c and made a few
276 * minor changes. For now I am just going to pray that it is correct.
280 setup_time = ide_pio_timings[pio_mode].setup_time;
281 active_time = ide_pio_timings[pio_mode].active_time;
282 recovery_time = cycle_time - (setup_time + active_time);
283 clock_time = 1000 / bus_speed;
284 cycle_count = (cycle_time + clock_time - 1) / clock_time;
286 setup_count = (setup_time + clock_time - 1) / clock_time;
288 active_count = (active_time + clock_time - 1) / clock_time;
290 recovery_count = (recovery_time + clock_time - 1) / clock_time;
291 recovery_count2 = cycle_count - (setup_count + active_count);
292 if (recovery_count2 > recovery_count)
293 recovery_count = recovery_count2;
294 if (recovery_count > 16) {
295 active_count += recovery_count - 16;
298 if (active_count > 16)
299 active_count = 16; /* maximum allowed by cmd646 */
302 * In a perfect world, we might set the drive pio mode here
303 * (using WIN_SETFEATURE) before continuing.
305 * But we do not, because:
306 * 1) this is the wrong place to do it
307 * (proper is do_special() in ide.c)
308 * 2) in practice this is rarely, if ever, necessary
310 program_drive_counts (drive, setup_count, active_count, recovery_count);
312 cmdprintk("%s: selected cmd646 PIO mode%d : %d (%dns)%s, "
314 drive->name, pio_mode, mode_wanted, cycle_time,
315 d.overridden ? " (overriding vendor mode)" : "",
316 setup_count, active_count, recovery_count);
319 static u8 cmd64x_ratemask (ide_drive_t *drive)
321 struct pci_dev *dev = HWIF(drive)->pci_dev;
324 switch(dev->device) {
325 case PCI_DEVICE_ID_CMD_649:
328 case PCI_DEVICE_ID_CMD_648:
331 case PCI_DEVICE_ID_CMD_643:
334 case PCI_DEVICE_ID_CMD_646:
336 unsigned int class_rev = 0;
337 pci_read_config_dword(dev,
338 PCI_CLASS_REVISION, &class_rev);
341 * UltraDMA only supported on PCI646U and PCI646U2, which
342 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
343 * Actually, although the CMD tech support people won't
344 * tell me the details, the 0x03 revision cannot support
345 * UDMA correctly without hardware modifications, and even
346 * then it only works with Quantum disks due to some
347 * hold time assumptions in the 646U part which are fixed
350 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
363 if (!eighty_ninty_three(drive))
364 mode = min(mode, (u8)1);
368 static void config_cmd64x_chipset_for_pio (ide_drive_t *drive, u8 set_speed)
371 u8 set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL);
373 cmd64x_tuneproc(drive, set_pio);
374 speed = XFER_PIO_0 + set_pio;
376 (void) ide_config_drive_speed(drive, speed);
379 static void config_chipset_for_pio (ide_drive_t *drive, u8 set_speed)
381 config_cmd64x_chipset_for_pio(drive, set_speed);
384 static int cmd64x_tune_chipset (ide_drive_t *drive, u8 xferspeed)
386 ide_hwif_t *hwif = HWIF(drive);
387 struct pci_dev *dev = hwif->pci_dev;
389 u8 unit = (drive->select.b.unit & 0x01);
390 u8 regU = 0, pciU = (hwif->channel) ? UDIDETCR1 : UDIDETCR0;
391 u8 regD = 0, pciD = (hwif->channel) ? BMIDESR1 : BMIDESR0;
393 u8 speed = ide_rate_filter(cmd64x_ratemask(drive), xferspeed);
395 if (speed > XFER_PIO_4) {
396 (void) pci_read_config_byte(dev, pciD, ®D);
397 (void) pci_read_config_byte(dev, pciU, ®U);
398 regD &= ~(unit ? 0x40 : 0x20);
399 regU &= ~(unit ? 0xCA : 0x35);
400 (void) pci_write_config_byte(dev, pciD, regD);
401 (void) pci_write_config_byte(dev, pciU, regU);
402 (void) pci_read_config_byte(dev, pciD, ®D);
403 (void) pci_read_config_byte(dev, pciU, ®U);
407 case XFER_UDMA_5: regU |= (unit ? 0x0A : 0x05); break;
408 case XFER_UDMA_4: regU |= (unit ? 0x4A : 0x15); break;
409 case XFER_UDMA_3: regU |= (unit ? 0x8A : 0x25); break;
410 case XFER_UDMA_2: regU |= (unit ? 0x42 : 0x11); break;
411 case XFER_UDMA_1: regU |= (unit ? 0x82 : 0x21); break;
412 case XFER_UDMA_0: regU |= (unit ? 0xC2 : 0x31); break;
413 case XFER_MW_DMA_2: regD |= (unit ? 0x40 : 0x10); break;
414 case XFER_MW_DMA_1: regD |= (unit ? 0x80 : 0x20); break;
415 case XFER_MW_DMA_0: regD |= (unit ? 0xC0 : 0x30); break;
416 case XFER_SW_DMA_2: regD |= (unit ? 0x40 : 0x10); break;
417 case XFER_SW_DMA_1: regD |= (unit ? 0x80 : 0x20); break;
418 case XFER_SW_DMA_0: regD |= (unit ? 0xC0 : 0x30); break;
419 case XFER_PIO_4: cmd64x_tuneproc(drive, 4); break;
420 case XFER_PIO_3: cmd64x_tuneproc(drive, 3); break;
421 case XFER_PIO_2: cmd64x_tuneproc(drive, 2); break;
422 case XFER_PIO_1: cmd64x_tuneproc(drive, 1); break;
423 case XFER_PIO_0: cmd64x_tuneproc(drive, 0); break;
429 if (speed > XFER_PIO_4) {
430 (void) pci_write_config_byte(dev, pciU, regU);
431 regD |= (unit ? 0x40 : 0x20);
432 (void) pci_write_config_byte(dev, pciD, regD);
435 return (ide_config_drive_speed(drive, speed));
438 static int config_chipset_for_dma (ide_drive_t *drive)
440 u8 speed = ide_dma_speed(drive, cmd64x_ratemask(drive));
442 config_chipset_for_pio(drive, !speed);
447 if(ide_set_xfer_rate(drive, speed))
450 if (!drive->init_speed)
451 drive->init_speed = speed;
453 return ide_dma_enable(drive);
456 static int cmd64x_config_drive_for_dma (ide_drive_t *drive)
458 ide_hwif_t *hwif = HWIF(drive);
459 struct hd_driveid *id = drive->id;
461 if ((id->capability & 1) != 0 && drive->autodma) {
462 /* Consult the list of known "bad" drives */
463 if (hwif->ide_dma_bad_drive(drive))
465 if ((id->field_valid & 4) && cmd64x_ratemask(drive)) {
466 if (id->dma_ultra & hwif->ultra_mask) {
467 /* Force if Capable UltraDMA */
468 int dma = config_chipset_for_dma(drive);
469 if ((id->field_valid & 2) && !dma)
472 } else if (id->field_valid & 2) {
474 if ((id->dma_mword & hwif->mwdma_mask) ||
475 (id->dma_1word & hwif->swdma_mask)) {
476 /* Force if Capable regular DMA modes */
477 if (!config_chipset_for_dma(drive))
480 } else if (hwif->ide_dma_good_drive(drive) &&
481 (id->eide_dma_time < 150)) {
482 /* Consult the list of known "good" drives */
483 if (!config_chipset_for_dma(drive))
488 return hwif->ide_dma_on(drive);
489 } else if ((id->capability & 8) || (id->field_valid & 2)) {
492 config_chipset_for_pio(drive, 1);
493 return hwif->ide_dma_off_quietly(drive);
495 /* IORDY not supported */
499 static int cmd64x_alt_dma_status (struct pci_dev *dev)
501 switch(dev->device) {
502 case PCI_DEVICE_ID_CMD_648:
503 case PCI_DEVICE_ID_CMD_649:
511 static int cmd64x_ide_dma_end (ide_drive_t *drive)
513 u8 dma_stat = 0, dma_cmd = 0;
514 ide_hwif_t *hwif = HWIF(drive);
515 struct pci_dev *dev = hwif->pci_dev;
517 drive->waiting_for_dma = 0;
518 /* read DMA command state */
519 dma_cmd = hwif->INB(hwif->dma_command);
521 hwif->OUTB((dma_cmd & ~1), hwif->dma_command);
523 dma_stat = hwif->INB(hwif->dma_status);
524 /* clear the INTR & ERROR bits */
525 hwif->OUTB(dma_stat|6, hwif->dma_status);
526 if (cmd64x_alt_dma_status(dev)) {
528 u8 dma_mask = (hwif->channel) ? ARTTIM23_INTR_CH1 :
530 u8 dma_reg = (hwif->channel) ? ARTTIM2 : CFR;
531 (void) pci_read_config_byte(dev, dma_reg, &dma_intr);
532 /* clear the INTR bit */
533 (void) pci_write_config_byte(dev, dma_reg, dma_intr|dma_mask);
535 /* purge DMA mappings */
536 ide_destroy_dmatable(drive);
537 /* verify good DMA status */
538 return (dma_stat & 7) != 4;
541 static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
543 ide_hwif_t *hwif = HWIF(drive);
544 struct pci_dev *dev = hwif->pci_dev;
545 u8 dma_alt_stat = 0, mask = (hwif->channel) ? MRDMODE_INTR_CH1 :
547 u8 dma_stat = hwif->INB(hwif->dma_status);
549 (void) pci_read_config_byte(dev, MRDMODE, &dma_alt_stat);
551 printk("%s: dma_stat: 0x%02x dma_alt_stat: "
552 "0x%02x mask: 0x%02x\n", drive->name,
553 dma_stat, dma_alt_stat, mask);
555 if (!(dma_alt_stat & mask))
558 /* return 1 if INTR asserted */
559 if ((dma_stat & 4) == 4)
566 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
567 * event order for DMA transfers.
570 static int cmd646_1_ide_dma_end (ide_drive_t *drive)
572 ide_hwif_t *hwif = HWIF(drive);
573 u8 dma_stat = 0, dma_cmd = 0;
575 drive->waiting_for_dma = 0;
577 dma_stat = hwif->INB(hwif->dma_status);
578 /* read DMA command state */
579 dma_cmd = hwif->INB(hwif->dma_command);
581 hwif->OUTB((dma_cmd & ~1), hwif->dma_command);
582 /* clear the INTR & ERROR bits */
583 hwif->OUTB(dma_stat|6, hwif->dma_status);
584 /* and free any DMA resources */
585 ide_destroy_dmatable(drive);
586 /* verify good DMA status */
587 return (dma_stat & 7) != 4;
590 static unsigned int __init init_chipset_cmd64x (struct pci_dev *dev, const char *name)
595 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
599 if (dev->resource[PCI_ROM_RESOURCE].start) {
600 pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
601 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
605 switch(dev->device) {
606 case PCI_DEVICE_ID_CMD_643:
608 case PCI_DEVICE_ID_CMD_646:
609 printk(KERN_INFO "%s: chipset revision 0x%02X, ", name, class_rev);
613 printk("UltraDMA Capable");
616 printk("MultiWord DMA Force Limited");
620 printk("MultiWord DMA Limited, IRQ workaround enabled");
625 case PCI_DEVICE_ID_CMD_648:
626 case PCI_DEVICE_ID_CMD_649:
632 /* Set a good latency timer and cache line size value. */
633 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
635 (void) pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x10);
639 /* Setup interrupts. */
640 (void) pci_read_config_byte(dev, MRDMODE, &mrdmode);
642 (void) pci_write_config_byte(dev, MRDMODE, mrdmode);
644 /* Use MEMORY READ LINE for reads.
645 * NOTE: Although not mentioned in the PCI0646U specs,
646 * these bits are write only and won't be read
647 * back as set or not. The PCI0646U2 specs clarify
650 (void) pci_write_config_byte(dev, MRDMODE, mrdmode | 0x02);
652 /* Set reasonable active/recovery/address-setup values. */
653 (void) pci_write_config_byte(dev, ARTTIM0, 0x40);
654 (void) pci_write_config_byte(dev, DRWTIM0, 0x3f);
655 (void) pci_write_config_byte(dev, ARTTIM1, 0x40);
656 (void) pci_write_config_byte(dev, DRWTIM1, 0x3f);
658 (void) pci_write_config_byte(dev, ARTTIM23, 0x1c);
660 (void) pci_write_config_byte(dev, ARTTIM23, 0x5c);
662 (void) pci_write_config_byte(dev, DRWTIM23, 0x3f);
663 (void) pci_write_config_byte(dev, DRWTIM3, 0x3f);
665 (void) pci_write_config_byte(dev, UDIDETCR0, 0xf0);
666 #endif /* CONFIG_PPC */
668 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
670 cmd_devs[n_cmd_devs++] = dev;
674 ide_pci_register_host_proc(&cmd64x_procs[0]);
676 #endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_PROC_FS */
681 static unsigned int __init ata66_cmd64x (ide_hwif_t *hwif)
683 u8 ata66 = 0, mask = (hwif->channel) ? 0x02 : 0x01;
685 switch(hwif->pci_dev->device) {
686 case PCI_DEVICE_ID_CMD_643:
687 case PCI_DEVICE_ID_CMD_646:
692 pci_read_config_byte(hwif->pci_dev, BMIDECSR, &ata66);
693 return (ata66 & mask) ? 1 : 0;
696 static void __init init_hwif_cmd64x (ide_hwif_t *hwif)
698 struct pci_dev *dev = hwif->pci_dev;
699 unsigned int class_rev;
702 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
705 hwif->tuneproc = &cmd64x_tuneproc;
706 hwif->speedproc = &cmd64x_tune_chipset;
708 if (!hwif->dma_base) {
709 hwif->drives[0].autotune = 1;
710 hwif->drives[1].autotune = 1;
716 hwif->ultra_mask = 0x3f;
717 hwif->mwdma_mask = 0x07;
718 hwif->swdma_mask = 0x07;
720 if (dev->device == PCI_DEVICE_ID_CMD_643)
721 hwif->ultra_mask = 0x80;
722 if (dev->device == PCI_DEVICE_ID_CMD_646)
723 hwif->ultra_mask = (class_rev > 0x04) ? 0x07 : 0x80;
724 if (dev->device == PCI_DEVICE_ID_CMD_648)
725 hwif->ultra_mask = 0x1f;
727 hwif->ide_dma_check = &cmd64x_config_drive_for_dma;
728 if (!(hwif->udma_four))
729 hwif->udma_four = ata66_cmd64x(hwif);
731 if (dev->device == PCI_DEVICE_ID_CMD_646) {
732 hwif->chipset = ide_cmd646;
733 if (class_rev == 0x01) {
734 hwif->ide_dma_end = &cmd646_1_ide_dma_end;
736 hwif->ide_dma_end = &cmd64x_ide_dma_end;
737 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
740 hwif->ide_dma_end = &cmd64x_ide_dma_end;
741 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
747 hwif->drives[0].autodma = hwif->autodma;
748 hwif->drives[1].autodma = hwif->autodma;
751 static void __init init_dma_cmd64x (ide_hwif_t *hwif, unsigned long dmabase)
753 ide_setup_dma(hwif, dmabase, 8);
756 extern void ide_setup_pci_device(struct pci_dev *, ide_pci_device_t *);
758 static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
760 ide_pci_device_t *d = &cmd64x_chipsets[id->driver_data];
761 if (dev->device != d->device)
763 ide_setup_pci_device(dev, d);
768 static struct pci_device_id cmd64x_pci_tbl[] __devinitdata = {
769 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
770 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
771 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
772 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
776 static struct pci_driver driver = {
777 .name = "CMD64x IDE",
778 .id_table = cmd64x_pci_tbl,
779 .probe = cmd64x_init_one,
782 static int cmd64x_ide_init(void)
784 return ide_pci_register_driver(&driver);
787 static void cmd64x_ide_exit(void)
789 ide_pci_unregister_driver(&driver);
792 module_init(cmd64x_ide_init);
793 module_exit(cmd64x_ide_exit);
795 MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
796 MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
797 MODULE_LICENSE("GPL");