4 #include <linux/config.h>
8 #define DISPLAY_PDC202XX_TIMINGS
11 #define SPLIT_BYTE(B,H,L) ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
14 #define PDC202XX_DEBUG_DRIVE_INFO 0
15 #define PDC202XX_DECODE_REGISTER_INFO 0
17 const static char *pdc_quirk_drives[] = {
18 "QUANTUM FIREBALLlct08 08",
19 "QUANTUM FIREBALLP KA6.4",
20 "QUANTUM FIREBALLP KA9.1",
21 "QUANTUM FIREBALLP LM20.4",
22 "QUANTUM FIREBALLP KX13.6",
23 "QUANTUM FIREBALLP KX20.5",
24 "QUANTUM FIREBALLP KX27.3",
25 "QUANTUM FIREBALLP LM20.5",
30 #define SYNC_ERRDY_EN 0xC0
32 #define SYNC_IN 0x80 /* control bit, different for master vs. slave drives */
33 #define ERRDY_EN 0x40 /* control bit, different for master vs. slave drives */
34 #define IORDY_EN 0x20 /* PIO: IOREADY */
35 #define PREFETCH_EN 0x10 /* PIO: PREFETCH */
37 #define PA3 0x08 /* PIO"A" timing */
38 #define PA2 0x04 /* PIO"A" timing */
39 #define PA1 0x02 /* PIO"A" timing */
40 #define PA0 0x01 /* PIO"A" timing */
44 #define MB2 0x80 /* DMA"B" timing */
45 #define MB1 0x40 /* DMA"B" timing */
46 #define MB0 0x20 /* DMA"B" timing */
48 #define PB4 0x10 /* PIO_FORCE 1:0 */
50 #define PB3 0x08 /* PIO"B" timing */ /* PIO flow Control mode */
51 #define PB2 0x04 /* PIO"B" timing */ /* PIO 4 */
52 #define PB1 0x02 /* PIO"B" timing */ /* PIO 3 half */
53 #define PB0 0x01 /* PIO"B" timing */ /* PIO 3 other half */
56 #define IORDYp_NO_SPEED 0x4F
57 #define SPEED_DIS 0x0F
64 #define MC3 0x08 /* DMA"C" timing */
65 #define MC2 0x04 /* DMA"C" timing */
66 #define MC1 0x02 /* DMA"C" timing */
67 #define MC0 0x01 /* DMA"C" timing */
69 #if PDC202XX_DECODE_REGISTER_INFO
76 static void decode_registers (u8 registers, u8 value)
78 u8 bit = 0, bit1 = 0, bit2 = 0;
83 printk("A Register ");
84 if (value & 0x80) printk("SYNC_IN ");
85 if (value & 0x40) printk("ERRDY_EN ");
86 if (value & 0x20) printk("IORDY_EN ");
87 if (value & 0x10) printk("PREFETCH_EN ");
88 if (value & 0x08) { printk("PA3 ");bit2 |= 0x08; }
89 if (value & 0x04) { printk("PA2 ");bit2 |= 0x04; }
90 if (value & 0x02) { printk("PA1 ");bit2 |= 0x02; }
91 if (value & 0x01) { printk("PA0 ");bit2 |= 0x01; }
92 printk("PIO(A) = %d ", bit2);
96 printk("B Register ");
97 if (value & 0x80) { printk("MB2 ");bit1 |= 0x80; }
98 if (value & 0x40) { printk("MB1 ");bit1 |= 0x40; }
99 if (value & 0x20) { printk("MB0 ");bit1 |= 0x20; }
100 printk("DMA(B) = %d ", bit1 >> 5);
101 if (value & 0x10) printk("PIO_FORCED/PB4 ");
102 if (value & 0x08) { printk("PB3 ");bit2 |= 0x08; }
103 if (value & 0x04) { printk("PB2 ");bit2 |= 0x04; }
104 if (value & 0x02) { printk("PB1 ");bit2 |= 0x02; }
105 if (value & 0x01) { printk("PB0 ");bit2 |= 0x01; }
106 printk("PIO(B) = %d ", bit2);
110 printk("C Register ");
111 if (value & 0x80) printk("DMARQp ");
112 if (value & 0x40) printk("IORDYp ");
113 if (value & 0x20) printk("DMAR_EN ");
114 if (value & 0x10) printk("DMAW_EN ");
116 if (value & 0x08) { printk("MC3 ");bit2 |= 0x08; }
117 if (value & 0x04) { printk("MC2 ");bit2 |= 0x04; }
118 if (value & 0x02) { printk("MC1 ");bit2 |= 0x02; }
119 if (value & 0x01) { printk("MC0 ");bit2 |= 0x01; }
120 printk("DMA(C) = %d ", bit2);
123 printk("D Register ");
128 printk("\n %s ", (registers & REG_D) ? "DP" :
129 (registers & REG_C) ? "CP" :
130 (registers & REG_B) ? "BP" :
131 (registers & REG_A) ? "AP" : "ERROR");
132 for (bit=128;bit>0;bit/=2)
133 printk("%s", (value & bit) ? "1" : "0");
137 #endif /* PDC202XX_DECODE_REGISTER_INFO */
139 #define set_2regs(a, b) \
141 hwif->OUTB((a + adj), indexreg); \
142 hwif->OUTB(b, datareg); \
145 #define set_ultra(a, b, c) \
147 set_2regs(0x10,(a)); \
148 set_2regs(0x11,(b)); \
149 set_2regs(0x12,(c)); \
152 #define set_ata2(a, b) \
154 set_2regs(0x0e,(a)); \
155 set_2regs(0x0f,(b)); \
158 #define set_pio(a, b, c) \
160 set_2regs(0x0c,(a)); \
161 set_2regs(0x0d,(b)); \
162 set_2regs(0x13,(c)); \
165 #define DISPLAY_PDC202XX_TIMINGS
167 #if defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS)
168 #include <linux/stat.h>
169 #include <linux/proc_fs.h>
171 static u8 pdcnew_proc;
173 static int pdcnew_get_info(char *, char **, off_t, int);
175 static ide_pci_host_proc_t pdcnew_procs[] __initdata = {
179 .get_info = pdcnew_get_info,
183 #endif /* DISPLAY_PDC202XX_TIMINGS && CONFIG_PROC_FS */
186 static void init_setup_pdcnew(struct pci_dev *, ide_pci_device_t *);
187 static void init_setup_pdc20270(struct pci_dev *, ide_pci_device_t *);
188 static void init_setup_pdc20276(struct pci_dev *dev, ide_pci_device_t *d);
189 static unsigned int init_chipset_pdcnew(struct pci_dev *, const char *);
190 static void init_hwif_pdc202new(ide_hwif_t *);
191 static void init_dma_pdc202new(ide_hwif_t *, unsigned long);
193 static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
195 .vendor = PCI_VENDOR_ID_PROMISE,
196 .device = PCI_DEVICE_ID_PROMISE_20268,
198 .init_setup = init_setup_pdcnew,
199 .init_chipset = init_chipset_pdcnew,
201 .init_hwif = init_hwif_pdc202new,
202 .init_dma = init_dma_pdc202new,
205 .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
206 .bootable = OFF_BOARD,
209 .vendor = PCI_VENDOR_ID_PROMISE,
210 .device = PCI_DEVICE_ID_PROMISE_20269,
212 .init_setup = init_setup_pdcnew,
213 .init_chipset = init_chipset_pdcnew,
215 .init_hwif = init_hwif_pdc202new,
216 .init_dma = init_dma_pdc202new,
219 .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
220 .bootable = OFF_BOARD,
223 .vendor = PCI_VENDOR_ID_PROMISE,
224 .device = PCI_DEVICE_ID_PROMISE_20270,
226 .init_setup = init_setup_pdc20270,
227 .init_chipset = init_chipset_pdcnew,
229 .init_hwif = init_hwif_pdc202new,
230 .init_dma = init_dma_pdc202new,
233 #ifdef CONFIG_PDC202XX_FORCE
234 .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
235 #else /* !CONFIG_PDC202XX_FORCE */
236 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
238 .bootable = OFF_BOARD,
241 .vendor = PCI_VENDOR_ID_PROMISE,
242 .device = PCI_DEVICE_ID_PROMISE_20271,
244 .init_setup = init_setup_pdcnew,
245 .init_chipset = init_chipset_pdcnew,
247 .init_hwif = init_hwif_pdc202new,
248 .init_dma = init_dma_pdc202new,
251 .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
252 .bootable = OFF_BOARD,
255 .vendor = PCI_VENDOR_ID_PROMISE,
256 .device = PCI_DEVICE_ID_PROMISE_20275,
258 .init_setup = init_setup_pdc20276,
259 .init_chipset = init_chipset_pdcnew,
261 .init_hwif = init_hwif_pdc202new,
262 .init_dma = init_dma_pdc202new,
265 .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
266 .bootable = OFF_BOARD,
269 .vendor = PCI_VENDOR_ID_PROMISE,
270 .device = PCI_DEVICE_ID_PROMISE_20276,
272 .init_setup = init_setup_pdc20276,
273 .init_chipset = init_chipset_pdcnew,
275 .init_hwif = init_hwif_pdc202new,
276 .init_dma = init_dma_pdc202new,
279 #ifdef CONFIG_PDC202XX_FORCE
280 .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
281 #else /* !CONFIG_PDC202XX_FORCE */
282 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
284 .bootable = OFF_BOARD,
287 .vendor = PCI_VENDOR_ID_PROMISE,
288 .device = PCI_DEVICE_ID_PROMISE_20277,
290 .init_setup = init_setup_pdc20276,
291 .init_chipset = init_chipset_pdcnew,
293 .init_hwif = init_hwif_pdc202new,
294 .init_dma = init_dma_pdc202new,
297 .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
298 .bootable = OFF_BOARD,
308 #endif /* PDC202XX_H */