2 * linux/drivers/ide/pci/serverworks.c Version 0.8 25 Ebr 2003
4 * Copyright (C) 1998-2000 Michel Aubry
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
6 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
7 * Portions copyright (c) 2001 Sun Microsystems
10 * RCC/ServerWorks IDE driver for Linux
12 * OSB4: `Open South Bridge' IDE Interface (fn 1)
13 * supports UDMA mode 2 (33 MB/s)
15 * CSB5: `Champion South Bridge' IDE Interface (fn 1)
16 * all revisions support UDMA mode 4 (66 MB/s)
17 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
19 * *** The CSB5 does not provide ANY register ***
20 * *** to detect 80-conductor cable presence. ***
22 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
25 * Available under NDA only. Errata info very hard to get.
29 #include <linux/config.h>
30 #include <linux/types.h>
31 #include <linux/module.h>
32 #include <linux/kernel.h>
33 #include <linux/ioport.h>
34 #include <linux/pci.h>
35 #include <linux/hdreg.h>
36 #include <linux/ide.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
42 #include "ide_modes.h"
43 #include "serverworks.h"
45 static u8 svwks_revision = 0;
46 static struct pci_dev *isa_dev;
48 #if defined(DISPLAY_SVWKS_TIMINGS) && defined(CONFIG_PROC_FS)
49 #include <linux/stat.h>
50 #include <linux/proc_fs.h>
52 static u8 svwks_proc = 0;
53 #define SVWKS_MAX_DEVS 2
54 static struct pci_dev *svwks_devs[SVWKS_MAX_DEVS];
55 static int n_svwks_devs;
57 static int svwks_get_info (char *buffer, char **addr, off_t offset, int count)
63 "ServerWorks OSB4/CSB5/CSB6\n");
65 for (i = 0; i < n_svwks_devs; i++) {
66 struct pci_dev *dev = svwks_devs[i];
67 unsigned long bibma = pci_resource_start(dev, 4);
72 pci_read_config_dword(dev, 0x40, ®40);
73 pci_read_config_dword(dev, 0x44, ®44);
74 pci_read_config_word(dev, 0x48, ®48);
75 pci_read_config_byte(dev, 0x54, ®54);
76 pci_read_config_word(dev, 0x56, ®56);
79 * at that point bibma+0x2 et bibma+0xa are byte registers
82 c0 = inb_p(bibma + 0x02);
83 c1 = inb_p(bibma + 0x0a);
85 p += sprintf(p, "\n ServerWorks ");
87 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
88 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
89 p += sprintf(p, "CSB6 ");
91 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
92 p += sprintf(p, "CSB5 ");
94 case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE:
95 p += sprintf(p, "OSB4 ");
98 p += sprintf(p, "%04x ", dev->device);
101 p += sprintf(p, "Chipset (rev %02x)\n", svwks_revision);
103 p += sprintf(p, "------------------------------- "
105 "---------------------------------\n");
106 p += sprintf(p, "--------------- Primary Channel "
107 "---------------- Secondary Channel "
109 p += sprintf(p, " %sabled"
111 (c0&0x80) ? "dis" : " en",
112 (c1&0x80) ? "dis" : " en");
113 p += sprintf(p, "--------------- drive0 --------- drive1 "
114 "-------- drive0 ---------- drive1 ------\n");
115 p += sprintf(p, "DMA enabled: %s %s"
117 (c0&0x20) ? "yes" : "no ",
118 (c0&0x40) ? "yes" : "no ",
119 (c1&0x20) ? "yes" : "no ",
120 (c1&0x40) ? "yes" : "no " );
121 p += sprintf(p, "UDMA enabled: %s %s"
123 (reg54 & 0x01) ? "yes" : "no ",
124 (reg54 & 0x02) ? "yes" : "no ",
125 (reg54 & 0x04) ? "yes" : "no ",
126 (reg54 & 0x08) ? "yes" : "no " );
127 p += sprintf(p, "UDMA enabled: %s %s"
129 ((reg56&0x0005)==0x0005)?"5":
130 ((reg56&0x0004)==0x0004)?"4":
131 ((reg56&0x0003)==0x0003)?"3":
132 ((reg56&0x0002)==0x0002)?"2":
133 ((reg56&0x0001)==0x0001)?"1":
134 ((reg56&0x000F))?"?":"0",
135 ((reg56&0x0050)==0x0050)?"5":
136 ((reg56&0x0040)==0x0040)?"4":
137 ((reg56&0x0030)==0x0030)?"3":
138 ((reg56&0x0020)==0x0020)?"2":
139 ((reg56&0x0010)==0x0010)?"1":
140 ((reg56&0x00F0))?"?":"0",
141 ((reg56&0x0500)==0x0500)?"5":
142 ((reg56&0x0400)==0x0400)?"4":
143 ((reg56&0x0300)==0x0300)?"3":
144 ((reg56&0x0200)==0x0200)?"2":
145 ((reg56&0x0100)==0x0100)?"1":
146 ((reg56&0x0F00))?"?":"0",
147 ((reg56&0x5000)==0x5000)?"5":
148 ((reg56&0x4000)==0x4000)?"4":
149 ((reg56&0x3000)==0x3000)?"3":
150 ((reg56&0x2000)==0x2000)?"2":
151 ((reg56&0x1000)==0x1000)?"1":
152 ((reg56&0xF000))?"?":"0");
153 p += sprintf(p, "DMA enabled: %s %s"
155 ((reg44&0x00002000)==0x00002000)?"2":
156 ((reg44&0x00002100)==0x00002100)?"1":
157 ((reg44&0x00007700)==0x00007700)?"0":
158 ((reg44&0x0000FF00)==0x0000FF00)?"X":"?",
159 ((reg44&0x00000020)==0x00000020)?"2":
160 ((reg44&0x00000021)==0x00000021)?"1":
161 ((reg44&0x00000077)==0x00000077)?"0":
162 ((reg44&0x000000FF)==0x000000FF)?"X":"?",
163 ((reg44&0x20000000)==0x20000000)?"2":
164 ((reg44&0x21000000)==0x21000000)?"1":
165 ((reg44&0x77000000)==0x77000000)?"0":
166 ((reg44&0xFF000000)==0xFF000000)?"X":"?",
167 ((reg44&0x00200000)==0x00200000)?"2":
168 ((reg44&0x00210000)==0x00210000)?"1":
169 ((reg44&0x00770000)==0x00770000)?"0":
170 ((reg44&0x00FF0000)==0x00FF0000)?"X":"?");
172 p += sprintf(p, "PIO enabled: %s %s"
174 ((reg40&0x00002000)==0x00002000)?"4":
175 ((reg40&0x00002200)==0x00002200)?"3":
176 ((reg40&0x00003400)==0x00003400)?"2":
177 ((reg40&0x00004700)==0x00004700)?"1":
178 ((reg40&0x00005D00)==0x00005D00)?"0":"?",
179 ((reg40&0x00000020)==0x00000020)?"4":
180 ((reg40&0x00000022)==0x00000022)?"3":
181 ((reg40&0x00000034)==0x00000034)?"2":
182 ((reg40&0x00000047)==0x00000047)?"1":
183 ((reg40&0x0000005D)==0x0000005D)?"0":"?",
184 ((reg40&0x20000000)==0x20000000)?"4":
185 ((reg40&0x22000000)==0x22000000)?"3":
186 ((reg40&0x34000000)==0x34000000)?"2":
187 ((reg40&0x47000000)==0x47000000)?"1":
188 ((reg40&0x5D000000)==0x5D000000)?"0":"?",
189 ((reg40&0x00200000)==0x00200000)?"4":
190 ((reg40&0x00220000)==0x00220000)?"3":
191 ((reg40&0x00340000)==0x00340000)?"2":
192 ((reg40&0x00470000)==0x00470000)?"1":
193 ((reg40&0x005D0000)==0x005D0000)?"0":"?");
196 p += sprintf(p, "\n");
198 /* p - buffer must be less than 4k! */
199 len = (p - buffer) - offset;
200 *addr = buffer + offset;
202 return len > count ? count : len;
204 #endif /* defined(DISPLAY_SVWKS_TIMINGS) && defined(CONFIG_PROC_FS) */
206 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
209 if (!strcmp(*list++, drive->id->model))
214 static u8 svwks_ratemask (ide_drive_t *drive)
216 struct pci_dev *dev = HWIF(drive)->pci_dev;
220 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
222 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
225 pci_read_config_dword(isa_dev, 0x64, ®);
228 * Don't enable UDMA on disk devices for the moment
230 if(drive->media == ide_disk)
232 /* Check the OSB4 DMA33 enable bit */
233 return ((reg & 0x00004000) == 0x00004000) ? 1 : 0;
234 } else if (svwks_revision < SVWKS_CSB5_REVISION_NEW) {
236 } else if (svwks_revision >= SVWKS_CSB5_REVISION_NEW) {
238 pci_read_config_byte(dev, 0x5A, &btr);
240 if (!eighty_ninty_three(drive))
241 mode = min(mode, (u8)1);
242 /* If someone decides to do UDMA133 on CSB5 the same
243 issue will bite so be inclusive */
244 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
247 if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
248 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
249 (!(PCI_FUNC(dev->devfn) & 1)))
254 static u8 svwks_csb_check (struct pci_dev *dev)
256 switch (dev->device) {
257 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
258 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
259 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
266 static int svwks_tune_chipset (ide_drive_t *drive, u8 xferspeed)
268 u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
269 u8 dma_modes[] = { 0x77, 0x21, 0x20 };
270 u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
271 u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
272 u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
274 ide_hwif_t *hwif = HWIF(drive);
275 struct pci_dev *dev = hwif->pci_dev;
277 u8 pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
278 u8 unit = (drive->select.b.unit & 0x01);
279 u8 csb5 = svwks_csb_check(dev);
280 u8 ultra_enable = 0, ultra_timing = 0;
281 u8 dma_timing = 0, pio_timing = 0;
284 if (xferspeed == 255) /* PIO auto-tuning */
285 speed = XFER_PIO_0 + pio;
287 speed = ide_rate_filter(svwks_ratemask(drive), xferspeed);
289 /* If we are about to put a disk into UDMA mode we screwed up.
290 Our code assumes we never _ever_ do this on an OSB4 */
292 if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
293 drive->media == ide_disk && speed >= XFER_UDMA_0)
296 pci_read_config_byte(dev, drive_pci[drive->dn], &pio_timing);
297 pci_read_config_byte(dev, drive_pci2[drive->dn], &dma_timing);
298 pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
299 pci_read_config_word(dev, 0x4A, &csb5_pio);
300 pci_read_config_byte(dev, 0x54, &ultra_enable);
302 /* Per Specified Design by OEM, and ASIC Architect */
303 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
304 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
305 if (!drive->init_speed) {
306 u8 dma_stat = hwif->INB(hwif->dma_status);
309 if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) &&
310 ((dma_stat & (1<<(5+unit))) == (1<<(5+unit)))) {
311 drive->current_speed = drive->init_speed = XFER_UDMA_0 + udma_modes[(ultra_timing >> (4*unit)) & ~(0xF0)];
313 } else if ((dma_timing) &&
314 ((dma_stat&(1<<(5+unit)))==(1<<(5+unit)))) {
315 u8 dmaspeed = dma_timing;
318 if ((dmaspeed & 0x20) == 0x20)
319 dmaspeed = XFER_MW_DMA_2;
320 else if ((dmaspeed & 0x21) == 0x21)
321 dmaspeed = XFER_MW_DMA_1;
322 else if ((dmaspeed & 0x77) == 0x77)
323 dmaspeed = XFER_MW_DMA_0;
326 drive->current_speed = drive->init_speed = dmaspeed;
328 } else if (pio_timing) {
329 u8 piospeed = pio_timing;
332 if ((piospeed & 0x20) == 0x20)
333 piospeed = XFER_PIO_4;
334 else if ((piospeed & 0x22) == 0x22)
335 piospeed = XFER_PIO_3;
336 else if ((piospeed & 0x34) == 0x34)
337 piospeed = XFER_PIO_2;
338 else if ((piospeed & 0x47) == 0x47)
339 piospeed = XFER_PIO_1;
340 else if ((piospeed & 0x5d) == 0x5d)
341 piospeed = XFER_PIO_0;
343 goto oem_setup_failed;
344 drive->current_speed = drive->init_speed = piospeed;
354 ultra_timing &= ~(0x0F << (4*unit));
355 ultra_enable &= ~(0x01 << drive->dn);
356 csb5_pio &= ~(0x0F << (4*drive->dn));
364 pio_timing |= pio_modes[speed - XFER_PIO_0];
365 csb5_pio |= ((speed - XFER_PIO_0) << (4*drive->dn));
371 pio_timing |= pio_modes[pio];
372 csb5_pio |= (pio << (4*drive->dn));
373 dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
382 pio_timing |= pio_modes[pio];
383 csb5_pio |= (pio << (4*drive->dn));
384 dma_timing |= dma_modes[2];
385 ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
386 ultra_enable |= (0x01 << drive->dn);
391 pci_write_config_byte(dev, drive_pci[drive->dn], pio_timing);
393 pci_write_config_word(dev, 0x4A, csb5_pio);
395 pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
396 pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
397 pci_write_config_byte(dev, 0x54, ultra_enable);
399 return (ide_config_drive_speed(drive, speed));
402 static void config_chipset_for_pio (ide_drive_t *drive)
404 u16 eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
405 u16 xfer_pio = drive->id->eide_pio_modes;
406 u8 timing, speed, pio;
408 pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
413 if (drive->id->eide_pio_iordy > 0)
416 drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
419 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
420 (drive->id->eide_pio_modes & 2) ? 0x04 :
421 (drive->id->eide_pio_modes & 1) ? 0x03 :
422 (drive->id->tPIO & 2) ? 0x02 :
423 (drive->id->tPIO & 1) ? 0x01 : xfer_pio;
425 timing = (xfer_pio >= pio) ? xfer_pio : pio;
428 case 4: speed = XFER_PIO_4;break;
429 case 3: speed = XFER_PIO_3;break;
430 case 2: speed = XFER_PIO_2;break;
431 case 1: speed = XFER_PIO_1;break;
433 speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
436 (void) svwks_tune_chipset(drive, speed);
437 drive->current_speed = speed;
440 static void svwks_tune_drive (ide_drive_t *drive, u8 pio)
443 (void) svwks_tune_chipset(drive, 255);
445 (void) svwks_tune_chipset(drive, (XFER_PIO_0 + pio));
448 static int config_chipset_for_dma (ide_drive_t *drive)
450 u8 speed = ide_dma_speed(drive, svwks_ratemask(drive));
453 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
455 (void) svwks_tune_chipset(drive, speed);
456 return ide_dma_enable(drive);
459 static int svwks_config_drive_xfer_rate (ide_drive_t *drive)
461 ide_hwif_t *hwif = HWIF(drive);
462 struct hd_driveid *id = drive->id;
464 drive->init_speed = 0;
466 if ((id->capability & 1) && drive->autodma) {
467 /* Consult the list of known "bad" drives */
468 if (hwif->ide_dma_bad_drive(drive))
470 if (id->field_valid & 4) {
471 if (id->dma_ultra & hwif->ultra_mask) {
472 /* Force if Capable UltraDMA */
473 int dma = config_chipset_for_dma(drive);
474 if ((id->field_valid & 2) && !dma)
477 /* UDMA disabled by mask, try other DMA modes */
479 } else if (id->field_valid & 2) {
481 if ((id->dma_mword & hwif->mwdma_mask) ||
482 (id->dma_1word & hwif->swdma_mask)) {
483 /* Force if Capable regular DMA modes */
484 if (!config_chipset_for_dma(drive))
487 } else if (hwif->ide_dma_good_drive(drive) &&
488 (id->eide_dma_time < 150)) {
489 /* Consult the list of known "good" drives */
490 if (!config_chipset_for_dma(drive))
495 return hwif->ide_dma_on(drive);
496 } else if ((id->capability & 8) || (id->field_valid & 2)) {
499 config_chipset_for_pio(drive);
500 // hwif->tuneproc(drive, 5);
501 return hwif->ide_dma_off_quietly(drive);
503 /* IORDY not supported */
507 /* This can go soon */
509 static int svwks_ide_dma_end (ide_drive_t *drive)
511 return __ide_dma_end(drive);
514 static unsigned int __init init_chipset_svwks (struct pci_dev *dev, const char *name)
519 /* save revision id to determine DMA capability */
520 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
522 /* force Master Latency Timer value to 64 PCICLKs */
523 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
525 /* OSB4 : South Bridge and IDE */
526 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
527 isa_dev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,
528 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
530 pci_read_config_dword(isa_dev, 0x64, ®);
531 reg &= ~0x00002000; /* disable 600ns interrupt mask */
532 if(!(reg & 0x00004000))
533 printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
534 reg |= 0x00004000; /* enable UDMA/33 support */
535 pci_write_config_dword(isa_dev, 0x64, reg);
539 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
540 else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
541 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
542 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
543 // u32 pioreg = 0, dmareg = 0;
545 /* Third Channel Test */
546 if (!(PCI_FUNC(dev->devfn) & 1)) {
548 struct pci_dev * findev = NULL;
550 findev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,
551 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
553 pci_read_config_dword(findev, 0x4C, ®4c);
554 reg4c &= ~0x000007FF;
557 pci_write_config_dword(findev, 0x4C, reg4c);
560 outb_p(0x06, 0x0c00);
561 dev->irq = inb_p(0x0c01);
563 /* WE need to figure out how to get the correct one */
564 printk("%s: interrupt %d\n", name, dev->irq);
565 if (dev->irq != 0x0B)
569 printk("%s: device class (0x%04x)\n",
572 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
573 dev->class &= ~0x000F0F00;
574 // dev->class |= ~0x00000400;
575 dev->class |= ~0x00010100;
580 struct pci_dev * findev = NULL;
583 findev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,
584 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
586 pci_read_config_byte(findev, 0x41, ®41);
588 pci_write_config_byte(findev, 0x41, reg41);
591 * This is a device pin issue on CSB6.
592 * Since there will be a future raid mode,
593 * early versions of the chipset require the
594 * interrupt pin to be set, and it is a compatibility
599 // pci_read_config_dword(dev, 0x40, &pioreg)
600 // pci_write_config_dword(dev, 0x40, 0x99999999);
601 // pci_read_config_dword(dev, 0x44, &dmareg);
602 // pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
603 /* setup the UDMA Control register
605 * 1. clear bit 6 to enable DMA
606 * 2. enable DMA modes with bits 0-1
610 * 11 : udma2/udma4/udma5
612 pci_read_config_byte(dev, 0x5A, &btr);
614 if (!(PCI_FUNC(dev->devfn) & 1))
617 btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
618 pci_write_config_byte(dev, 0x5A, btr);
622 #if defined(DISPLAY_SVWKS_TIMINGS) && defined(CONFIG_PROC_FS)
623 svwks_devs[n_svwks_devs++] = dev;
627 ide_pci_register_host_proc(&svwks_procs[0]);
629 #endif /* DISPLAY_SVWKS_TIMINGS && CONFIG_PROC_FS */
631 return (dev->irq) ? dev->irq : 0;
634 static unsigned int __init ata66_svwks_svwks (ide_hwif_t *hwif)
639 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
640 * of the subsystem device ID indicate presence of an 80-pin cable.
641 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
642 * Bit 15 set = secondary IDE channel has 80-pin cable.
643 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
644 * Bit 14 set = primary IDE channel has 80-pin cable.
646 static unsigned int __init ata66_svwks_dell (ide_hwif_t *hwif)
648 struct pci_dev *dev = hwif->pci_dev;
649 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
650 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
651 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
652 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
653 return ((1 << (hwif->channel + 14)) &
654 dev->subsystem_device) ? 1 : 0;
658 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
659 * detect issue by attaching the drives directly to the board.
660 * This check follows the Dell precedent (how scary is that?!)
662 * WARNING: this only works on Alpine hardware!
664 static unsigned int __init ata66_svwks_cobalt (ide_hwif_t *hwif)
666 struct pci_dev *dev = hwif->pci_dev;
667 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
668 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
669 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
670 return ((1 << (hwif->channel + 14)) &
671 dev->subsystem_device) ? 1 : 0;
675 static unsigned int __init ata66_svwks (ide_hwif_t *hwif)
677 struct pci_dev *dev = hwif->pci_dev;
679 /* Per Specified Design by OEM, and ASIC Architect */
680 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
681 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
685 if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
686 return ata66_svwks_svwks (hwif);
689 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
690 return ata66_svwks_dell (hwif);
693 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
694 return ata66_svwks_cobalt (hwif);
700 static void __init init_hwif_svwks (ide_hwif_t *hwif)
705 hwif->irq = hwif->channel ? 15 : 14;
707 hwif->tuneproc = &svwks_tune_drive;
708 hwif->speedproc = &svwks_tune_chipset;
712 if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
713 hwif->ultra_mask = 0x3f;
715 hwif->mwdma_mask = 0x07;
717 hwif->swdma_mask = 0x07;
718 #endif /* CAN_SW_DMA */
722 if (!hwif->dma_base) {
723 hwif->drives[0].autotune = 1;
724 hwif->drives[1].autotune = 1;
728 hwif->ide_dma_check = &svwks_config_drive_xfer_rate;
729 if (hwif->pci_dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
730 hwif->ide_dma_end = &svwks_ide_dma_end;
731 else if (!(hwif->udma_four))
732 hwif->udma_four = ata66_svwks(hwif);
736 dma_stat = hwif->INB(hwif->dma_status);
737 hwif->drives[0].autodma = (dma_stat & 0x20);
738 hwif->drives[1].autodma = (dma_stat & 0x40);
739 hwif->drives[0].autotune = (!(dma_stat & 0x20));
740 hwif->drives[1].autotune = (!(dma_stat & 0x40));
741 // hwif->drives[0].autodma = hwif->autodma;
742 // hwif->drives[1].autodma = hwif->autodma;
746 * We allow the BM-DMA driver to only work on enabled interfaces.
748 static void __init init_dma_svwks (ide_hwif_t *hwif, unsigned long dmabase)
750 struct pci_dev *dev = hwif->pci_dev;
752 if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
753 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
754 (!(PCI_FUNC(dev->devfn) & 1)) && (hwif->channel))
757 ide_setup_dma(hwif, dmabase, 8);
760 extern void ide_setup_pci_device(struct pci_dev *, ide_pci_device_t *);
762 static void __init init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d)
764 ide_setup_pci_device(dev, d);
767 static void __init init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d)
769 if (!(PCI_FUNC(dev->devfn) & 1)) {
770 d->bootable = NEVER_BOARD;
771 if (dev->resource[0].start == 0x01f1)
772 d->bootable = ON_BOARD;
774 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
778 if ((IDE_PCI_DEVID_EQ(d->devid, DEVID_CSB6) &&
779 (!(PCI_FUNC(dev->devfn) & 1)))
780 d->autodma = AUTODMA;
783 d->channels = (((d->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
784 (d->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
785 (!(PCI_FUNC(dev->devfn) & 1))) ? 1 : 2;
787 ide_setup_pci_device(dev, d);
792 * svwks_init_one - called when a OSB/CSB is found
793 * @dev: the svwks device
794 * @id: the matching pci id
796 * Called when the PCI registration layer (or the IDE initialization)
797 * finds a device matching our IDE device tables.
800 static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
802 ide_pci_device_t *d = &serverworks_chipsets[id->driver_data];
804 if (dev->device != d->device)
806 d->init_setup(dev, d);
811 static struct pci_device_id svwks_pci_tbl[] __devinitdata = {
812 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
813 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
814 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
815 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
819 static struct pci_driver driver = {
820 .name = "Serverworks IDE",
821 .id_table = svwks_pci_tbl,
822 .probe = svwks_init_one,
823 #if 0 /* FIXME: implement */
829 static int svwks_ide_init(void)
831 return ide_pci_register_driver(&driver);
834 static void svwks_ide_exit(void)
836 ide_pci_unregister_driver(&driver);
839 module_init(svwks_ide_init);
840 module_exit(svwks_ide_exit);
842 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
843 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
844 MODULE_LICENSE("GPL");