2 * linux/drivers/ide/pci/siimage.c Version 1.06 June 11, 2003
4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2003 Red Hat <alan@redhat.com>
7 * May be copied or modified under the terms of the GNU General Public License
9 * Documentation available under NDA only
13 * If you are using Marvell SATA-IDE adapters with Maxtor drives
14 * ensure the system is set up for ATA100/UDMA5 not UDMA6.
16 * If you are using WD drives with SATA bridges you must set the
17 * drive to "Single". "Master" will hang
19 * If you have strange problems with nVidia chipset systems please
20 * see the SI support documentation and update your system BIOS
24 #include <linux/config.h>
25 #include <linux/types.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/delay.h>
29 #include <linux/hdreg.h>
30 #include <linux/ide.h>
31 #include <linux/init.h>
35 #include "ide_modes.h"
38 #if defined(DISPLAY_SIIMAGE_TIMINGS) && defined(CONFIG_PROC_FS)
39 #include <linux/stat.h>
40 #include <linux/proc_fs.h>
42 static u8 siimage_proc = 0;
43 #define SIIMAGE_MAX_DEVS 16
44 static struct pci_dev *siimage_devs[SIIMAGE_MAX_DEVS];
45 static int n_siimage_devs;
48 * pdev_is_sata - check if device is SATA
49 * @pdev: PCI device to check
51 * Returns true if this is a SATA controller
54 static int pdev_is_sata(struct pci_dev *pdev)
58 case PCI_DEVICE_ID_SII_3112:
59 case PCI_DEVICE_ID_SII_1210SA:
61 case PCI_DEVICE_ID_SII_680:
69 * is_sata - check if hwif is SATA
70 * @hwif: interface to check
72 * Returns true if this is a SATA controller
75 static inline int is_sata(ide_hwif_t *hwif)
77 return pdev_is_sata(hwif->pci_dev);
81 * siimage_selreg - return register base
85 * Turn a config register offset into the right address in either
86 * PCI space or MMIO space to access the control register in question
87 * Thankfully this is a configuration operation so isnt performance
91 static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
93 unsigned long base = (unsigned long)hwif->hwif_data;
96 base += (hwif->channel << 6);
98 base += (hwif->channel << 4);
103 * siimage_seldev - return register base
107 * Turn a config register offset into the right address in either
108 * PCI space or MMIO space to access the control register in question
109 * including accounting for the unit shift.
112 static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
114 ide_hwif_t *hwif = HWIF(drive);
115 unsigned long base = (unsigned long)hwif->hwif_data;
118 base += (hwif->channel << 6);
120 base += (hwif->channel << 4);
121 base |= drive->select.b.unit << drive->select.b.unit;
126 * print_siimage_get_info - print minimal proc information
127 * @buf: buffer to write into (kernel space)
128 * @dev: PCI device we are describing
129 * @index: Controller number
131 * Print the basic information for the state of the CMD680/SI3112
132 * channel. We don't actually dump a lot of information out for
133 * this controller although we could expand it if we needed.
136 static char *print_siimage_get_info (char *buf, struct pci_dev *dev, int index)
139 u8 mmio = (pci_get_drvdata(dev) != NULL) ? 1 : 0;
140 unsigned long bmdma = pci_resource_start(dev, 4);
143 bmdma = pci_resource_start(dev, 5);
145 p += sprintf(p, "\nController: %d\n", index);
146 p += sprintf(p, "SiI%x Chipset.\n", dev->device);
148 p += sprintf(p, "MMIO Base 0x%lx\n", bmdma);
149 p += sprintf(p, "%s-DMA Base 0x%lx\n", (mmio)?"MMIO":"BM", bmdma);
150 p += sprintf(p, "%s-DMA Base 0x%lx\n", (mmio)?"MMIO":"BM", bmdma+8);
155 * siimage_get_info - proc callback
156 * @buffer: kernel buffer to complete
157 * @addr: written with base of data to return
158 * offset: seek offset
159 * count: bytes to fill in
161 * Called when the user reads data from the virtual file for this
162 * controller from /proc
165 static int siimage_get_info (char *buffer, char **addr, off_t offset, int count)
171 p += sprintf(p, "\n");
172 for (i = 0; i < n_siimage_devs; i++) {
173 struct pci_dev *dev = siimage_devs[i];
174 p = print_siimage_get_info(p, dev, i);
176 /* p - buffer must be less than 4k! */
177 len = (p - buffer) - offset;
178 *addr = buffer + offset;
180 return len > count ? count : len;
183 #endif /* defined(DISPLAY_SIIMAGE_TIMINGS) && defined(CONFIG_PROC_FS) */
186 * siimage_ratemask - Compute available modes
189 * Compute the available speeds for the devices on the interface.
190 * For the CMD680 this depends on the clocking mode (scsc), for the
191 * SI3312 SATA controller life is a bit simpler. Enforce UDMA33
192 * as a limit if there is no 80pin cable present.
195 static byte siimage_ratemask (ide_drive_t *drive)
197 ide_hwif_t *hwif = HWIF(drive);
198 u8 mode = 0, scsc = 0;
199 unsigned long base = (unsigned long) hwif->hwif_data;
202 scsc = hwif->INB(base + 0x4A);
204 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
208 if(strstr(drive->id->model, "Maxtor"))
213 if ((scsc & 0x30) == 0x10) /* 133 */
215 else if ((scsc & 0x30) == 0x20) /* 2xPCI */
217 else if ((scsc & 0x30) == 0x00) /* 100 */
219 else /* Disabled ? */
222 if (!eighty_ninty_three(drive))
223 mode = min(mode, (u8)1);
228 * siimage_taskfile_timing - turn timing data to a mode
229 * @hwif: interface to query
231 * Read the timing data for the interface and return the
232 * mode that is being used.
235 static byte siimage_taskfile_timing (ide_hwif_t *hwif)
238 unsigned long addr = siimage_selreg(hwif, 2);
241 timing = hwif->INW(addr);
243 pci_read_config_word(hwif->pci_dev, addr, &timing);
246 case 0x10c1: return 4;
247 case 0x10c3: return 3;
249 case 0x1281: return 2;
250 case 0x2283: return 1;
257 * simmage_tuneproc - tune a drive
258 * @drive: drive to tune
259 * @mode_wanted: the target operating mode
261 * Load the timing settings for this device mode into the
262 * controller. If we are in PIO mode 3 or 4 turn on IORDY
263 * monitoring (bit 9). The TF timing is bits 31:16
266 static void siimage_tuneproc (ide_drive_t *drive, byte mode_wanted)
268 ide_hwif_t *hwif = HWIF(drive);
271 unsigned long addr = siimage_seldev(drive, 0x04);
272 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
274 /* cheat for now and use the docs */
275 switch(mode_wanted) {
300 hwif->OUTW(speedt, addr);
301 hwif->OUTW(speedp, tfaddr);
302 /* Now set up IORDY */
303 if(mode_wanted == 3 || mode_wanted == 4)
304 hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2);
306 hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
310 pci_write_config_word(hwif->pci_dev, addr, speedp);
311 pci_write_config_word(hwif->pci_dev, tfaddr, speedt);
312 pci_read_config_word(hwif->pci_dev, tfaddr-2, &speedp);
314 /* Set IORDY for mode 3 or 4 */
315 if(mode_wanted == 3 || mode_wanted == 4)
317 pci_write_config_word(hwif->pci_dev, tfaddr-2, speedp);
322 * config_siimage_chipset_for_pio - set drive timings
323 * @drive: drive to tune
326 * Compute the best pio mode we can for a given device. Also honour
327 * the timings for the driver when dealing with mixed devices. Some
328 * of this is ugly but its all wrapped up here
330 * The SI680 can also do VDMA - we need to start using that
332 * FIXME: we use the BIOS channel timings to avoid driving the task
333 * files too fast at the disk. We need to compute the master/slave
334 * drive PIO mode properly so that we can up the speed on a hotplug
338 static void config_siimage_chipset_for_pio (ide_drive_t *drive, byte set_speed)
340 u8 channel_timings = siimage_taskfile_timing(HWIF(drive));
341 u8 speed = 0, set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL);
343 /* WARNING PIO timing mess is going to happen b/w devices, argh */
344 if ((channel_timings != set_pio) && (set_pio > channel_timings))
345 set_pio = channel_timings;
347 siimage_tuneproc(drive, set_pio);
348 speed = XFER_PIO_0 + set_pio;
350 (void) ide_config_drive_speed(drive, speed);
353 static void config_chipset_for_pio (ide_drive_t *drive, byte set_speed)
355 config_siimage_chipset_for_pio(drive, set_speed);
359 * siimage_tune_chipset - set controller timings
360 * @drive: Drive to set up
361 * @xferspeed: speed we want to achieve
363 * Tune the SII chipset for the desired mode. If we can't achieve
364 * the desired mode then tune for a lower one, but ultimately
365 * make the thing work.
368 static int siimage_tune_chipset (ide_drive_t *drive, byte xferspeed)
370 u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
371 u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
372 u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
374 ide_hwif_t *hwif = HWIF(drive);
375 u16 ultra = 0, multi = 0;
376 u8 mode = 0, unit = drive->select.b.unit;
377 u8 speed = ide_rate_filter(siimage_ratemask(drive), xferspeed);
378 unsigned long base = (unsigned long)hwif->hwif_data;
379 u8 scsc = 0, addr_mask = ((hwif->channel) ?
380 ((hwif->mmio) ? 0xF4 : 0x84) :
381 ((hwif->mmio) ? 0xB4 : 0x80));
383 unsigned long ma = siimage_seldev(drive, 0x08);
384 unsigned long ua = siimage_seldev(drive, 0x0C);
387 scsc = hwif->INB(base + 0x4A);
388 mode = hwif->INB(base + addr_mask);
389 multi = hwif->INW(ma);
390 ultra = hwif->INW(ua);
392 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
393 pci_read_config_byte(hwif->pci_dev, addr_mask, &mode);
394 pci_read_config_word(hwif->pci_dev, ma, &multi);
395 pci_read_config_word(hwif->pci_dev, ua, &ultra);
398 mode &= ~((unit) ? 0x30 : 0x03);
400 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
402 scsc = is_sata(hwif) ? 1 : scsc;
410 siimage_tuneproc(drive, (speed - XFER_PIO_0));
411 mode |= ((unit) ? 0x10 : 0x01);
416 multi = dma[speed - XFER_MW_DMA_0];
417 mode |= ((unit) ? 0x20 : 0x02);
418 config_siimage_chipset_for_pio(drive, 0);
428 ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) :
429 (ultra5[speed - XFER_UDMA_0]));
430 mode |= ((unit) ? 0x30 : 0x03);
431 config_siimage_chipset_for_pio(drive, 0);
438 hwif->OUTB(mode, base + addr_mask);
439 hwif->OUTW(multi, ma);
440 hwif->OUTW(ultra, ua);
442 pci_write_config_byte(hwif->pci_dev, addr_mask, mode);
443 pci_write_config_word(hwif->pci_dev, ma, multi);
444 pci_write_config_word(hwif->pci_dev, ua, ultra);
446 return (ide_config_drive_speed(drive, speed));
450 * config_chipset_for_dma - configure for DMA
451 * @drive: drive to configure
453 * Called by the IDE layer when it wants the timings set up.
454 * For the CMD680 we also need to set up the PIO timings and
458 static int config_chipset_for_dma (ide_drive_t *drive)
460 u8 speed = ide_dma_speed(drive, siimage_ratemask(drive));
462 config_chipset_for_pio(drive, !speed);
467 if (ide_set_xfer_rate(drive, speed))
470 if (!drive->init_speed)
471 drive->init_speed = speed;
473 return ide_dma_enable(drive);
477 * siimage_configure_drive_for_dma - set up for DMA transfers
478 * @drive: drive we are going to set up
480 * Set up the drive for DMA, tune the controller and drive as
481 * required. If the drive isn't suitable for DMA or we hit
482 * other problems then we will drop down to PIO and set up
486 static int siimage_config_drive_for_dma (ide_drive_t *drive)
488 ide_hwif_t *hwif = HWIF(drive);
489 struct hd_driveid *id = drive->id;
491 if ((id->capability & 1) != 0 && drive->autodma) {
492 /* Consult the list of known "bad" drives */
493 if (hwif->ide_dma_bad_drive(drive))
496 if ((id->field_valid & 4) && siimage_ratemask(drive)) {
497 if (id->dma_ultra & hwif->ultra_mask) {
498 /* Force if Capable UltraDMA */
499 int dma = config_chipset_for_dma(drive);
500 if ((id->field_valid & 2) && !dma)
503 } else if (id->field_valid & 2) {
505 if ((id->dma_mword & hwif->mwdma_mask) ||
506 (id->dma_1word & hwif->swdma_mask)) {
507 /* Force if Capable regular DMA modes */
508 if (!config_chipset_for_dma(drive))
511 } else if (hwif->ide_dma_good_drive(drive) &&
512 (id->eide_dma_time < 150)) {
513 /* Consult the list of known "good" drives */
514 if (!config_chipset_for_dma(drive))
519 return hwif->ide_dma_on(drive);
520 } else if ((id->capability & 8) || (id->field_valid & 2)) {
523 config_chipset_for_pio(drive, 1);
524 return hwif->ide_dma_off_quietly(drive);
526 /* IORDY not supported */
530 /* returns 1 if dma irq issued, 0 otherwise */
531 static int siimage_io_ide_dma_test_irq (ide_drive_t *drive)
533 ide_hwif_t *hwif = HWIF(drive);
535 unsigned long addr = siimage_selreg(hwif, 1);
537 /* return 1 if INTR asserted */
538 if ((hwif->INB(hwif->dma_status) & 4) == 4)
541 /* return 1 if Device INTR asserted */
542 pci_read_config_byte(hwif->pci_dev, addr, &dma_altstat);
544 return 0; //return 1;
549 * siimage_mmio_ide_dma_count - DMA bytes done
552 * If we are doing VDMA the CMD680 requires a little bit
553 * of more careful handling and we have to read the counts
554 * off ourselves. For non VDMA life is normal.
557 static int siimage_mmio_ide_dma_count (ide_drive_t *drive)
559 #ifdef SIIMAGE_VIRTUAL_DMAPIO
560 struct request *rq = HWGROUP(drive)->rq;
561 ide_hwif_t *hwif = HWIF(drive);
562 u32 count = (rq->nr_sectors * SECTOR_SIZE);
564 unsigned long addr = siimage_selreg(hwif, 0x1C);
566 hwif->OUTL(count, addr);
567 rcount = hwif->INL(addr);
569 printk("\n%s: count = %d, rcount = %d, nr_sectors = %lu\n",
570 drive->name, count, rcount, rq->nr_sectors);
572 #endif /* SIIMAGE_VIRTUAL_DMAPIO */
573 return __ide_dma_count(drive);
577 * siimage_mmio_ide_dma_test_irq - check we caused an IRQ
578 * @drive: drive we are testing
580 * Check if we caused an IDE DMA interrupt. We may also have caused
581 * SATA status interrupts, if so we clean them up and continue.
584 static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
586 ide_hwif_t *hwif = HWIF(drive);
587 unsigned long base = (unsigned long)hwif->hwif_data;
588 unsigned long addr = siimage_selreg(hwif, 0x1);
590 if (SATA_ERROR_REG) {
591 u32 ext_stat = hwif->INL(base + 0x10);
593 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
594 u32 sata_error = hwif->INL(SATA_ERROR_REG);
595 hwif->OUTL(sata_error, SATA_ERROR_REG);
596 watchdog = (sata_error & 0x00680000) ? 1 : 0;
598 printk(KERN_WARNING "%s: sata_error = 0x%08x, "
599 "watchdog = %d, %s\n",
600 drive->name, sata_error, watchdog,
605 watchdog = (ext_stat & 0x8000) ? 1 : 0;
609 if (!(ext_stat & 0x0404) && !watchdog)
613 /* return 1 if INTR asserted */
614 if ((hwif->INB(hwif->dma_status) & 0x04) == 0x04)
617 /* return 1 if Device INTR asserted */
618 if ((hwif->INB(addr) & 8) == 8)
619 return 0; //return 1;
624 static int siimage_mmio_ide_dma_verbose (ide_drive_t *drive)
626 int temp = __ide_dma_verbose(drive);
631 * siimage_busproc - bus isolation ioctl
632 * @drive: drive to isolate/restore
633 * @state: bus state to set
635 * Used by the SII3112 to handle bus isolation. As this is a
636 * SATA controller the work required is quite limited, we
637 * just have to clean up the statistics
640 static int siimage_busproc (ide_drive_t * drive, int state)
642 ide_hwif_t *hwif = HWIF(drive);
644 unsigned long addr = siimage_selreg(hwif, 0);
647 stat_config = hwif->INL(addr);
649 pci_read_config_dword(hwif->pci_dev, addr, &stat_config);
653 hwif->drives[0].failures = 0;
654 hwif->drives[1].failures = 0;
657 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
658 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
660 case BUSSTATE_TRISTATE:
661 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
662 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
667 hwif->bus_state = state;
672 * siimage_reset_poll - wait for sata reset
673 * @drive: drive we are resetting
675 * Poll the SATA phy and see whether it has come back from the dead
679 static int siimage_reset_poll (ide_drive_t *drive)
681 if (SATA_STATUS_REG) {
682 ide_hwif_t *hwif = HWIF(drive);
684 if ((hwif->INL(SATA_STATUS_REG) & 0x03) != 0x03) {
685 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
686 hwif->name, hwif->INL(SATA_STATUS_REG));
687 HWGROUP(drive)->poll_timeout = 0;
697 * siimage_pre_reset - reset hook
698 * @drive: IDE device being reset
700 * For the SATA devices we need to handle recalibration/geometry
704 static void siimage_pre_reset (ide_drive_t *drive)
706 if (drive->media != ide_disk)
709 if (is_sata(HWIF(drive)))
711 drive->special.b.set_geometry = 0;
712 drive->special.b.recalibrate = 0;
717 * siimage_reset - reset a device on an siimage controller
718 * @drive: drive to reset
720 * Perform a controller level reset fo the device. For
721 * SATA we must also check the PHY.
724 static void siimage_reset (ide_drive_t *drive)
726 ide_hwif_t *hwif = HWIF(drive);
728 unsigned long addr = siimage_selreg(hwif, 0);
731 reset = hwif->INB(addr);
732 hwif->OUTB((reset|0x03), addr);
735 hwif->OUTB(reset, addr);
736 (void) hwif->INB(addr);
738 pci_read_config_byte(hwif->pci_dev, addr, &reset);
739 pci_write_config_byte(hwif->pci_dev, addr, reset|0x03);
741 pci_write_config_byte(hwif->pci_dev, addr, reset);
742 pci_read_config_byte(hwif->pci_dev, addr, &reset);
745 if (SATA_STATUS_REG) {
746 u32 sata_stat = hwif->INL(SATA_STATUS_REG);
747 printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n",
748 hwif->name, sata_stat, __FUNCTION__);
750 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
751 hwif->name, sata_stat);
759 * proc_reports_siimage - add siimage controller to proc
761 * @clocking: SCSC value
762 * @name: controller name
764 * Report the clocking mode of the controller and add it to
765 * the /proc interface layer
768 static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
770 if(pdev_is_sata(dev))
773 printk(KERN_INFO "%s: BASE CLOCK ", name);
776 case 0x03: printk("DISABLED !\n"); break;
777 case 0x02: printk("== 2X PCI \n"); break;
778 case 0x01: printk("== 133 \n"); break;
779 case 0x00: printk("== 100 \n"); break;
784 #if defined(DISPLAY_SIIMAGE_TIMINGS) && defined(CONFIG_PROC_FS)
785 siimage_devs[n_siimage_devs++] = dev;
789 ide_pci_register_host_proc(&siimage_procs[0]);
791 #endif /* DISPLAY_SIIMAGE_TIMINGS && CONFIG_PROC_FS */
795 * setup_mmio_siimage - switch an SI controller into MMIO
796 * @dev: PCI device we are configuring
799 * Attempt to put the device into mmio mode. There are some slight
800 * complications here with certain systems where the mmio bar isnt
801 * mapped so we have to be sure we can fall back to I/O.
804 static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
806 unsigned long bar5 = pci_resource_start(dev, 5);
807 unsigned long barsize = pci_resource_len(dev, 5);
813 * Drop back to PIO if we can't map the mmio. Some
814 * systems seem to get terminally confused in the PCI
818 if(!request_mem_region(bar5, barsize, name))
820 printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
824 ioaddr = ioremap(bar5, barsize);
828 release_mem_region(bar5, barsize);
833 pci_set_drvdata(dev, ioaddr);
834 addr = (unsigned long) ioaddr;
836 if (pdev_is_sata(dev)) {
837 writel(0, addr + 0x148);
838 writel(0, addr + 0x1C8);
841 writeb(0, addr + 0xB4);
842 writeb(0, addr + 0xF4);
843 tmpbyte = readb(addr + 0x4A);
845 switch(tmpbyte & 0x30) {
847 /* In 100 MHz clocking, try and switch to 133 */
848 writeb(tmpbyte|0x10, addr + 0x4A);
851 /* On 133Mhz clocking */
854 /* On PCIx2 clocking */
857 /* Clocking is disabled */
858 /* 133 clock attempt to force it on */
859 writeb(tmpbyte & ~0x20, addr + 0x4A);
863 writeb( 0x72, addr + 0xA1);
864 writew( 0x328A, addr + 0xA2);
865 writel(0x62DD62DD, addr + 0xA4);
866 writel(0x43924392, addr + 0xA8);
867 writel(0x40094009, addr + 0xAC);
868 writeb( 0x72, addr + 0xE1);
869 writew( 0x328A, addr + 0xE2);
870 writel(0x62DD62DD, addr + 0xE4);
871 writel(0x43924392, addr + 0xE8);
872 writel(0x40094009, addr + 0xEC);
874 if (pdev_is_sata(dev)) {
875 writel(0xFFFF0000, addr + 0x108);
876 writel(0xFFFF0000, addr + 0x188);
877 writel(0x00680000, addr + 0x148);
878 writel(0x00680000, addr + 0x1C8);
881 tmpbyte = readb(addr + 0x4A);
883 proc_reports_siimage(dev, (tmpbyte>>4), name);
888 * init_chipset_siimage - set up an SI device
892 * Perform the initial PCI set up for this device. Attempt to switch
893 * to 133MHz clocking if the system isn't already set up to do it.
896 static unsigned int __init init_chipset_siimage (struct pci_dev *dev, const char *name)
902 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
904 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
906 pci_read_config_byte(dev, 0x8A, &BA5_EN);
907 if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
908 if (setup_mmio_siimage(dev, name)) {
913 pci_write_config_byte(dev, 0x80, 0x00);
914 pci_write_config_byte(dev, 0x84, 0x00);
915 pci_read_config_byte(dev, 0x8A, &tmpbyte);
916 switch(tmpbyte & 0x30) {
918 /* 133 clock attempt to force it on */
919 pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
921 /* if clocking is disabled */
922 /* 133 clock attempt to force it on */
923 pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
928 /* BIOS set PCI x2 clocking */
932 pci_read_config_byte(dev, 0x8A, &tmpbyte);
934 pci_write_config_byte(dev, 0xA1, 0x72);
935 pci_write_config_word(dev, 0xA2, 0x328A);
936 pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
937 pci_write_config_dword(dev, 0xA8, 0x43924392);
938 pci_write_config_dword(dev, 0xAC, 0x40094009);
939 pci_write_config_byte(dev, 0xB1, 0x72);
940 pci_write_config_word(dev, 0xB2, 0x328A);
941 pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
942 pci_write_config_dword(dev, 0xB8, 0x43924392);
943 pci_write_config_dword(dev, 0xBC, 0x40094009);
945 proc_reports_siimage(dev, (tmpbyte>>4), name);
950 * init_mmio_iops_siimage - set up the iops for MMIO
951 * @hwif: interface to set up
953 * The basic setup here is fairly simple, we can use standard MMIO
954 * operations. However we do have to set the taskfile register offsets
955 * by hand as there isnt a standard defined layout for them this
958 * The hardware supports buffered taskfiles and also some rather nice
959 * extended PRD tables. Unfortunately right now we don't.
962 static void __init init_mmio_iops_siimage (ide_hwif_t *hwif)
964 struct pci_dev *dev = hwif->pci_dev;
965 void *addr = pci_get_drvdata(dev);
966 u8 ch = hwif->channel;
971 * Fill in the basic HWIF bits
974 default_hwif_mmiops(hwif);
975 hwif->hwif_data = addr;
978 * Now set up the hw. We have to do this ourselves as
979 * the MMIO layout isnt the same as the the standard port
983 memset(&hw, 0, sizeof(hw_regs_t));
986 base = (unsigned long)addr;
993 * The buffered task file doesn't have status/control
994 * so we can't currently use it sanely since we want to
998 // hwif->addressing = 1;
1000 hw.io_ports[IDE_DATA_OFFSET] = base;
1001 hw.io_ports[IDE_ERROR_OFFSET] = base + 1;
1002 hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
1003 hw.io_ports[IDE_SECTOR_OFFSET] = base + 3;
1004 hw.io_ports[IDE_LCYL_OFFSET] = base + 4;
1005 hw.io_ports[IDE_HCYL_OFFSET] = base + 5;
1006 hw.io_ports[IDE_SELECT_OFFSET] = base + 6;
1007 hw.io_ports[IDE_STATUS_OFFSET] = base + 7;
1008 hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
1010 hw.io_ports[IDE_IRQ_OFFSET] = 0;
1012 if (pdev_is_sata(dev)) {
1013 base = (unsigned long) addr;
1016 hw.sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
1017 hw.sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
1018 hw.sata_scr[SATA_CONTROL_OFFSET]= base + 0x100;
1019 hw.sata_misc[SATA_MISC_OFFSET] = base + 0x140;
1020 hw.sata_misc[SATA_PHY_OFFSET] = base + 0x144;
1021 hw.sata_misc[SATA_IEN_OFFSET] = base + 0x148;
1024 hw.irq = hwif->pci_dev->irq;
1026 memcpy(&hwif->hw, &hw, sizeof(hw));
1027 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports));
1029 if (is_sata(hwif)) {
1030 memcpy(hwif->sata_scr, hwif->hw.sata_scr, sizeof(hwif->hw.sata_scr));
1031 memcpy(hwif->sata_misc, hwif->hw.sata_misc, sizeof(hwif->hw.sata_misc));
1036 base = (unsigned long) addr;
1038 #ifdef SIIMAGE_LARGE_DMA
1039 /* Watch the brackets - even Ken and Dennis get some language design wrong */
1040 hwif->dma_base = base + (ch ? 0x18 : 0x10);
1041 hwif->dma_base2 = base + (ch ? 0x08 : 0x00);
1042 hwif->dma_prdtable = hwif->dma_base2 + 4;
1043 #else /* ! SIIMAGE_LARGE_DMA */
1044 hwif->dma_base = base + (ch ? 0x08 : 0x00);
1045 hwif->dma_base2 = base + (ch ? 0x18 : 0x10);
1046 #endif /* SIIMAGE_LARGE_DMA */
1051 * init_iops_siimage - set up iops
1052 * @hwif: interface to set up
1054 * Do the basic setup for the SIIMAGE hardware interface
1055 * and then do the MMIO setup if we can. This is the first
1056 * look in we get for setting up the hwif so that we
1057 * can get the iops right before using them.
1060 static void __init init_iops_siimage (ide_hwif_t *hwif)
1062 struct pci_dev *dev = hwif->pci_dev;
1065 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1068 hwif->hwif_data = 0;
1074 if (pci_get_drvdata(dev) == NULL)
1076 init_mmio_iops_siimage(hwif);
1080 * ata66_siimage - check for 80 pin cable
1081 * @hwif: interface to check
1083 * Check for the presence of an ATA66 capable cable on the
1087 static unsigned int __init ata66_siimage (ide_hwif_t *hwif)
1089 unsigned long addr = siimage_selreg(hwif, 0);
1090 if (pci_get_drvdata(hwif->pci_dev) == NULL) {
1092 pci_read_config_byte(hwif->pci_dev, addr, &ata66);
1093 return (ata66 & 0x01) ? 1 : 0;
1096 return (hwif->INB(addr) & 0x01) ? 1 : 0;
1100 * init_hwif_siimage - set up hwif structs
1101 * @hwif: interface to set up
1103 * We do the basic set up of the interface structure. The SIIMAGE
1104 * requires several custom handlers so we override the default
1105 * ide DMA handlers appropriately
1108 static void __init init_hwif_siimage (ide_hwif_t *hwif)
1112 hwif->resetproc = &siimage_reset;
1113 hwif->speedproc = &siimage_tune_chipset;
1114 hwif->tuneproc = &siimage_tuneproc;
1115 hwif->reset_poll = &siimage_reset_poll;
1116 hwif->pre_reset = &siimage_pre_reset;
1120 hwif->busproc = &siimage_busproc;
1124 if (!hwif->dma_base) {
1125 hwif->drives[0].autotune = 1;
1126 hwif->drives[1].autotune = 1;
1130 hwif->ultra_mask = 0x7f;
1131 hwif->mwdma_mask = 0x07;
1132 hwif->swdma_mask = 0x07;
1135 hwif->atapi_dma = 1;
1137 hwif->ide_dma_check = &siimage_config_drive_for_dma;
1138 if (!(hwif->udma_four))
1139 hwif->udma_four = ata66_siimage(hwif);
1142 hwif->ide_dma_count = &siimage_mmio_ide_dma_count;
1143 hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq;
1144 hwif->ide_dma_verbose = &siimage_mmio_ide_dma_verbose;
1146 hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq;
1150 * The BIOS often doesn't set up DMA on this controller
1151 * so we always do it.
1155 hwif->drives[0].autodma = hwif->autodma;
1156 hwif->drives[1].autodma = hwif->autodma;
1160 * init_dma_siimage - set up IDE DMA
1162 * @dmabase: DMA base address to use
1164 * For the SI chips this requires no special set up so we can just
1165 * let the IDE DMA core do the usual work.
1168 static void __init init_dma_siimage (ide_hwif_t *hwif, unsigned long dmabase)
1170 ide_setup_dma(hwif, dmabase, 8);
1173 extern void ide_setup_pci_device(struct pci_dev *, ide_pci_device_t *);
1177 * siimage_init_one - pci layer discovery entry
1179 * @id: ident table entry
1181 * Called by the PCI code when it finds an SI680 or SI3112 controller.
1182 * We then use the IDE PCI generic helper to do most of the work.
1185 static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1187 ide_pci_device_t *d = &siimage_chipsets[id->driver_data];
1188 if (dev->device != d->device)
1190 ide_setup_pci_device(dev, d);
1195 static struct pci_device_id siimage_pci_tbl[] __devinitdata = {
1196 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1197 #ifdef CONFIG_BLK_DEV_IDE_SATA
1198 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1199 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_1210SA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1204 static struct pci_driver driver = {
1206 .id_table = siimage_pci_tbl,
1207 .probe = siimage_init_one,
1210 static int siimage_ide_init(void)
1212 return ide_pci_register_driver(&driver);
1215 static void siimage_ide_exit(void)
1217 ide_pci_unregister_driver(&driver);
1220 module_init(siimage_ide_init);
1221 module_exit(siimage_ide_exit);
1223 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
1224 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
1225 MODULE_LICENSE("GPL");