drivers/isdn/hisax/bkm_a8.c

   1 /* $Id: bkm_a8.c,v 1.1.1.1 2005/04/11 02:50:23 jack Exp $
   2  *
   3  * low level stuff for Scitel Quadro (4*S0, passive)
   4  *
   5  * Author       Roland Klabunde
   6  * Copyright    by Roland Klabunde   <R.Klabunde@Berkom.de>
   7  *
   8  * This software may be used and distributed according to the terms
   9  * of the GNU General Public License, incorporated herein by reference.
  10  *
  11  */
  12
  13 #define __NO_VERSION__
  14
  15 #include <linux/config.h>
  16 #include <linux/init.h>
  17 #include "hisax.h"
  18 #include "isac.h"
  19 #include "ipac.h"
  20 #include "hscx.h"
  21 #include "isdnl1.h"
  22 #include <linux/pci.h>
  23 #include "bkm_ax.h"
  24
  25 #if CONFIG_PCI
  26
  27 #define ATTEMPT_PCI_REMAPPING   /* Required for PLX rev 1 */
  28
  29 extern const char *CardType[];
  30
  31 const char sct_quadro_revision[] = "$Revision: 1.1.1.1 $";
  32
  33 static const char *sct_quadro_subtypes[] =
  34 {
  35         "",
  36         "#1",
  37         "#2",
  38         "#3",
  39         "#4"
  40 };
  41
  42
  43 #define wordout(addr,val) outw(val,addr)
  44 #define wordin(addr) inw(addr)
  45
  46 static inline u_char
  47 readreg(unsigned int ale, unsigned int adr, u_char off)
  48 {
  49         register u_char ret;
  50         long flags;
  51         save_flags(flags);
  52         cli();
  53         wordout(ale, off);
  54         ret = wordin(adr) & 0xFF;
  55         restore_flags(flags);
  56         return (ret);
  57 }
  58
  59 static inline void
  60 readfifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
  61 {
  62         /* fifo read without cli because it's allready done  */
  63         int i;
  64         wordout(ale, off);
  65         for (i = 0; i < size; i++)
  66                 data[i] = wordin(adr) & 0xFF;
  67 }
  68
  69
  70 static inline void
  71 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data)
  72 {
  73         long flags;
  74         save_flags(flags);
  75         cli();
  76         wordout(ale, off);
  77         wordout(adr, data);
  78         restore_flags(flags);
  79 }
  80
  81 static inline void
  82 writefifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
  83 {
  84         /* fifo write without cli because it's allready done  */
  85         int i;
  86         wordout(ale, off);
  87         for (i = 0; i < size; i++)
  88                 wordout(adr, data[i]);
  89 }
  90
  91 /* Interface functions */
  92
  93 static u_char
  94 ReadISAC(struct IsdnCardState *cs, u_char offset)
  95 {
  96         return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80));
  97 }
  98
  99 static void
 100 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
 101 {
 102         writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value);
 103 }
 104
 105 static void
 106 ReadISACfifo(struct IsdnCardState *cs, u_char * data, int size)
 107 {
 108         readfifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);
 109 }
 110
 111 static void
 112 WriteISACfifo(struct IsdnCardState *cs, u_char * data, int size)
 113 {
 114         writefifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);
 115 }
 116
 117
 118 static u_char
 119 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
 120 {
 121         return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0)));
 122 }
 123
 124 static void
 125 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
 126 {
 127         writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value);
 128 }
 129
 130 /* Set the specific ipac to active */
 131 static void
 132 set_ipac_active(struct IsdnCardState *cs, u_int active)
 133 {
 134         /* set irq mask */
 135         writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK,
 136                 active ? 0xc0 : 0xff);
 137 }
 138
 139 /*
 140  * fast interrupt HSCX stuff goes here
 141  */
 142
 143 #define READHSCX(cs, nr, reg) readreg(cs->hw.ax.base, \
 144         cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0))
 145 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ax.base, \
 146         cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0), data)
 147 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.ax.base, \
 148         cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
 149 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.ax.base, \
 150         cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
 151
 152 #include "hscx_irq.c"
 153
 154 static void
 155 bkm_interrupt_ipac(int intno, void *dev_id, struct pt_regs *regs)
 156 {
 157         struct IsdnCardState *cs = dev_id;
 158         u_char ista, val, icnt = 5;
 159
 160         if (!cs) {
 161                 printk(KERN_WARNING "HiSax: Scitel Quadro: Spurious interrupt!\n");
 162                 return;
 163         }
 164         ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);
 165         if (!(ista & 0x3f)) /* not this IPAC */
 166                 return;
 167       Start_IPAC:
 168         if (cs->debug & L1_DEB_IPAC)
 169                 debugl1(cs, "IPAC ISTA %02X", ista);
 170         if (ista & 0x0f) {
 171                 val = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, HSCX_ISTA + 0x40);
 172                 if (ista & 0x01)
 173                         val |= 0x01;
 174                 if (ista & 0x04)
 175                         val |= 0x02;
 176                 if (ista & 0x08)
 177                         val |= 0x04;
 178                 if (val) {
 179                         hscx_int_main(cs, val);
 180                 }
 181         }
 182         if (ista & 0x20) {
 183                 val = 0xfe & readreg(cs->hw.ax.base, cs->hw.ax.data_adr, ISAC_ISTA | 0x80);
 184                 if (val) {
 185                         isac_interrupt(cs, val);
 186                 }
 187         }
 188         if (ista & 0x10) {
 189                 val = 0x01;
 190                 isac_interrupt(cs, val);
 191         }
 192         ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);
 193         if ((ista & 0x3f) && icnt) {
 194                 icnt--;
 195                 goto Start_IPAC;
 196         }
 197         if (!icnt)
 198                 printk(KERN_WARNING "HiSax: %s (%s) IRQ LOOP\n",
 199                        CardType[cs->typ],
 200                        sct_quadro_subtypes[cs->subtyp]);
 201         writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF);
 202         writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0);
 203 }
 204
 205
 206 void
 207 release_io_sct_quadro(struct IsdnCardState *cs)
 208 {
 209         release_region(cs->hw.ax.base & 0xffffffc0, 128);
 210         if (cs->subtyp == SCT_1)
 211                 release_region(cs->hw.ax.plx_adr, 64);
 212 }
 213
 214 static void
 215 enable_bkm_int(struct IsdnCardState *cs, unsigned bEnable)
 216 {
 217         if (cs->typ == ISDN_CTYPE_SCT_QUADRO) {
 218                 if (bEnable)
 219                         wordout(cs->hw.ax.plx_adr + 0x4C, (wordin(cs->hw.ax.plx_adr + 0x4C) | 0x41));
 220                 else
 221                         wordout(cs->hw.ax.plx_adr + 0x4C, (wordin(cs->hw.ax.plx_adr + 0x4C) & ~0x41));
 222         }
 223 }
 224
 225 static void
 226 reset_bkm(struct IsdnCardState *cs)
 227 {
 228         long flags;
 229
 230         if (cs->subtyp == SCT_1) {
 231                 wordout(cs->hw.ax.plx_adr + 0x50, (wordin(cs->hw.ax.plx_adr + 0x50) & ~4));
 232                 save_flags(flags);
 233                 sti();
 234                 set_current_state(TASK_UNINTERRUPTIBLE);
 235                 schedule_timeout((10 * HZ) / 1000);
 236                 /* Remove the soft reset */
 237                 wordout(cs->hw.ax.plx_adr + 0x50, (wordin(cs->hw.ax.plx_adr + 0x50) | 4));
 238                 set_current_state(TASK_UNINTERRUPTIBLE);
 239                 schedule_timeout((10 * HZ) / 1000);
 240                 restore_flags(flags);
 241         }
 242 }
 243
 244 static int
 245 BKM_card_msg(struct IsdnCardState *cs, int mt, void *arg)
 246 {
 247         switch (mt) {
 248                 case CARD_RESET:
 249                         /* Disable ints */
 250                         set_ipac_active(cs, 0);
 251                         enable_bkm_int(cs, 0);
 252                         reset_bkm(cs);
 253                         return (0);
 254                 case CARD_RELEASE:
 255                         /* Sanity */
 256                         set_ipac_active(cs, 0);
 257                         enable_bkm_int(cs, 0);
 258                         release_io_sct_quadro(cs);
 259                         return (0);
 260                 case CARD_INIT:
 261                         cs->debug |= L1_DEB_IPAC;
 262                         set_ipac_active(cs, 1);
 263                         inithscxisac(cs, 3);
 264                         /* Enable ints */
 265                         enable_bkm_int(cs, 1);
 266                         return (0);
 267                 case CARD_TEST:
 268                         return (0);
 269         }
 270         return (0);
 271 }
 272
 273 int __init
 274 sct_alloc_io(u_int adr, u_int len)
 275 {
 276         if (check_region(adr, len)) {
 277                 printk(KERN_WARNING
 278                         "HiSax: Scitel port %#x-%#x already in use\n",
 279                         adr, adr + len);
 280                 return (1);
 281         } else {
 282                 request_region(adr, len, "scitel");
 283         }
 284         return(0);
 285 }
 286
 287 static struct pci_dev *dev_a8 __initdata = NULL;
 288 static u16  sub_vendor_id __initdata = 0;
 289 static u16  sub_sys_id __initdata = 0;
 290 static u_char pci_bus __initdata = 0;
 291 static u_char pci_device_fn __initdata = 0;
 292 static u_char pci_irq __initdata = 0;
 293
 294 #endif /* CONFIG_PCI */
 295
 296 int __init
 297 setup_sct_quadro(struct IsdnCard *card)
 298 {
 299 #if CONFIG_PCI
 300         struct IsdnCardState *cs = card->cs;
 301         char tmp[64];
 302         u_char pci_rev_id;
 303         u_int found = 0;
 304         u_int pci_ioaddr1, pci_ioaddr2, pci_ioaddr3, pci_ioaddr4, pci_ioaddr5;
 305
 306         strcpy(tmp, sct_quadro_revision);
 307         printk(KERN_INFO "HiSax: T-Berkom driver Rev. %s\n", HiSax_getrev(tmp));
 308         if (cs->typ == ISDN_CTYPE_SCT_QUADRO) {
 309                 cs->subtyp = SCT_1;     /* Preset */
 310         } else
 311                 return (0);
 312
 313         /* Identify subtype by para[0] */
 314         if (card->para[0] >= SCT_1 && card->para[0] <= SCT_4)
 315                 cs->subtyp = card->para[0];
 316         else {
 317                 printk(KERN_WARNING "HiSax: %s: Invalid subcontroller in configuration, default to 1\n",
 318                         CardType[card->typ]);
 319                 return (0);
 320         }
 321         if ((cs->subtyp != SCT_1) && ((sub_sys_id != PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO) ||
 322                 (sub_vendor_id != PCI_VENDOR_ID_BERKOM)))
 323                 return (0);
 324         if (cs->subtyp == SCT_1) {
 325                 if (!pci_present()) {
 326                         printk(KERN_ERR "bkm_a4t: no PCI bus present\n");
 327                         return (0);
 328                 }
 329                 while ((dev_a8 = pci_find_device(PCI_VENDOR_ID_PLX,
 330                         PCI_DEVICE_ID_PLX_9050, dev_a8))) {
 331
 332                         sub_vendor_id = dev_a8->subsystem_vendor;
 333                         sub_sys_id = dev_a8->subsystem_device;
 334                         if ((sub_sys_id == PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO) &&
 335                                 (sub_vendor_id == PCI_VENDOR_ID_BERKOM)) {
 336                                 if (pci_enable_device(dev_a8))
 337                                         return(0);
 338                                 pci_ioaddr1 = pci_resource_start(dev_a8, 1);
 339                                 pci_irq = dev_a8->irq;
 340                                 pci_bus = dev_a8->bus->number;
 341                                 pci_device_fn = dev_a8->devfn;
 342                                 found = 1;
 343                                 break;
 344                         }
 345                 }
 346                 if (!found) {
 347                         printk(KERN_WARNING "HiSax: %s (%s): Card not found\n",
 348                                 CardType[card->typ],
 349                                 sct_quadro_subtypes[cs->subtyp]);
 350                         return (0);
 351                 }
 352 #ifdef ATTEMPT_PCI_REMAPPING
 353 /* HACK: PLX revision 1 bug: PLX address bit 7 must not be set */
 354                 pcibios_read_config_byte(pci_bus, pci_device_fn,
 355                         PCI_REVISION_ID, &pci_rev_id);
 356                 if ((pci_ioaddr1 & 0x80) && (pci_rev_id == 1)) {
 357                         printk(KERN_WARNING "HiSax: %s (%s): PLX rev 1, remapping required!\n",
 358                                 CardType[card->typ],
 359                                 sct_quadro_subtypes[cs->subtyp]);
 360                         /* Restart PCI negotiation */
 361                         pcibios_write_config_dword(pci_bus, pci_device_fn,
 362                                 PCI_BASE_ADDRESS_1, (u_int) - 1);
 363                         /* Move up by 0x80 byte */
 364                         pci_ioaddr1 += 0x80;
 365                         pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
 366                         pcibios_write_config_dword(pci_bus, pci_device_fn,
 367                                 PCI_BASE_ADDRESS_1, pci_ioaddr1);
 368                         dev_a8->resource[ 1].start = pci_ioaddr1;
 369                 }
 370 #endif /* End HACK */
 371         }
 372         if (!pci_irq) {         /* IRQ range check ?? */
 373                 printk(KERN_WARNING "HiSax: %s (%s): No IRQ\n",
 374                        CardType[card->typ],
 375                        sct_quadro_subtypes[cs->subtyp]);
 376                 return (0);
 377         }
 378         pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_1, &pci_ioaddr1);
 379         pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_2, &pci_ioaddr2);
 380         pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_3, &pci_ioaddr3);
 381         pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_4, &pci_ioaddr4);
 382         pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_5, &pci_ioaddr5);
 383         if (!pci_ioaddr1 || !pci_ioaddr2 || !pci_ioaddr3 || !pci_ioaddr4 || !pci_ioaddr5) {
 384                 printk(KERN_WARNING "HiSax: %s (%s): No IO base address(es)\n",
 385                        CardType[card->typ],
 386                        sct_quadro_subtypes[cs->subtyp]);
 387                 return (0);
 388         }
 389         pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
 390         pci_ioaddr2 &= PCI_BASE_ADDRESS_IO_MASK;
 391         pci_ioaddr3 &= PCI_BASE_ADDRESS_IO_MASK;
 392         pci_ioaddr4 &= PCI_BASE_ADDRESS_IO_MASK;
 393         pci_ioaddr5 &= PCI_BASE_ADDRESS_IO_MASK;
 394         /* Take over */
 395         cs->irq = pci_irq;
 396         cs->irq_flags |= SA_SHIRQ;
 397         /* pci_ioaddr1 is unique to all subdevices */
 398         /* pci_ioaddr2 is for the fourth subdevice only */
 399         /* pci_ioaddr3 is for the third subdevice only */
 400         /* pci_ioaddr4 is for the second subdevice only */
 401         /* pci_ioaddr5 is for the first subdevice only */
 402         cs->hw.ax.plx_adr = pci_ioaddr1;
 403         /* Enter all ipac_base addresses */
 404         switch(cs->subtyp) {
 405                 case 1:
 406                         cs->hw.ax.base = pci_ioaddr5 + 0x00;
 407                         if (sct_alloc_io(pci_ioaddr1, 128))
 408                                 return(0);
 409                         if (sct_alloc_io(pci_ioaddr5, 64))
 410                                 return(0);
 411                         /* disable all IPAC */
 412                         writereg(pci_ioaddr5, pci_ioaddr5 + 4,
 413                                 IPAC_MASK, 0xFF);
 414                         writereg(pci_ioaddr4 + 0x08, pci_ioaddr4 + 0x0c,
 415                                 IPAC_MASK, 0xFF);
 416                         writereg(pci_ioaddr3 + 0x10, pci_ioaddr3 + 0x14,
 417                                 IPAC_MASK, 0xFF);
 418                         writereg(pci_ioaddr2 + 0x20, pci_ioaddr2 + 0x24,
 419                                 IPAC_MASK, 0xFF);
 420                         break;
 421                 case 2:
 422                         cs->hw.ax.base = pci_ioaddr4 + 0x08;
 423                         if (sct_alloc_io(pci_ioaddr4, 64))
 424                                 return(0);
 425                         break;
 426                 case 3:
 427                         cs->hw.ax.base = pci_ioaddr3 + 0x10;
 428                         if (sct_alloc_io(pci_ioaddr3, 64))
 429                                 return(0);
 430                         break;
 431                 case 4:
 432                         cs->hw.ax.base = pci_ioaddr2 + 0x20;
 433                         if (sct_alloc_io(pci_ioaddr2, 64))
 434                                 return(0);
 435                         break;
 436         }
 437         /* For isac and hscx data path */
 438         cs->hw.ax.data_adr = cs->hw.ax.base + 4;
 439
 440         printk(KERN_INFO "HiSax: %s (%s) configured at 0x%.4lX, 0x%.4lX, 0x%.4lX and IRQ %d\n",
 441                CardType[card->typ],
 442                sct_quadro_subtypes[cs->subtyp],
 443                cs->hw.ax.plx_adr,
 444                cs->hw.ax.base,
 445                cs->hw.ax.data_adr,
 446                cs->irq);
 447
 448         test_and_set_bit(HW_IPAC, &cs->HW_Flags);
 449
 450         cs->readisac = &ReadISAC;
 451         cs->writeisac = &WriteISAC;
 452         cs->readisacfifo = &ReadISACfifo;
 453         cs->writeisacfifo = &WriteISACfifo;
 454
 455         cs->BC_Read_Reg = &ReadHSCX;
 456         cs->BC_Write_Reg = &WriteHSCX;
 457         cs->BC_Send_Data = &hscx_fill_fifo;
 458         cs->cardmsg = &BKM_card_msg;
 459         cs->irq_func = &bkm_interrupt_ipac;
 460
 461         printk(KERN_INFO "HiSax: %s (%s): IPAC Version %d\n",
 462                 CardType[card->typ],
 463                 sct_quadro_subtypes[cs->subtyp],
 464                 readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID));
 465         return (1);
 466 #else
 467         printk(KERN_ERR "HiSax: bkm_a8 only supported on PCI Systems\n");
 468 #endif /* CONFIG_PCI */
 469 }