drivers/isdn/hisax/diva.c

   1 /* $Id: diva.c,v 1.1.4.2 2002/08/30 11:21:00 keil Exp $
   2  *
   3  * low level stuff for Eicon.Diehl Diva Family ISDN cards
   4  *
   5  * Author       Karsten Keil
   6  * Copyright    by Karsten Keil      <keil@isdn4linux.de>
   7  *
   8  * This software may be used and distributed according to the terms
   9  * of the GNU General Public License, incorporated herein by reference.
  10  *
  11  * For changes and modifications please read
  12  * ../../../Documentation/isdn/HiSax.cert
  13  *
  14  * Thanks to Eicon Technology for documents and information
  15  *
  16  */
  17
  18 #define __NO_VERSION__
  19 #include <linux/init.h>
  20 #include <linux/config.h>
  21 #include "hisax.h"
  22 #include "isac.h"
  23 #include "hscx.h"
  24 #include "ipac.h"
  25 #include "ipacx.h"
  26 #include "isdnl1.h"
  27 #include <linux/pci.h>
  28 #include <linux/isapnp.h>
  29
  30 extern const char *CardType[];
  31
  32 const char *Diva_revision = "$Revision: 1.1.4.2 $";
  33
  34 #define byteout(addr,val) outb(val,addr)
  35 #define bytein(addr) inb(addr)
  36
  37 #define DIVA_HSCX_DATA          0
  38 #define DIVA_HSCX_ADR           4
  39 #define DIVA_ISA_ISAC_DATA      2
  40 #define DIVA_ISA_ISAC_ADR       6
  41 #define DIVA_ISA_CTRL           7
  42 #define DIVA_IPAC_ADR           0
  43 #define DIVA_IPAC_DATA          1
  44
  45 #define DIVA_PCI_ISAC_DATA      8
  46 #define DIVA_PCI_ISAC_ADR       0xc
  47 #define DIVA_PCI_CTRL           0x10
  48
  49 /* SUB Types */
  50 #define DIVA_ISA        1
  51 #define DIVA_PCI        2
  52 #define DIVA_IPAC_ISA   3
  53 #define DIVA_IPAC_PCI   4
  54 #define DIVA_IPACX_PCI  5
  55
  56 /* CTRL (Read) */
  57 #define DIVA_IRQ_STAT   0x01
  58 #define DIVA_EEPROM_SDA 0x02
  59
  60 /* CTRL (Write) */
  61 #define DIVA_IRQ_REQ    0x01
  62 #define DIVA_RESET      0x08
  63 #define DIVA_EEPROM_CLK 0x40
  64 #define DIVA_PCI_LED_A  0x10
  65 #define DIVA_PCI_LED_B  0x20
  66 #define DIVA_ISA_LED_A  0x20
  67 #define DIVA_ISA_LED_B  0x40
  68 #define DIVA_IRQ_CLR    0x80
  69
  70 /* Siemens PITA */
  71 #define PITA_MISC_REG           0x1c
  72 #ifdef __BIG_ENDIAN
  73 #define PITA_PARA_SOFTRESET     0x00000001
  74 #define PITA_SER_SOFTRESET      0x00000002
  75 #define PITA_PARA_MPX_MODE      0x00000004
  76 #define PITA_INT0_ENABLE        0x00000200
  77 #else
  78 #define PITA_PARA_SOFTRESET     0x01000000
  79 #define PITA_SER_SOFTRESET      0x02000000
  80 #define PITA_PARA_MPX_MODE      0x04000000
  81 #define PITA_INT0_ENABLE        0x00020000
  82 #endif
  83 #define PITA_INT0_STATUS        0x02
  84
  85 static inline u_char
  86 readreg(unsigned int ale, unsigned int adr, u_char off)
  87 {
  88         register u_char ret;
  89         long flags;
  90
  91         save_flags(flags);
  92         cli();
  93         byteout(ale, off);
  94         ret = bytein(adr);
  95         restore_flags(flags);
  96         return (ret);
  97 }
  98
  99 static inline void
 100 readfifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
 101 {
 102         /* fifo read without cli because it's allready done  */
 103
 104         byteout(ale, off);
 105         insb(adr, data, size);
 106 }
 107
 108
 109 static inline void
 110 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data)
 111 {
 112         long flags;
 113
 114         save_flags(flags);
 115         cli();
 116         byteout(ale, off);
 117         byteout(adr, data);
 118         restore_flags(flags);
 119 }
 120
 121 static inline void
 122 writefifo(unsigned int ale, unsigned int adr, u_char off, u_char *data, int size)
 123 {
 124         /* fifo write without cli because it's allready done  */
 125         byteout(ale, off);
 126         outsb(adr, data, size);
 127 }
 128
 129 static inline u_char
 130 memreadreg(unsigned long adr, u_char off)
 131 {
 132         return(*((unsigned char *)
 133                 (((unsigned int *)adr) + off)));
 134 }
 135
 136 static inline void
 137 memwritereg(unsigned long adr, u_char off, u_char data)
 138 {
 139         register u_char *p;
 140
 141         p = (unsigned char *)(((unsigned int *)adr) + off);
 142         *p = data;
 143 }
 144
 145 /* Interface functions */
 146
 147 static u_char
 148 ReadISAC(struct IsdnCardState *cs, u_char offset)
 149 {
 150         return(readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset));
 151 }
 152
 153 static void
 154 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
 155 {
 156         writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset, value);
 157 }
 158
 159 static void
 160 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size)
 161 {
 162         readfifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0, data, size);
 163 }
 164
 165 static void
 166 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size)
 167 {
 168         writefifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0, data, size);
 169 }
 170
 171 static u_char
 172 ReadISAC_IPAC(struct IsdnCardState *cs, u_char offset)
 173 {
 174         return (readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset+0x80));
 175 }
 176
 177 static void
 178 WriteISAC_IPAC(struct IsdnCardState *cs, u_char offset, u_char value)
 179 {
 180         writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset|0x80, value);
 181 }
 182
 183 static void
 184 ReadISACfifo_IPAC(struct IsdnCardState *cs, u_char * data, int size)
 185 {
 186         readfifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0x80, data, size);
 187 }
 188
 189 static void
 190 WriteISACfifo_IPAC(struct IsdnCardState *cs, u_char * data, int size)
 191 {
 192         writefifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0x80, data, size);
 193 }
 194
 195 static u_char
 196 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
 197 {
 198         return(readreg(cs->hw.diva.hscx_adr,
 199                 cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0)));
 200 }
 201
 202 static void
 203 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
 204 {
 205         writereg(cs->hw.diva.hscx_adr,
 206                 cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0), value);
 207 }
 208
 209 static u_char
 210 MemReadISAC_IPAC(struct IsdnCardState *cs, u_char offset)
 211 {
 212         return (memreadreg(cs->hw.diva.cfg_reg, offset+0x80));
 213 }
 214
 215 static void
 216 MemWriteISAC_IPAC(struct IsdnCardState *cs, u_char offset, u_char value)
 217 {
 218         memwritereg(cs->hw.diva.cfg_reg, offset|0x80, value);
 219 }
 220
 221 static void
 222 MemReadISACfifo_IPAC(struct IsdnCardState *cs, u_char * data, int size)
 223 {
 224         while(size--)
 225                 *data++ = memreadreg(cs->hw.diva.cfg_reg, 0x80);
 226 }
 227
 228 static void
 229 MemWriteISACfifo_IPAC(struct IsdnCardState *cs, u_char * data, int size)
 230 {
 231         while(size--)
 232                 memwritereg(cs->hw.diva.cfg_reg, 0x80, *data++);
 233 }
 234
 235 static u_char
 236 MemReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
 237 {
 238         return(memreadreg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0)));
 239 }
 240
 241 static void
 242 MemWriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
 243 {
 244         memwritereg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0), value);
 245 }
 246
 247 /* IO-Functions for IPACX type cards */
 248 static u_char
 249 MemReadISAC_IPACX(struct IsdnCardState *cs, u_char offset)
 250 {
 251         return (memreadreg(cs->hw.diva.cfg_reg, offset));
 252 }
 253
 254 static void
 255 MemWriteISAC_IPACX(struct IsdnCardState *cs, u_char offset, u_char value)
 256 {
 257         memwritereg(cs->hw.diva.cfg_reg, offset, value);
 258 }
 259
 260 static void
 261 MemReadISACfifo_IPACX(struct IsdnCardState *cs, u_char * data, int size)
 262 {
 263         while(size--)
 264                 *data++ = memreadreg(cs->hw.diva.cfg_reg, 0);
 265 }
 266
 267 static void
 268 MemWriteISACfifo_IPACX(struct IsdnCardState *cs, u_char * data, int size)
 269 {
 270         while(size--)
 271                 memwritereg(cs->hw.diva.cfg_reg, 0, *data++);
 272 }
 273
 274 static u_char
 275 MemReadHSCX_IPACX(struct IsdnCardState *cs, int hscx, u_char offset)
 276 {
 277         return(memreadreg(cs->hw.diva.cfg_reg, offset +
 278                     (hscx ? IPACX_OFF_B2 : IPACX_OFF_B1)));
 279 }
 280
 281 static void
 282 MemWriteHSCX_IPACX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
 283 {
 284         memwritereg(cs->hw.diva.cfg_reg, offset +
 285               (hscx ? IPACX_OFF_B2 : IPACX_OFF_B1), value);
 286 }
 287
 288 /*
 289  * fast interrupt HSCX stuff goes here
 290  */
 291
 292 #define READHSCX(cs, nr, reg) readreg(cs->hw.diva.hscx_adr, \
 293                 cs->hw.diva.hscx, reg + (nr ? 0x40 : 0))
 294 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.diva.hscx_adr, \
 295                 cs->hw.diva.hscx, reg + (nr ? 0x40 : 0), data)
 296
 297 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.diva.hscx_adr, \
 298                 cs->hw.diva.hscx, (nr ? 0x40 : 0), ptr, cnt)
 299
 300 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.diva.hscx_adr, \
 301                 cs->hw.diva.hscx, (nr ? 0x40 : 0), ptr, cnt)
 302
 303 #include "hscx_irq.c"
 304
 305 static void
 306 diva_interrupt(int intno, void *dev_id, struct pt_regs *regs)
 307 {
 308         struct IsdnCardState *cs = dev_id;
 309         u_char val, sval;
 310         int cnt=5;
 311
 312         if (!cs) {
 313                 printk(KERN_WARNING "Diva: Spurious interrupt!\n");
 314                 return;
 315         }
 316         while (((sval = bytein(cs->hw.diva.ctrl)) & DIVA_IRQ_REQ) && cnt) {
 317                 val = readreg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_ISTA + 0x40);
 318                 if (val)
 319                         hscx_int_main(cs, val);
 320                 val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_ISTA);
 321                 if (val)
 322                         isac_interrupt(cs, val);
 323                 cnt--;
 324         }
 325         if (!cnt)
 326                 printk(KERN_WARNING "Diva: IRQ LOOP\n");
 327         writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0xFF);
 328         writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0xFF);
 329         writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0xFF);
 330         writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0x0);
 331         writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0x0);
 332         writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0x0);
 333 }
 334
 335 static void
 336 diva_irq_ipac_isa(int intno, void *dev_id, struct pt_regs *regs)
 337 {
 338         struct IsdnCardState *cs = dev_id;
 339         u_char ista,val;
 340         int icnt=5;
 341
 342         if (!cs) {
 343                 printk(KERN_WARNING "Diva: Spurious interrupt!\n");
 344                 return;
 345         }
 346         ista = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ISTA);
 347 Start_IPACISA:
 348         if (cs->debug & L1_DEB_IPAC)
 349                 debugl1(cs, "IPAC ISTA %02X", ista);
 350         if (ista & 0x0f) {
 351                 val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, HSCX_ISTA + 0x40);
 352                 if (ista & 0x01)
 353                         val |= 0x01;
 354                 if (ista & 0x04)
 355                         val |= 0x02;
 356                 if (ista & 0x08)
 357                         val |= 0x04;
 358                 if (val)
 359                         hscx_int_main(cs, val);
 360         }
 361         if (ista & 0x20) {
 362                 val = 0xfe & readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_ISTA + 0x80);
 363                 if (val) {
 364                         isac_interrupt(cs, val);
 365                 }
 366         }
 367         if (ista & 0x10) {
 368                 val = 0x01;
 369                 isac_interrupt(cs, val);
 370         }
 371         ista  = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ISTA);
 372         if ((ista & 0x3f) && icnt) {
 373                 icnt--;
 374                 goto Start_IPACISA;
 375         }
 376         if (!icnt)
 377                 printk(KERN_WARNING "DIVA IPAC IRQ LOOP\n");
 378         writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xFF);
 379         writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xC0);
 380 }
 381
 382 static inline void
 383 MemwaitforCEC(struct IsdnCardState *cs, int hscx)
 384 {
 385         int to = 50;
 386
 387         while ((MemReadHSCX(cs, hscx, HSCX_STAR) & 0x04) && to) {
 388                 udelay(1);
 389                 to--;
 390         }
 391         if (!to)
 392                 printk(KERN_WARNING "HiSax: waitforCEC timeout\n");
 393 }
 394
 395
 396 static inline void
 397 MemwaitforXFW(struct IsdnCardState *cs, int hscx)
 398 {
 399         int to = 50;
 400
 401         while ((!(MemReadHSCX(cs, hscx, HSCX_STAR) & 0x44) == 0x40) && to) {
 402                 udelay(1);
 403                 to--;
 404         }
 405         if (!to)
 406                 printk(KERN_WARNING "HiSax: waitforXFW timeout\n");
 407 }
 408
 409 static inline void
 410 MemWriteHSCXCMDR(struct IsdnCardState *cs, int hscx, u_char data)
 411 {
 412         long flags;
 413
 414         save_flags(flags);
 415         cli();
 416         MemwaitforCEC(cs, hscx);
 417         MemWriteHSCX(cs, hscx, HSCX_CMDR, data);
 418         restore_flags(flags);
 419 }
 420
 421 static void
 422 Memhscx_empty_fifo(struct BCState *bcs, int count)
 423 {
 424         u_char *ptr;
 425         struct IsdnCardState *cs = bcs->cs;
 426         long flags;
 427         int cnt;
 428
 429         if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
 430                 debugl1(cs, "hscx_empty_fifo");
 431
 432         if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) {
 433                 if (cs->debug & L1_DEB_WARN)
 434                         debugl1(cs, "hscx_empty_fifo: incoming packet too large");
 435                 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80);
 436                 bcs->hw.hscx.rcvidx = 0;
 437                 return;
 438         }
 439         save_flags(flags);
 440         cli();
 441         ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
 442         cnt = count;
 443         while (cnt--)
 444                 *ptr++ = memreadreg(cs->hw.diva.cfg_reg, bcs->hw.hscx.hscx ? 0x40 : 0);
 445         MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80);
 446         ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
 447         bcs->hw.hscx.rcvidx += count;
 448         restore_flags(flags);
 449         if (cs->debug & L1_DEB_HSCX_FIFO) {
 450                 char *t = bcs->blog;
 451
 452                 t += sprintf(t, "hscx_empty_fifo %c cnt %d",
 453                              bcs->hw.hscx.hscx ? 'B' : 'A', count);
 454                 QuickHex(t, ptr, count);
 455                 debugl1(cs, bcs->blog);
 456         }
 457 }
 458
 459 static void
 460 Memhscx_fill_fifo(struct BCState *bcs)
 461 {
 462         struct IsdnCardState *cs = bcs->cs;
 463         int more, count, cnt;
 464         int fifo_size = test_bit(HW_IPAC, &cs->HW_Flags)? 64: 32;
 465         u_char *ptr,*p;
 466         long flags;
 467
 468
 469         if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
 470                 debugl1(cs, "hscx_fill_fifo");
 471
 472         if (!bcs->tx_skb)
 473                 return;
 474         if (bcs->tx_skb->len <= 0)
 475                 return;
 476
 477         more = (bcs->mode == L1_MODE_TRANS) ? 1 : 0;
 478         if (bcs->tx_skb->len > fifo_size) {
 479                 more = !0;
 480                 count = fifo_size;
 481         } else
 482                 count = bcs->tx_skb->len;
 483         cnt = count;
 484         MemwaitforXFW(cs, bcs->hw.hscx.hscx);
 485         save_flags(flags);
 486         cli();
 487         p = ptr = bcs->tx_skb->data;
 488         skb_pull(bcs->tx_skb, count);
 489         bcs->tx_cnt -= count;
 490         bcs->hw.hscx.count += count;
 491         while(cnt--)
 492                 memwritereg(cs->hw.diva.cfg_reg, bcs->hw.hscx.hscx ? 0x40 : 0,
 493                         *p++);
 494         MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, more ? 0x8 : 0xa);
 495         restore_flags(flags);
 496         if (cs->debug & L1_DEB_HSCX_FIFO) {
 497                 char *t = bcs->blog;
 498
 499                 t += sprintf(t, "hscx_fill_fifo %c cnt %d",
 500                              bcs->hw.hscx.hscx ? 'B' : 'A', count);
 501                 QuickHex(t, ptr, count);
 502                 debugl1(cs, bcs->blog);
 503         }
 504 }
 505
 506 static inline void
 507 Memhscx_interrupt(struct IsdnCardState *cs, u_char val, u_char hscx)
 508 {
 509         u_char r;
 510         struct BCState *bcs = cs->bcs + hscx;
 511         struct sk_buff *skb;
 512         int fifo_size = test_bit(HW_IPAC, &cs->HW_Flags)? 64: 32;
 513         int count;
 514
 515         if (!test_bit(BC_FLG_INIT, &bcs->Flag))
 516                 return;
 517
 518         if (val & 0x80) {       /* RME */
 519                 r = MemReadHSCX(cs, hscx, HSCX_RSTA);
 520                 if ((r & 0xf0) != 0xa0) {
 521                         if (!(r & 0x80))
 522                                 if (cs->debug & L1_DEB_WARN)
 523                                         debugl1(cs, "HSCX invalid frame");
 524                         if ((r & 0x40) && bcs->mode)
 525                                 if (cs->debug & L1_DEB_WARN)
 526                                         debugl1(cs, "HSCX RDO mode=%d",
 527                                                 bcs->mode);
 528                         if (!(r & 0x20))
 529                                 if (cs->debug & L1_DEB_WARN)
 530                                         debugl1(cs, "HSCX CRC error");
 531                         MemWriteHSCXCMDR(cs, hscx, 0x80);
 532                 } else {
 533                         count = MemReadHSCX(cs, hscx, HSCX_RBCL) & (
 534                                 test_bit(HW_IPAC, &cs->HW_Flags)? 0x3f: 0x1f);
 535                         if (count == 0)
 536                                 count = fifo_size;
 537                         Memhscx_empty_fifo(bcs, count);
 538                         if ((count = bcs->hw.hscx.rcvidx - 1) > 0) {
 539                                 if (cs->debug & L1_DEB_HSCX_FIFO)
 540                                         debugl1(cs, "HX Frame %d", count);
 541                                 if (!(skb = dev_alloc_skb(count)))
 542                                         printk(KERN_WARNING "HSCX: receive out of memory\n");
 543                                 else {
 544                                         memcpy(skb_put(skb, count), bcs->hw.hscx.rcvbuf, count);
 545                                         skb_queue_tail(&bcs->rqueue, skb);
 546                                 }
 547                         }
 548                 }
 549                 bcs->hw.hscx.rcvidx = 0;
 550                 hscx_sched_event(bcs, B_RCVBUFREADY);
 551         }
 552         if (val & 0x40) {       /* RPF */
 553                 Memhscx_empty_fifo(bcs, fifo_size);
 554                 if (bcs->mode == L1_MODE_TRANS) {
 555                         /* receive audio data */
 556                         if (!(skb = dev_alloc_skb(fifo_size)))
 557                                 printk(KERN_WARNING "HiSax: receive out of memory\n");
 558                         else {
 559                                 memcpy(skb_put(skb, fifo_size), bcs->hw.hscx.rcvbuf, fifo_size);
 560                                 skb_queue_tail(&bcs->rqueue, skb);
 561                         }
 562                         bcs->hw.hscx.rcvidx = 0;
 563                         hscx_sched_event(bcs, B_RCVBUFREADY);
 564                 }
 565         }
 566         if (val & 0x10) {       /* XPR */
 567                 if (bcs->tx_skb) {
 568                         if (bcs->tx_skb->len) {
 569                                 Memhscx_fill_fifo(bcs);
 570                                 return;
 571                         } else {
 572                                 if (bcs->st->lli.l1writewakeup &&
 573                                         (PACKET_NOACK != bcs->tx_skb->pkt_type))
 574                                         bcs->st->lli.l1writewakeup(bcs->st, bcs->hw.hscx.count);
 575                                 dev_kfree_skb_irq(bcs->tx_skb);
 576                                 bcs->hw.hscx.count = 0;
 577                                 bcs->tx_skb = NULL;
 578                         }
 579                 }
 580                 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
 581                         bcs->hw.hscx.count = 0;
 582                         test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
 583                         Memhscx_fill_fifo(bcs);
 584                 } else {
 585                         test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
 586                         hscx_sched_event(bcs, B_XMTBUFREADY);
 587                 }
 588         }
 589 }
 590
 591 static inline void
 592 Memhscx_int_main(struct IsdnCardState *cs, u_char val)
 593 {
 594
 595         u_char exval;
 596         struct BCState *bcs;
 597
 598         if (val & 0x01) { // EXB
 599                 bcs = cs->bcs + 1;
 600                 exval = MemReadHSCX(cs, 1, HSCX_EXIR);
 601                 if (exval & 0x40) {
 602                         if (bcs->mode == 1)
 603                                 Memhscx_fill_fifo(bcs);
 604                         else {
 605                                 /* Here we lost an TX interrupt, so
 606                                    * restart transmitting the whole frame.
 607                                  */
 608                                 if (bcs->tx_skb) {
 609                                         skb_push(bcs->tx_skb, bcs->hw.hscx.count);
 610                                         bcs->tx_cnt += bcs->hw.hscx.count;
 611                                         bcs->hw.hscx.count = 0;
 612                                 }
 613                                 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01);
 614                                 if (cs->debug & L1_DEB_WARN)
 615                                         debugl1(cs, "HSCX B EXIR %x Lost TX", exval);
 616                         }
 617                 } else if (cs->debug & L1_DEB_HSCX)
 618                         debugl1(cs, "HSCX B EXIR %x", exval);
 619         }
 620         if (val & 0xf8) {
 621                 if (cs->debug & L1_DEB_HSCX)
 622                         debugl1(cs, "HSCX B interrupt %x", val);
 623                 Memhscx_interrupt(cs, val, 1);
 624         }
 625         if (val & 0x02) {       // EXA
 626                 bcs = cs->bcs;
 627                 exval = MemReadHSCX(cs, 0, HSCX_EXIR);
 628                 if (exval & 0x40) {
 629                         if (bcs->mode == L1_MODE_TRANS)
 630                                 Memhscx_fill_fifo(bcs);
 631                         else {
 632                                 /* Here we lost an TX interrupt, so
 633                                    * restart transmitting the whole frame.
 634                                  */
 635                                 if (bcs->tx_skb) {
 636                                         skb_push(bcs->tx_skb, bcs->hw.hscx.count);
 637                                         bcs->tx_cnt += bcs->hw.hscx.count;
 638                                         bcs->hw.hscx.count = 0;
 639                                 }
 640                                 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01);
 641                                 if (cs->debug & L1_DEB_WARN)
 642                                         debugl1(cs, "HSCX A EXIR %x Lost TX", exval);
 643                         }
 644                 } else if (cs->debug & L1_DEB_HSCX)
 645                         debugl1(cs, "HSCX A EXIR %x", exval);
 646         }
 647         if (val & 0x04) {       // ICA
 648                 exval = MemReadHSCX(cs, 0, HSCX_ISTA);
 649                 if (cs->debug & L1_DEB_HSCX)
 650                         debugl1(cs, "HSCX A interrupt %x", exval);
 651                 Memhscx_interrupt(cs, exval, 0);
 652         }
 653 }
 654
 655 static void
 656 diva_irq_ipac_pci(int intno, void *dev_id, struct pt_regs *regs)
 657 {
 658         struct IsdnCardState *cs = dev_id;
 659         u_char ista,val;
 660         int icnt=5;
 661         u_char *cfg;
 662
 663         if (!cs) {
 664                 printk(KERN_WARNING "Diva: Spurious interrupt!\n");
 665                 return;
 666         }
 667         cfg = (u_char *) cs->hw.diva.pci_cfg;
 668         val = *cfg;
 669         if (!(val & PITA_INT0_STATUS))
 670                 return; /* other shared IRQ */
 671         *cfg = PITA_INT0_STATUS; /* Reset pending INT0 */
 672         ista = memreadreg(cs->hw.diva.cfg_reg, IPAC_ISTA);
 673 Start_IPACPCI:
 674         if (cs->debug & L1_DEB_IPAC)
 675                 debugl1(cs, "IPAC ISTA %02X", ista);
 676         if (ista & 0x0f) {
 677                 val = memreadreg(cs->hw.diva.cfg_reg, HSCX_ISTA + 0x40);
 678                 if (ista & 0x01)
 679                         val |= 0x01;
 680                 if (ista & 0x04)
 681                         val |= 0x02;
 682                 if (ista & 0x08)
 683                         val |= 0x04;
 684                 if (val)
 685                         Memhscx_int_main(cs, val);
 686         }
 687         if (ista & 0x20) {
 688                 val = 0xfe & memreadreg(cs->hw.diva.cfg_reg, ISAC_ISTA + 0x80);
 689                 if (val) {
 690                         isac_interrupt(cs, val);
 691                 }
 692         }
 693         if (ista & 0x10) {
 694                 val = 0x01;
 695                 isac_interrupt(cs, val);
 696         }
 697         ista  = memreadreg(cs->hw.diva.cfg_reg, IPAC_ISTA);
 698         if ((ista & 0x3f) && icnt) {
 699                 icnt--;
 700                 goto Start_IPACPCI;
 701         }
 702         if (!icnt)
 703                 printk(KERN_WARNING "DIVA IPAC PCI IRQ LOOP\n");
 704         memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xFF);
 705         memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xC0);
 706 }
 707
 708 static void
 709 diva_irq_ipacx_pci(int intno, void *dev_id, struct pt_regs *regs)
 710 {
 711         struct IsdnCardState *cs = dev_id;
 712         u_char val;
 713         u_char *cfg;
 714
 715         if (!cs) {
 716                 printk(KERN_WARNING "Diva: Spurious interrupt!\n");
 717                 return;
 718         }
 719         cfg = (u_char *) cs->hw.diva.pci_cfg;
 720         val = *cfg;
 721         if (!(val &PITA_INT0_STATUS)) return; // other shared IRQ
 722   interrupt_ipacx(cs);      // handler for chip
 723         *cfg = PITA_INT0_STATUS;  // Reset PLX interrupt
 724 }
 725
 726 void
 727 release_io_diva(struct IsdnCardState *cs)
 728 {
 729         int bytecnt;
 730
 731         if ((cs->subtyp == DIVA_IPAC_PCI) ||
 732             (cs->subtyp == DIVA_IPACX_PCI)   ) {
 733                 u_int *cfg = (unsigned int *)cs->hw.diva.pci_cfg;
 734
 735                 *cfg = 0; /* disable INT0/1 */
 736                 *cfg = 2; /* reset pending INT0 */
 737                 iounmap((void *)cs->hw.diva.cfg_reg);
 738                 iounmap((void *)cs->hw.diva.pci_cfg);
 739                 return;
 740         } else if (cs->subtyp != DIVA_IPAC_ISA) {
 741                 del_timer(&cs->hw.diva.tl);
 742                 if (cs->hw.diva.cfg_reg)
 743                         byteout(cs->hw.diva.ctrl, 0); /* LED off, Reset */
 744         }
 745         if ((cs->subtyp == DIVA_ISA) || (cs->subtyp == DIVA_IPAC_ISA))
 746                 bytecnt = 8;
 747         else
 748                 bytecnt = 32;
 749         if (cs->hw.diva.cfg_reg) {
 750                 release_region(cs->hw.diva.cfg_reg, bytecnt);
 751         }
 752 }
 753
 754 static void
 755 reset_diva(struct IsdnCardState *cs)
 756 {
 757         long flags;
 758
 759         save_flags(flags);
 760         sti();
 761         if (cs->subtyp == DIVA_IPAC_ISA) {
 762                 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_POTA2, 0x20);
 763                 set_current_state(TASK_UNINTERRUPTIBLE);
 764                 schedule_timeout((10*HZ)/1000);
 765                 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_POTA2, 0x00);
 766                 set_current_state(TASK_UNINTERRUPTIBLE);
 767                 schedule_timeout((10*HZ)/1000);
 768                 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xc0);
 769         } else if (cs->subtyp == DIVA_IPAC_PCI) {
 770                 unsigned int *ireg = (unsigned int *)(cs->hw.diva.pci_cfg +
 771                                         PITA_MISC_REG);
 772                 *ireg = PITA_PARA_SOFTRESET | PITA_PARA_MPX_MODE;
 773                 set_current_state(TASK_UNINTERRUPTIBLE);
 774                 schedule_timeout((10*HZ)/1000);
 775                 *ireg = PITA_PARA_MPX_MODE;
 776                 set_current_state(TASK_UNINTERRUPTIBLE);
 777                 schedule_timeout((10*HZ)/1000);
 778                 memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xc0);
 779         } else if (cs->subtyp == DIVA_IPACX_PCI) {
 780                 unsigned int *ireg = (unsigned int *)(cs->hw.diva.pci_cfg +
 781                                         PITA_MISC_REG);
 782                 *ireg = PITA_PARA_SOFTRESET | PITA_PARA_MPX_MODE;
 783                 set_current_state(TASK_UNINTERRUPTIBLE);
 784                 schedule_timeout((10*HZ)/1000);
 785                 *ireg = PITA_PARA_MPX_MODE | PITA_SER_SOFTRESET;
 786                 set_current_state(TASK_UNINTERRUPTIBLE);
 787                 schedule_timeout((10*HZ)/1000);
 788                 MemWriteISAC_IPACX(cs, IPACX_MASK, 0xff); // Interrupts off
 789         } else { /* DIVA 2.0 */
 790                 cs->hw.diva.ctrl_reg = 0;        /* Reset On */
 791                 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
 792                 set_current_state(TASK_UNINTERRUPTIBLE);
 793                 schedule_timeout((10*HZ)/1000);
 794                 cs->hw.diva.ctrl_reg |= DIVA_RESET;  /* Reset Off */
 795                 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
 796                 set_current_state(TASK_UNINTERRUPTIBLE);
 797                 schedule_timeout((10*HZ)/1000);
 798                 if (cs->subtyp == DIVA_ISA)
 799                         cs->hw.diva.ctrl_reg |= DIVA_ISA_LED_A;
 800                 else {
 801                         /* Workaround PCI9060 */
 802                         byteout(cs->hw.diva.pci_cfg + 0x69, 9);
 803                         cs->hw.diva.ctrl_reg |= DIVA_PCI_LED_A;
 804                 }
 805                 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
 806         }
 807         restore_flags(flags);
 808 }
 809
 810 #define DIVA_ASSIGN 1
 811
 812 static void
 813 diva_led_handler(struct IsdnCardState *cs)
 814 {
 815         int blink = 0;
 816
 817         if ((cs->subtyp == DIVA_IPAC_ISA) ||
 818             (cs->subtyp == DIVA_IPAC_PCI) ||
 819             (cs->subtyp == DIVA_IPACX_PCI)   )
 820                 return;
 821         del_timer(&cs->hw.diva.tl);
 822         if (cs->hw.diva.status & DIVA_ASSIGN)
 823                 cs->hw.diva.ctrl_reg |= (DIVA_ISA == cs->subtyp) ?
 824                         DIVA_ISA_LED_A : DIVA_PCI_LED_A;
 825         else {
 826                 cs->hw.diva.ctrl_reg ^= (DIVA_ISA == cs->subtyp) ?
 827                         DIVA_ISA_LED_A : DIVA_PCI_LED_A;
 828                 blink = 250;
 829         }
 830         if (cs->hw.diva.status & 0xf000)
 831                 cs->hw.diva.ctrl_reg |= (DIVA_ISA == cs->subtyp) ?
 832                         DIVA_ISA_LED_B : DIVA_PCI_LED_B;
 833         else if (cs->hw.diva.status & 0x0f00) {
 834                 cs->hw.diva.ctrl_reg ^= (DIVA_ISA == cs->subtyp) ?
 835                         DIVA_ISA_LED_B : DIVA_PCI_LED_B;
 836                 blink = 500;
 837         } else
 838                 cs->hw.diva.ctrl_reg &= ~((DIVA_ISA == cs->subtyp) ?
 839                         DIVA_ISA_LED_B : DIVA_PCI_LED_B);
 840
 841         byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
 842         if (blink) {
 843                 init_timer(&cs->hw.diva.tl);
 844                 cs->hw.diva.tl.expires = jiffies + ((blink * HZ) / 1000);
 845                 add_timer(&cs->hw.diva.tl);
 846         }
 847 }
 848
 849 static int
 850 Diva_card_msg(struct IsdnCardState *cs, int mt, void *arg)
 851 {
 852         u_int *ireg;
 853
 854         switch (mt) {
 855                 case CARD_RESET:
 856                         reset_diva(cs);
 857                         return(0);
 858                 case CARD_RELEASE:
 859                         release_io_diva(cs);
 860                         return(0);
 861                 case CARD_INIT:
 862                         if (cs->subtyp == DIVA_IPACX_PCI) {
 863                                 ireg = (unsigned int *)cs->hw.diva.pci_cfg;
 864                                 *ireg = PITA_INT0_ENABLE;
 865                           init_ipacx(cs, 3); // init chip and enable interrupts
 866         return (0);
 867                         }
 868                         if (cs->subtyp == DIVA_IPAC_PCI) {
 869                                 ireg = (unsigned int *)cs->hw.diva.pci_cfg;
 870                                 *ireg = PITA_INT0_ENABLE;
 871                         }
 872                         inithscxisac(cs, 3);
 873                         return(0);
 874                 case CARD_TEST:
 875                         return(0);
 876                 case (MDL_REMOVE | REQUEST):
 877                         cs->hw.diva.status = 0;
 878                         break;
 879                 case (MDL_ASSIGN | REQUEST):
 880                         cs->hw.diva.status |= DIVA_ASSIGN;
 881                         break;
 882                 case MDL_INFO_SETUP:
 883                         if ((long)arg)
 884                                 cs->hw.diva.status |=  0x0200;
 885                         else
 886                                 cs->hw.diva.status |=  0x0100;
 887                         break;
 888                 case MDL_INFO_CONN:
 889                         if ((long)arg)
 890                                 cs->hw.diva.status |=  0x2000;
 891                         else
 892                                 cs->hw.diva.status |=  0x1000;
 893                         break;
 894                 case MDL_INFO_REL:
 895                         if ((long)arg) {
 896                                 cs->hw.diva.status &=  ~0x2000;
 897                                 cs->hw.diva.status &=  ~0x0200;
 898                         } else {
 899                                 cs->hw.diva.status &=  ~0x1000;
 900                                 cs->hw.diva.status &=  ~0x0100;
 901                         }
 902                         break;
 903         }
 904         if ((cs->subtyp != DIVA_IPAC_ISA) &&
 905             (cs->subtyp != DIVA_IPAC_PCI) &&
 906             (cs->subtyp != DIVA_IPACX_PCI)   )
 907                 diva_led_handler(cs);
 908         return(0);
 909 }
 910
 911 static struct pci_dev *dev_diva __initdata = NULL;
 912 static struct pci_dev *dev_diva_u __initdata = NULL;
 913 static struct pci_dev *dev_diva201 __initdata = NULL;
 914 static struct pci_dev *dev_diva202 __initdata = NULL;
 915
 916 #ifdef __ISAPNP__
 917 static struct isapnp_device_id diva_ids[] __initdata = {
 918         { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x51),
 919           ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x51),
 920           (unsigned long) "Diva picola" },
 921         { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x51),
 922           ISAPNP_VENDOR('E', 'I', 'C'), ISAPNP_FUNCTION(0x51),
 923           (unsigned long) "Diva picola" },
 924         { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x71),
 925           ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x71),
 926           (unsigned long) "Diva 2.0" },
 927         { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x71),
 928           ISAPNP_VENDOR('E', 'I', 'C'), ISAPNP_FUNCTION(0x71),
 929           (unsigned long) "Diva 2.0" },
 930         { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0xA1),
 931           ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0xA1),
 932           (unsigned long) "Diva 2.01" },
 933         { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0xA1),
 934           ISAPNP_VENDOR('E', 'I', 'C'), ISAPNP_FUNCTION(0xA1),
 935           (unsigned long) "Diva 2.01" },
 936         { 0, }
 937 };
 938
 939 static struct isapnp_device_id *pdev = &diva_ids[0];
 940 static struct pci_bus *pnp_c __devinitdata = NULL;
 941 #endif
 942
 943
 944 int __init
 945 setup_diva(struct IsdnCard *card)
 946 {
 947         int bytecnt = 8;
 948         u_char val;
 949         struct IsdnCardState *cs = card->cs;
 950         char tmp[64];
 951
 952         strcpy(tmp, Diva_revision);
 953         printk(KERN_INFO "HiSax: Eicon.Diehl Diva driver Rev. %s\n", HiSax_getrev(tmp));
 954         if (cs->typ != ISDN_CTYPE_DIEHLDIVA)
 955                 return(0);
 956         cs->hw.diva.status = 0;
 957         if (card->para[1]) {
 958                 cs->hw.diva.ctrl_reg = 0;
 959                 cs->hw.diva.cfg_reg = card->para[1];
 960                 val = readreg(cs->hw.diva.cfg_reg + DIVA_IPAC_ADR,
 961                         cs->hw.diva.cfg_reg + DIVA_IPAC_DATA, IPAC_ID);
 962                 printk(KERN_INFO "Diva: IPAC version %x\n", val);
 963                 if ((val == 1) || (val==2)) {
 964                         cs->subtyp = DIVA_IPAC_ISA;
 965                         cs->hw.diva.ctrl = 0;
 966                         cs->hw.diva.isac = card->para[1] + DIVA_IPAC_DATA;
 967                         cs->hw.diva.hscx = card->para[1] + DIVA_IPAC_DATA;
 968                         cs->hw.diva.isac_adr = card->para[1] + DIVA_IPAC_ADR;
 969                         cs->hw.diva.hscx_adr = card->para[1] + DIVA_IPAC_ADR;
 970                         test_and_set_bit(HW_IPAC, &cs->HW_Flags);
 971                 } else {
 972                         cs->subtyp = DIVA_ISA;
 973                         cs->hw.diva.ctrl = card->para[1] + DIVA_ISA_CTRL;
 974                         cs->hw.diva.isac = card->para[1] + DIVA_ISA_ISAC_DATA;
 975                         cs->hw.diva.hscx = card->para[1] + DIVA_HSCX_DATA;
 976                         cs->hw.diva.isac_adr = card->para[1] + DIVA_ISA_ISAC_ADR;
 977                         cs->hw.diva.hscx_adr = card->para[1] + DIVA_HSCX_ADR;
 978                 }
 979                 cs->irq = card->para[0];
 980         } else {
 981 #ifdef __ISAPNP__
 982                 if (isapnp_present()) {
 983                         struct pci_bus *pb;
 984                         struct pci_dev *pd;
 985
 986                         while(pdev->card_vendor) {
 987                                 if ((pb = isapnp_find_card(pdev->card_vendor,
 988                                         pdev->card_device, pnp_c))) {
 989                                         pnp_c = pb;
 990                                         pd = NULL;
 991                                         if ((pd = isapnp_find_dev(pnp_c,
 992                                                 pdev->vendor, pdev->function, pd))) {
 993                                                 printk(KERN_INFO "HiSax: %s detected\n",
 994                                                         (char *)pdev->driver_data);
 995                                                 pd->prepare(pd);
 996                                                 pd->deactivate(pd);
 997                                                 pd->activate(pd);
 998                                                 card->para[1] =
 999                                                         pd->resource[0].start;
1000                                                 card->para[0] =
1001                                                         pd->irq_resource[0].start;
1002                                                 if (!card->para[0] || !card->para[1]) {
1003                                                         printk(KERN_ERR "Diva PnP:some resources are missing %ld/%lx\n",
1004                                                                 card->para[0], card->para[1]);
1005                                                         pd->deactivate(pd);
1006                                                         return(0);
1007                                                 }
1008                                                 cs->hw.diva.cfg_reg  = card->para[1];
1009                                                 cs->irq = card->para[0];
1010                                                 if (pdev->function == ISAPNP_FUNCTION(0xA1)) {
1011                                                         cs->subtyp = DIVA_IPAC_ISA;
1012                                                         cs->hw.diva.ctrl = 0;
1013                                                         cs->hw.diva.isac =
1014                                                                 card->para[1] + DIVA_IPAC_DATA;
1015                                                         cs->hw.diva.hscx =
1016                                                                 card->para[1] + DIVA_IPAC_DATA;
1017                                                         cs->hw.diva.isac_adr =
1018                                                                 card->para[1] + DIVA_IPAC_ADR;
1019                                                         cs->hw.diva.hscx_adr =
1020                                                                 card->para[1] + DIVA_IPAC_ADR;
1021                                                         test_and_set_bit(HW_IPAC, &cs->HW_Flags);
1022                                                 } else {
1023                                                         cs->subtyp = DIVA_ISA;
1024                                                         cs->hw.diva.ctrl =
1025                                                                 card->para[1] + DIVA_ISA_CTRL;
1026                                                         cs->hw.diva.isac =
1027                                                                 card->para[1] + DIVA_ISA_ISAC_DATA;
1028                                                         cs->hw.diva.hscx =
1029                                                                 card->para[1] + DIVA_HSCX_DATA;
1030                                                         cs->hw.diva.isac_adr =
1031                                                                 card->para[1] + DIVA_ISA_ISAC_ADR;
1032                                                         cs->hw.diva.hscx_adr =
1033                                                                 card->para[1] + DIVA_HSCX_ADR;
1034                                                 }
1035                                                 goto ready;
1036                                         } else {
1037                                                 printk(KERN_ERR "Diva PnP: PnP error card found, no device\n");
1038                                                 return(0);
1039                                         }
1040                                 }
1041                                 pdev++;
1042                                 pnp_c=NULL;
1043                         }
1044                         if (!pdev->card_vendor) {
1045                                 printk(KERN_INFO "Diva PnP: no ISAPnP card found\n");
1046                         }
1047                 }
1048 #endif
1049 #if CONFIG_PCI
1050                 if (!pci_present()) {
1051                         printk(KERN_ERR "Diva: no PCI bus present\n");
1052                         return(0);
1053                 }
1054
1055                 cs->subtyp = 0;
1056                 if ((dev_diva = pci_find_device(PCI_VENDOR_ID_EICON,
1057                         PCI_DEVICE_ID_EICON_DIVA20, dev_diva))) {
1058                         if (pci_enable_device(dev_diva))
1059                                 return(0);
1060                         cs->subtyp = DIVA_PCI;
1061                         cs->irq = dev_diva->irq;
1062                         cs->hw.diva.cfg_reg = pci_resource_start(dev_diva, 2);
1063                 } else if ((dev_diva_u = pci_find_device(PCI_VENDOR_ID_EICON,
1064                         PCI_DEVICE_ID_EICON_DIVA20_U, dev_diva_u))) {
1065                         if (pci_enable_device(dev_diva_u))
1066                                 return(0);
1067                         cs->subtyp = DIVA_PCI;
1068                         cs->irq = dev_diva_u->irq;
1069                         cs->hw.diva.cfg_reg = pci_resource_start(dev_diva_u, 2);
1070                 } else if ((dev_diva201 = pci_find_device(PCI_VENDOR_ID_EICON,
1071                         PCI_DEVICE_ID_EICON_DIVA201, dev_diva201))) {
1072                         if (pci_enable_device(dev_diva201))
1073                                 return(0);
1074                         cs->subtyp = DIVA_IPAC_PCI;
1075                         cs->irq = dev_diva201->irq;
1076                         cs->hw.diva.pci_cfg =
1077                                 (ulong) ioremap(pci_resource_start(dev_diva201, 0), 4096);
1078                         cs->hw.diva.cfg_reg =
1079                                 (ulong) ioremap(pci_resource_start(dev_diva201, 1), 4096);
1080                 } else if ((dev_diva202 = pci_find_device(PCI_VENDOR_ID_EICON,
1081                         PCI_DEVICE_ID_EICON_DIVA202, dev_diva202))) {
1082                         if (pci_enable_device(dev_diva202))
1083                                 return(0);
1084                         cs->subtyp = DIVA_IPACX_PCI;
1085                         cs->irq = dev_diva202->irq;
1086                         cs->hw.diva.pci_cfg =
1087                                 (ulong) ioremap(pci_resource_start(dev_diva202, 0), 4096);
1088                         cs->hw.diva.cfg_reg =
1089                                 (ulong) ioremap(pci_resource_start(dev_diva202, 1), 4096);
1090                 } else {
1091                         printk(KERN_WARNING "Diva: No PCI card found\n");
1092                         return(0);
1093                 }
1094
1095                 if (!cs->irq) {
1096                         printk(KERN_WARNING "Diva: No IRQ for PCI card found\n");
1097                         return(0);
1098                 }
1099
1100                 if (!cs->hw.diva.cfg_reg) {
1101                         printk(KERN_WARNING "Diva: No IO-Adr for PCI card found\n");
1102                         return(0);
1103                 }
1104                 cs->irq_flags |= SA_SHIRQ;
1105 #else
1106                 printk(KERN_WARNING "Diva: cfgreg 0 and NO_PCI_BIOS\n");
1107                 printk(KERN_WARNING "Diva: unable to config DIVA PCI\n");
1108                 return (0);
1109 #endif /* CONFIG_PCI */
1110                 if ((cs->subtyp == DIVA_IPAC_PCI) ||
1111                     (cs->subtyp == DIVA_IPACX_PCI)   ) {
1112                         cs->hw.diva.ctrl = 0;
1113                         cs->hw.diva.isac = 0;
1114                         cs->hw.diva.hscx = 0;
1115                         cs->hw.diva.isac_adr = 0;
1116                         cs->hw.diva.hscx_adr = 0;
1117                         test_and_set_bit(HW_IPAC, &cs->HW_Flags);
1118                         bytecnt = 0;
1119                 } else {
1120                         cs->hw.diva.ctrl = cs->hw.diva.cfg_reg + DIVA_PCI_CTRL;
1121                         cs->hw.diva.isac = cs->hw.diva.cfg_reg + DIVA_PCI_ISAC_DATA;
1122                         cs->hw.diva.hscx = cs->hw.diva.cfg_reg + DIVA_HSCX_DATA;
1123                         cs->hw.diva.isac_adr = cs->hw.diva.cfg_reg + DIVA_PCI_ISAC_ADR;
1124                         cs->hw.diva.hscx_adr = cs->hw.diva.cfg_reg + DIVA_HSCX_ADR;
1125                         bytecnt = 32;
1126                 }
1127         }
1128 ready:
1129         printk(KERN_INFO
1130                 "Diva: %s card configured at %#lx IRQ %d\n",
1131                 (cs->subtyp == DIVA_PCI) ? "PCI" :
1132                 (cs->subtyp == DIVA_ISA) ? "ISA" :
1133                 (cs->subtyp == DIVA_IPAC_ISA) ? "IPAC ISA" :
1134                 (cs->subtyp == DIVA_IPAC_PCI) ? "IPAC PCI" : "IPACX PCI",
1135                 cs->hw.diva.cfg_reg, cs->irq);
1136         if ((cs->subtyp == DIVA_IPAC_PCI)  ||
1137             (cs->subtyp == DIVA_IPACX_PCI) ||
1138             (cs->subtyp == DIVA_PCI)         )
1139                 printk(KERN_INFO "Diva: %s space at %#lx\n",
1140                         (cs->subtyp == DIVA_PCI) ? "PCI" :
1141                         (cs->subtyp == DIVA_IPAC_PCI) ? "IPAC PCI" : "IPACX PCI",
1142                         cs->hw.diva.pci_cfg);
1143         if ((cs->subtyp != DIVA_IPAC_PCI) &&
1144             (cs->subtyp != DIVA_IPACX_PCI)   ) {
1145                 if (check_region(cs->hw.diva.cfg_reg, bytecnt)) {
1146                         printk(KERN_WARNING
1147                                "HiSax: %s config port %lx-%lx already in use\n",
1148                                CardType[card->typ],
1149                                cs->hw.diva.cfg_reg,
1150                                cs->hw.diva.cfg_reg + bytecnt);
1151                         return (0);
1152                 } else {
1153                         request_region(cs->hw.diva.cfg_reg, bytecnt, "diva isdn");
1154                 }
1155         }
1156         reset_diva(cs);
1157         cs->BC_Read_Reg  = &ReadHSCX;
1158         cs->BC_Write_Reg = &WriteHSCX;
1159         cs->BC_Send_Data = &hscx_fill_fifo;
1160         cs->cardmsg = &Diva_card_msg;
1161         if (cs->subtyp == DIVA_IPAC_ISA) {
1162                 cs->readisac  = &ReadISAC_IPAC;
1163                 cs->writeisac = &WriteISAC_IPAC;
1164                 cs->readisacfifo  = &ReadISACfifo_IPAC;
1165                 cs->writeisacfifo = &WriteISACfifo_IPAC;
1166                 cs->irq_func = &diva_irq_ipac_isa;
1167                 val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ID);
1168                 printk(KERN_INFO "Diva: IPAC version %x\n", val);
1169         } else if (cs->subtyp == DIVA_IPAC_PCI) {
1170                 cs->readisac  = &MemReadISAC_IPAC;
1171                 cs->writeisac = &MemWriteISAC_IPAC;
1172                 cs->readisacfifo  = &MemReadISACfifo_IPAC;
1173                 cs->writeisacfifo = &MemWriteISACfifo_IPAC;
1174                 cs->BC_Read_Reg  = &MemReadHSCX;
1175                 cs->BC_Write_Reg = &MemWriteHSCX;
1176                 cs->BC_Send_Data = &Memhscx_fill_fifo;
1177                 cs->irq_func = &diva_irq_ipac_pci;
1178                 val = memreadreg(cs->hw.diva.cfg_reg, IPAC_ID);
1179                 printk(KERN_INFO "Diva: IPAC version %x\n", val);
1180         } else if (cs->subtyp == DIVA_IPACX_PCI) {
1181                 cs->readisac  = &MemReadISAC_IPACX;
1182                 cs->writeisac = &MemWriteISAC_IPACX;
1183                 cs->readisacfifo  = &MemReadISACfifo_IPACX;
1184                 cs->writeisacfifo = &MemWriteISACfifo_IPACX;
1185                 cs->BC_Read_Reg  = &MemReadHSCX_IPACX;
1186                 cs->BC_Write_Reg = &MemWriteHSCX_IPACX;
1187                 cs->BC_Send_Data = 0; // function located in ipacx module
1188                 cs->irq_func = &diva_irq_ipacx_pci;
1189                 printk(KERN_INFO "Diva: IPACX Design Id: %x\n",
1190             MemReadISAC_IPACX(cs, IPACX_ID) &0x3F);
1191         } else { /* DIVA 2.0 */
1192                 cs->hw.diva.tl.function = (void *) diva_led_handler;
1193                 cs->hw.diva.tl.data = (long) cs;
1194                 init_timer(&cs->hw.diva.tl);
1195                 cs->readisac  = &ReadISAC;
1196                 cs->writeisac = &WriteISAC;
1197                 cs->readisacfifo  = &ReadISACfifo;
1198                 cs->writeisacfifo = &WriteISACfifo;
1199                 cs->irq_func = &diva_interrupt;
1200                 ISACVersion(cs, "Diva:");
1201                 if (HscxVersion(cs, "Diva:")) {
1202                         printk(KERN_WARNING
1203                        "Diva: wrong HSCX versions check IO address\n");
1204                         release_io_diva(cs);
1205                         return (0);
1206                 }
1207         }
1208         return (1);
1209 }