drivers/isdn/hisax/hfc_2bds0.c

   1 /* $Id: hfc_2bds0.c,v 1.1.4.1 2001/11/20 14:19:35 kai Exp $
   2  *
   3  * specific routines for CCD's HFC 2BDS0
   4  *
   5  * Author       Karsten Keil
   6  * Copyright    by Karsten Keil      <keil@isdn4linux.de>
   7  *
   8  * This software may be used and distributed according to the terms
   9  * of the GNU General Public License, incorporated herein by reference.
  10  *
  11  */
  12
  13 #define __NO_VERSION__
  14 #include <linux/init.h>
  15 #include "hisax.h"
  16 #include "hfc_2bds0.h"
  17 #include "isdnl1.h"
  18 #include <linux/interrupt.h>
  19 /*
  20 #define KDEBUG_DEF
  21 #include "kdebug.h"
  22 */
  23
  24 #define byteout(addr,val) outb(val,addr)
  25 #define bytein(addr) inb(addr)
  26
  27 static void
  28 dummyf(struct IsdnCardState *cs, u_char * data, int size)
  29 {
  30         printk(KERN_WARNING "HiSax: hfcd dummy fifo called\n");
  31 }
  32
  33 static inline u_char
  34 ReadReg(struct IsdnCardState *cs, int data, u_char reg)
  35 {
  36         register u_char ret;
  37
  38         if (data) {
  39                 if (cs->hw.hfcD.cip != reg) {
  40                         cs->hw.hfcD.cip = reg;
  41                         byteout(cs->hw.hfcD.addr | 1, reg);
  42                 }
  43                 ret = bytein(cs->hw.hfcD.addr);
  44 #if HFC_REG_DEBUG
  45                 if (cs->debug & L1_DEB_HSCX_FIFO && (data != 2))
  46                         debugl1(cs, "t3c RD %02x %02x", reg, ret);
  47 #endif
  48         } else
  49                 ret = bytein(cs->hw.hfcD.addr | 1);
  50         return (ret);
  51 }
  52
  53 static inline void
  54 WriteReg(struct IsdnCardState *cs, int data, u_char reg, u_char value)
  55 {
  56         if (cs->hw.hfcD.cip != reg) {
  57                 cs->hw.hfcD.cip = reg;
  58                 byteout(cs->hw.hfcD.addr | 1, reg);
  59         }
  60         if (data)
  61                 byteout(cs->hw.hfcD.addr, value);
  62 #if HFC_REG_DEBUG
  63         if (cs->debug & L1_DEB_HSCX_FIFO && (data != HFCD_DATA_NODEB))
  64                 debugl1(cs, "t3c W%c %02x %02x", data ? 'D' : 'C', reg, value);
  65 #endif
  66 }
  67
  68 /* Interface functions */
  69
  70 static u_char
  71 readreghfcd(struct IsdnCardState *cs, u_char offset)
  72 {
  73         return(ReadReg(cs, HFCD_DATA, offset));
  74 }
  75
  76 static void
  77 writereghfcd(struct IsdnCardState *cs, u_char offset, u_char value)
  78 {
  79         WriteReg(cs, HFCD_DATA, offset, value);
  80 }
  81
  82 void
  83 set_cs_func(struct IsdnCardState *cs)
  84 {
  85         cs->readisac = &readreghfcd;
  86         cs->writeisac = &writereghfcd;
  87         cs->readisacfifo = &dummyf;
  88         cs->writeisacfifo = &dummyf;
  89         cs->BC_Read_Reg = &ReadReg;
  90         cs->BC_Write_Reg = &WriteReg;
  91 }
  92
  93 static inline int
  94 WaitForBusy(struct IsdnCardState *cs)
  95 {
  96         int to = 130;
  97
  98         while (!(ReadReg(cs, HFCD_DATA, HFCD_STAT) & HFCD_BUSY) && to) {
  99                 udelay(1);
 100                 to--;
 101         }
 102         if (!to)
 103                 printk(KERN_WARNING "HiSax: WaitForBusy timeout\n");
 104         return (to);
 105 }
 106
 107 static inline int
 108 WaitNoBusy(struct IsdnCardState *cs)
 109 {
 110         long flags;
 111         int to = 130;
 112
 113         while ((ReadReg(cs, HFCD_STATUS, HFCD_STATUS) & HFCD_BUSY) && to) {
 114                 save_flags(flags);
 115                 sti();
 116                 udelay(1);
 117                 to--;
 118                 restore_flags(flags);
 119         }
 120         if (!to)
 121                 printk(KERN_WARNING "HiSax: WaitNoBusy timeout\n");
 122         return (to);
 123 }
 124
 125 static int
 126 SelFiFo(struct IsdnCardState *cs, u_char FiFo)
 127 {
 128         u_char cip;
 129         long flags;
 130
 131
 132         if (cs->hw.hfcD.fifo == FiFo)
 133                 return(1);
 134         save_flags(flags);
 135         cli();
 136         switch(FiFo) {
 137                 case 0: cip = HFCB_FIFO | HFCB_Z1 | HFCB_SEND | HFCB_B1;
 138                         break;
 139                 case 1: cip = HFCB_FIFO | HFCB_Z1 | HFCB_REC | HFCB_B1;
 140                         break;
 141                 case 2: cip = HFCB_FIFO | HFCB_Z1 | HFCB_SEND | HFCB_B2;
 142                         break;
 143                 case 3: cip = HFCB_FIFO | HFCB_Z1 | HFCB_REC | HFCB_B2;
 144                         break;
 145                 case 4: cip = HFCD_FIFO | HFCD_Z1 | HFCD_SEND;
 146                         break;
 147                 case 5: cip = HFCD_FIFO | HFCD_Z1 | HFCD_REC;
 148                         break;
 149                 default:
 150                         restore_flags(flags);
 151                         debugl1(cs, "SelFiFo Error");
 152                         return(0);
 153         }
 154         cs->hw.hfcD.fifo = FiFo;
 155         WaitNoBusy(cs);
 156         cs->BC_Write_Reg(cs, HFCD_DATA, cip, 0);
 157         sti();
 158         WaitForBusy(cs);
 159         restore_flags(flags);
 160         return(2);
 161 }
 162 static int
 163 GetFreeFifoBytes_B(struct BCState *bcs)
 164 {
 165         int s;
 166
 167         if (bcs->hw.hfc.f1 == bcs->hw.hfc.f2)
 168                 return (bcs->cs->hw.hfcD.bfifosize);
 169         s = bcs->hw.hfc.send[bcs->hw.hfc.f1] - bcs->hw.hfc.send[bcs->hw.hfc.f2];
 170         if (s <= 0)
 171                 s += bcs->cs->hw.hfcD.bfifosize;
 172         s = bcs->cs->hw.hfcD.bfifosize - s;
 173         return (s);
 174 }
 175
 176 static int
 177 GetFreeFifoBytes_D(struct IsdnCardState *cs)
 178 {
 179         int s;
 180
 181         if (cs->hw.hfcD.f1 == cs->hw.hfcD.f2)
 182                 return (cs->hw.hfcD.dfifosize);
 183         s = cs->hw.hfcD.send[cs->hw.hfcD.f1] - cs->hw.hfcD.send[cs->hw.hfcD.f2];
 184         if (s <= 0)
 185                 s += cs->hw.hfcD.dfifosize;
 186         s = cs->hw.hfcD.dfifosize - s;
 187         return (s);
 188 }
 189
 190 static int
 191 ReadZReg(struct IsdnCardState *cs, u_char reg)
 192 {
 193         int val;
 194
 195         WaitNoBusy(cs);
 196         val = 256 * ReadReg(cs, HFCD_DATA, reg | HFCB_Z_HIGH);
 197         WaitNoBusy(cs);
 198         val += ReadReg(cs, HFCD_DATA, reg | HFCB_Z_LOW);
 199         return (val);
 200 }
 201
 202 static void
 203 hfc_sched_event(struct BCState *bcs, int event)
 204 {
 205         bcs->event |= 1 << event;
 206         queue_task(&bcs->tqueue, &tq_immediate);
 207         mark_bh(IMMEDIATE_BH);
 208 }
 209
 210 static struct sk_buff
 211 *hfc_empty_fifo(struct BCState *bcs, int count)
 212 {
 213         u_char *ptr;
 214         struct sk_buff *skb;
 215         struct IsdnCardState *cs = bcs->cs;
 216         int idx;
 217         int chksum;
 218         long flags;
 219         u_char stat, cip;
 220
 221         if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
 222                 debugl1(cs, "hfc_empty_fifo");
 223         idx = 0;
 224         save_flags(flags);
 225         if (count > HSCX_BUFMAX + 3) {
 226                 if (cs->debug & L1_DEB_WARN)
 227                         debugl1(cs, "hfc_empty_fifo: incoming packet too large");
 228                 cip = HFCB_FIFO | HFCB_FIFO_OUT | HFCB_REC | HFCB_CHANNEL(bcs->channel);
 229                 while (idx++ < count) {
 230                         cli();
 231                         WaitNoBusy(cs);
 232                         ReadReg(cs, HFCD_DATA_NODEB, cip);
 233                         sti();
 234                 }
 235                 skb = NULL;
 236         } else if (count < 4) {
 237                 if (cs->debug & L1_DEB_WARN)
 238                         debugl1(cs, "hfc_empty_fifo: incoming packet too small");
 239                 cip = HFCB_FIFO | HFCB_FIFO_OUT | HFCB_REC | HFCB_CHANNEL(bcs->channel);
 240 #ifdef ERROR_STATISTIC
 241                 bcs->err_inv++;
 242 #endif
 243                 cli();
 244                 while ((idx++ < count) && WaitNoBusy(cs))
 245                         ReadReg(cs, HFCD_DATA_NODEB, cip);
 246                 skb = NULL;
 247         } else if (!(skb = dev_alloc_skb(count - 3)))
 248                 printk(KERN_WARNING "HFC: receive out of memory\n");
 249         else {
 250                 ptr = skb_put(skb, count - 3);
 251                 idx = 0;
 252                 cip = HFCB_FIFO | HFCB_FIFO_OUT | HFCB_REC | HFCB_CHANNEL(bcs->channel);
 253                 cli();
 254                 while (idx < (count - 3)) {
 255                         cli();
 256                         if (!WaitNoBusy(cs))
 257                                 break;
 258                         *ptr = ReadReg(cs,  HFCD_DATA_NODEB, cip);
 259                         sti();
 260                         ptr++;
 261                         idx++;
 262                 }
 263                 if (idx != count - 3) {
 264                         sti();
 265                         debugl1(cs, "RFIFO BUSY error");
 266                         printk(KERN_WARNING "HFC FIFO channel %d BUSY Error\n", bcs->channel);
 267                         dev_kfree_skb_irq(skb);
 268                         skb = NULL;
 269                 } else {
 270                         cli();
 271                         WaitNoBusy(cs);
 272                         chksum = (ReadReg(cs, HFCD_DATA, cip) << 8);
 273                         WaitNoBusy(cs);
 274                         chksum += ReadReg(cs, HFCD_DATA, cip);
 275                         WaitNoBusy(cs);
 276                         stat = ReadReg(cs, HFCD_DATA, cip);
 277                         sti();
 278                         if (cs->debug & L1_DEB_HSCX)
 279                                 debugl1(cs, "hfc_empty_fifo %d chksum %x stat %x",
 280                                         bcs->channel, chksum, stat);
 281                         if (stat) {
 282                                 debugl1(cs, "FIFO CRC error");
 283                                 dev_kfree_skb_irq(skb);
 284                                 skb = NULL;
 285 #ifdef ERROR_STATISTIC
 286                                 bcs->err_crc++;
 287 #endif
 288                         }
 289                 }
 290         }
 291         sti();
 292         WaitForBusy(cs);
 293         cli();
 294         WaitNoBusy(cs);
 295         stat = ReadReg(cs, HFCD_DATA, HFCB_FIFO | HFCB_F2_INC |
 296                 HFCB_REC | HFCB_CHANNEL(bcs->channel));
 297         sti();
 298         WaitForBusy(cs);
 299         restore_flags(flags);
 300         return (skb);
 301 }
 302
 303 static void
 304 hfc_fill_fifo(struct BCState *bcs)
 305 {
 306         struct IsdnCardState *cs = bcs->cs;
 307         long flags;
 308         int idx, fcnt;
 309         int count;
 310         u_char cip;
 311
 312         if (!bcs->tx_skb)
 313                 return;
 314         if (bcs->tx_skb->len <= 0)
 315                 return;
 316         save_flags(flags);
 317         cli();
 318         SelFiFo(cs, HFCB_SEND | HFCB_CHANNEL(bcs->channel));
 319         cip = HFCB_FIFO | HFCB_F1 | HFCB_SEND | HFCB_CHANNEL(bcs->channel);
 320         WaitNoBusy(cs);
 321         bcs->hw.hfc.f1 = ReadReg(cs, HFCD_DATA, cip);
 322         WaitNoBusy(cs);
 323         cip = HFCB_FIFO | HFCB_F2 | HFCB_SEND | HFCB_CHANNEL(bcs->channel);
 324         WaitNoBusy(cs);
 325         bcs->hw.hfc.f2 = ReadReg(cs, HFCD_DATA, cip);
 326         bcs->hw.hfc.send[bcs->hw.hfc.f1] = ReadZReg(cs, HFCB_FIFO | HFCB_Z1 | HFCB_SEND | HFCB_CHANNEL(bcs->channel));
 327         sti();
 328         if (cs->debug & L1_DEB_HSCX)
 329                 debugl1(cs, "hfc_fill_fifo %d f1(%d) f2(%d) z1(%x)",
 330                         bcs->channel, bcs->hw.hfc.f1, bcs->hw.hfc.f2,
 331                         bcs->hw.hfc.send[bcs->hw.hfc.f1]);
 332         fcnt = bcs->hw.hfc.f1 - bcs->hw.hfc.f2;
 333         if (fcnt < 0)
 334                 fcnt += 32;
 335         if (fcnt > 30) {
 336                 if (cs->debug & L1_DEB_HSCX)
 337                         debugl1(cs, "hfc_fill_fifo more as 30 frames");
 338                 restore_flags(flags);
 339                 return;
 340         }
 341         count = GetFreeFifoBytes_B(bcs);
 342         if (cs->debug & L1_DEB_HSCX)
 343                 debugl1(cs, "hfc_fill_fifo %d count(%ld/%d),%lx",
 344                         bcs->channel, bcs->tx_skb->len,
 345                         count, current->state);
 346         if (count < bcs->tx_skb->len) {
 347                 if (cs->debug & L1_DEB_HSCX)
 348                         debugl1(cs, "hfc_fill_fifo no fifo mem");
 349                 restore_flags(flags);
 350                 return;
 351         }
 352         cip = HFCB_FIFO | HFCB_FIFO_IN | HFCB_SEND | HFCB_CHANNEL(bcs->channel);
 353         idx = 0;
 354         cli();
 355         WaitForBusy(cs);
 356         WaitNoBusy(cs);
 357         WriteReg(cs, HFCD_DATA_NODEB, cip, bcs->tx_skb->data[idx++]);
 358         while (idx < bcs->tx_skb->len) {
 359                 cli();
 360                 if (!WaitNoBusy(cs))
 361                         break;
 362                 WriteReg(cs, HFCD_DATA_NODEB, cip, bcs->tx_skb->data[idx]);
 363                 sti();
 364                 idx++;
 365         }
 366         if (idx != bcs->tx_skb->len) {
 367                 sti();
 368                 debugl1(cs, "FIFO Send BUSY error");
 369                 printk(KERN_WARNING "HFC S FIFO channel %d BUSY Error\n", bcs->channel);
 370         } else {
 371                 bcs->tx_cnt -= bcs->tx_skb->len;
 372                 if (bcs->st->lli.l1writewakeup &&
 373                         (PACKET_NOACK != bcs->tx_skb->pkt_type))
 374                         bcs->st->lli.l1writewakeup(bcs->st, bcs->tx_skb->len);
 375                 dev_kfree_skb_any(bcs->tx_skb);
 376                 bcs->tx_skb = NULL;
 377         }
 378         WaitForBusy(cs);
 379         cli();
 380         WaitNoBusy(cs);
 381         ReadReg(cs, HFCD_DATA, HFCB_FIFO | HFCB_F1_INC | HFCB_SEND | HFCB_CHANNEL(bcs->channel));
 382         sti();
 383         WaitForBusy(cs);
 384         test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
 385         restore_flags(flags);
 386         return;
 387 }
 388
 389 static void
 390 hfc_send_data(struct BCState *bcs)
 391 {
 392         struct IsdnCardState *cs = bcs->cs;
 393
 394         if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 395                 hfc_fill_fifo(bcs);
 396                 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 397         } else
 398                 debugl1(cs,"send_data %d blocked", bcs->channel);
 399 }
 400
 401 void
 402 main_rec_2bds0(struct BCState *bcs)
 403 {
 404         long flags;
 405         struct IsdnCardState *cs = bcs->cs;
 406         int z1, z2, rcnt;
 407         u_char f1, f2, cip;
 408         int receive, count = 5;
 409         struct sk_buff *skb;
 410
 411         save_flags(flags);
 412     Begin:
 413         count--;
 414         cli();
 415         if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 416                 debugl1(cs,"rec_data %d blocked", bcs->channel);
 417                 restore_flags(flags);
 418                 return;
 419         }
 420         SelFiFo(cs, HFCB_REC | HFCB_CHANNEL(bcs->channel));
 421         cip = HFCB_FIFO | HFCB_F1 | HFCB_REC | HFCB_CHANNEL(bcs->channel);
 422         WaitNoBusy(cs);
 423         f1 = ReadReg(cs, HFCD_DATA, cip);
 424         cip = HFCB_FIFO | HFCB_F2 | HFCB_REC | HFCB_CHANNEL(bcs->channel);
 425         WaitNoBusy(cs);
 426         f2 = ReadReg(cs, HFCD_DATA, cip);
 427         sti();
 428         if (f1 != f2) {
 429                 if (cs->debug & L1_DEB_HSCX)
 430                         debugl1(cs, "hfc rec %d f1(%d) f2(%d)",
 431                                 bcs->channel, f1, f2);
 432                 cli();
 433                 z1 = ReadZReg(cs, HFCB_FIFO | HFCB_Z1 | HFCB_REC | HFCB_CHANNEL(bcs->channel));
 434                 z2 = ReadZReg(cs, HFCB_FIFO | HFCB_Z2 | HFCB_REC | HFCB_CHANNEL(bcs->channel));
 435                 sti();
 436                 rcnt = z1 - z2;
 437                 if (rcnt < 0)
 438                         rcnt += cs->hw.hfcD.bfifosize;
 439                 rcnt++;
 440                 if (cs->debug & L1_DEB_HSCX)
 441                         debugl1(cs, "hfc rec %d z1(%x) z2(%x) cnt(%d)",
 442                                 bcs->channel, z1, z2, rcnt);
 443                 if ((skb = hfc_empty_fifo(bcs, rcnt))) {
 444                         cli();
 445                         skb_queue_tail(&bcs->rqueue, skb);
 446                         sti();
 447                         hfc_sched_event(bcs, B_RCVBUFREADY);
 448                 }
 449                 rcnt = f1 -f2;
 450                 if (rcnt<0)
 451                         rcnt += 32;
 452                 if (rcnt>1)
 453                         receive = 1;
 454                 else
 455                         receive = 0;
 456         } else
 457                 receive = 0;
 458         test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 459         if (count && receive)
 460                 goto Begin;
 461         restore_flags(flags);
 462         return;
 463 }
 464
 465 void
 466 mode_2bs0(struct BCState *bcs, int mode, int bc)
 467 {
 468         struct IsdnCardState *cs = bcs->cs;
 469
 470         if (cs->debug & L1_DEB_HSCX)
 471                 debugl1(cs, "HFCD bchannel mode %d bchan %d/%d",
 472                         mode, bc, bcs->channel);
 473         bcs->mode = mode;
 474         bcs->channel = bc;
 475         switch (mode) {
 476                 case (L1_MODE_NULL):
 477                         if (bc) {
 478                                 cs->hw.hfcD.conn |= 0x18;
 479                                 cs->hw.hfcD.sctrl &= ~SCTRL_B2_ENA;
 480                         } else {
 481                                 cs->hw.hfcD.conn |= 0x3;
 482                                 cs->hw.hfcD.sctrl &= ~SCTRL_B1_ENA;
 483                         }
 484                         break;
 485                 case (L1_MODE_TRANS):
 486                         if (bc) {
 487                                 cs->hw.hfcD.ctmt |= 2;
 488                                 cs->hw.hfcD.conn &= ~0x18;
 489                                 cs->hw.hfcD.sctrl |= SCTRL_B2_ENA;
 490                         } else {
 491                                 cs->hw.hfcD.ctmt |= 1;
 492                                 cs->hw.hfcD.conn &= ~0x3;
 493                                 cs->hw.hfcD.sctrl |= SCTRL_B1_ENA;
 494                         }
 495                         break;
 496                 case (L1_MODE_HDLC):
 497                         if (bc) {
 498                                 cs->hw.hfcD.ctmt &= ~2;
 499                                 cs->hw.hfcD.conn &= ~0x18;
 500                                 cs->hw.hfcD.sctrl |= SCTRL_B2_ENA;
 501                         } else {
 502                                 cs->hw.hfcD.ctmt &= ~1;
 503                                 cs->hw.hfcD.conn &= ~0x3;
 504                                 cs->hw.hfcD.sctrl |= SCTRL_B1_ENA;
 505                         }
 506                         break;
 507         }
 508         WriteReg(cs, HFCD_DATA, HFCD_SCTRL, cs->hw.hfcD.sctrl);
 509         WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt);
 510         WriteReg(cs, HFCD_DATA, HFCD_CONN, cs->hw.hfcD.conn);
 511 }
 512
 513 static void
 514 hfc_l2l1(struct PStack *st, int pr, void *arg)
 515 {
 516         struct sk_buff *skb = arg;
 517         long flags;
 518
 519         switch (pr) {
 520                 case (PH_DATA | REQUEST):
 521                         save_flags(flags);
 522                         cli();
 523                         if (st->l1.bcs->tx_skb) {
 524                                 skb_queue_tail(&st->l1.bcs->squeue, skb);
 525                                 restore_flags(flags);
 526                         } else {
 527                                 st->l1.bcs->tx_skb = skb;
 528 /*                              test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
 529 */                              st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
 530                                 restore_flags(flags);
 531                         }
 532                         break;
 533                 case (PH_PULL | INDICATION):
 534                         if (st->l1.bcs->tx_skb) {
 535                                 printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n");
 536                                 break;
 537                         }
 538                         save_flags(flags);
 539                         cli();
 540 /*                      test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
 541 */                      st->l1.bcs->tx_skb = skb;
 542                         st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
 543                         restore_flags(flags);
 544                         break;
 545                 case (PH_PULL | REQUEST):
 546                         if (!st->l1.bcs->tx_skb) {
 547                                 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 548                                 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
 549                         } else
 550                                 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 551                         break;
 552                 case (PH_ACTIVATE | REQUEST):
 553                         test_and_set_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
 554                         mode_2bs0(st->l1.bcs, st->l1.mode, st->l1.bc);
 555                         l1_msg_b(st, pr, arg);
 556                         break;
 557                 case (PH_DEACTIVATE | REQUEST):
 558                         l1_msg_b(st, pr, arg);
 559                         break;
 560                 case (PH_DEACTIVATE | CONFIRM):
 561                         test_and_clear_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
 562                         test_and_clear_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
 563                         mode_2bs0(st->l1.bcs, 0, st->l1.bc);
 564                         st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
 565                         break;
 566         }
 567 }
 568
 569 void
 570 close_2bs0(struct BCState *bcs)
 571 {
 572         mode_2bs0(bcs, 0, bcs->channel);
 573         if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
 574                 skb_queue_purge(&bcs->rqueue);
 575                 skb_queue_purge(&bcs->squeue);
 576                 if (bcs->tx_skb) {
 577                         dev_kfree_skb_any(bcs->tx_skb);
 578                         bcs->tx_skb = NULL;
 579                         test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
 580                 }
 581         }
 582 }
 583
 584 static int
 585 open_hfcstate(struct IsdnCardState *cs, struct BCState *bcs)
 586 {
 587         if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
 588                 skb_queue_head_init(&bcs->rqueue);
 589                 skb_queue_head_init(&bcs->squeue);
 590         }
 591         bcs->tx_skb = NULL;
 592         test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
 593         bcs->event = 0;
 594         bcs->tx_cnt = 0;
 595         return (0);
 596 }
 597
 598 int
 599 setstack_2b(struct PStack *st, struct BCState *bcs)
 600 {
 601         bcs->channel = st->l1.bc;
 602         if (open_hfcstate(st->l1.hardware, bcs))
 603                 return (-1);
 604         st->l1.bcs = bcs;
 605         st->l2.l2l1 = hfc_l2l1;
 606         setstack_manager(st);
 607         bcs->st = st;
 608         setstack_l1_B(st);
 609         return (0);
 610 }
 611
 612 static void
 613 hfcd_bh(struct IsdnCardState *cs)
 614 {
 615 /*      struct PStack *stptr;
 616 */
 617         if (!cs)
 618                 return;
 619         if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
 620                 switch (cs->dc.hfcd.ph_state) {
 621                         case (0):
 622                                 l1_msg(cs, HW_RESET | INDICATION, NULL);
 623                                 break;
 624                         case (3):
 625                                 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
 626                                 break;
 627                         case (8):
 628                                 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
 629                                 break;
 630                         case (6):
 631                                 l1_msg(cs, HW_INFO2 | INDICATION, NULL);
 632                                 break;
 633                         case (7):
 634                                 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
 635                                 break;
 636                         default:
 637                                 break;
 638                 }
 639         }
 640         if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
 641                 DChannel_proc_rcv(cs);
 642         if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
 643                 DChannel_proc_xmt(cs);
 644 }
 645
 646 void
 647 sched_event_D(struct IsdnCardState *cs, int event)
 648 {
 649         test_and_set_bit(event, &cs->event);
 650         queue_task(&cs->tqueue, &tq_immediate);
 651         mark_bh(IMMEDIATE_BH);
 652 }
 653
 654 static
 655 int receive_dmsg(struct IsdnCardState *cs)
 656 {
 657         struct sk_buff *skb;
 658         long flags;
 659         int idx;
 660         int rcnt, z1, z2;
 661         u_char stat, cip, f1, f2;
 662         int chksum;
 663         int count=5;
 664         u_char *ptr;
 665
 666         save_flags(flags);
 667         cli();
 668         if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 669                 debugl1(cs, "rec_dmsg blocked");
 670                 restore_flags(flags);
 671                 return(1);
 672         }
 673         SelFiFo(cs, 4 | HFCD_REC);
 674         cip = HFCD_FIFO | HFCD_F1 | HFCD_REC;
 675         WaitNoBusy(cs);
 676         f1 = cs->readisac(cs, cip) & 0xf;
 677         cip = HFCD_FIFO | HFCD_F2 | HFCD_REC;
 678         WaitNoBusy(cs);
 679         f2 = cs->readisac(cs, cip) & 0xf;
 680         while ((f1 != f2) && count--) {
 681                 z1 = ReadZReg(cs, HFCD_FIFO | HFCD_Z1 | HFCD_REC);
 682                 z2 = ReadZReg(cs, HFCD_FIFO | HFCD_Z2 | HFCD_REC);
 683                 rcnt = z1 - z2;
 684                 if (rcnt < 0)
 685                         rcnt += cs->hw.hfcD.dfifosize;
 686                 rcnt++;
 687                 if (cs->debug & L1_DEB_ISAC)
 688                         debugl1(cs, "hfcd recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)",
 689                                 f1, f2, z1, z2, rcnt);
 690                 sti();
 691                 idx = 0;
 692                 cip = HFCD_FIFO | HFCD_FIFO_OUT | HFCD_REC;
 693                 if (rcnt > MAX_DFRAME_LEN + 3) {
 694                         if (cs->debug & L1_DEB_WARN)
 695                                 debugl1(cs, "empty_fifo d: incoming packet too large");
 696                         while (idx < rcnt) {
 697                                 cli();
 698                                 if (!(WaitNoBusy(cs)))
 699                                         break;
 700                                 ReadReg(cs, HFCD_DATA_NODEB, cip);
 701                                 sti();
 702                                 idx++;
 703                         }
 704                 } else if (rcnt < 4) {
 705                         if (cs->debug & L1_DEB_WARN)
 706                                 debugl1(cs, "empty_fifo d: incoming packet too small");
 707                         cli();
 708                         while ((idx++ < rcnt) && WaitNoBusy(cs))
 709                                 ReadReg(cs, HFCD_DATA_NODEB, cip);
 710                 } else if ((skb = dev_alloc_skb(rcnt - 3))) {
 711                         ptr = skb_put(skb, rcnt - 3);
 712                         while (idx < (rcnt - 3)) {
 713                                 cli();
 714                                 if (!(WaitNoBusy(cs)))
 715                                         break;
 716                                 *ptr = ReadReg(cs, HFCD_DATA_NODEB, cip);
 717                                 sti();
 718                                 idx++;
 719                                 ptr++;
 720                         }
 721                         if (idx != (rcnt - 3)) {
 722                                 sti();
 723                                 debugl1(cs, "RFIFO D BUSY error");
 724                                 printk(KERN_WARNING "HFC DFIFO channel BUSY Error\n");
 725                                 dev_kfree_skb_irq(skb);
 726                                 skb = NULL;
 727 #ifdef ERROR_STATISTIC
 728                                 cs->err_rx++;
 729 #endif
 730                         } else {
 731                                 cli();
 732                                 WaitNoBusy(cs);
 733                                 chksum = (ReadReg(cs, HFCD_DATA, cip) << 8);
 734                                 WaitNoBusy(cs);
 735                                 chksum += ReadReg(cs, HFCD_DATA, cip);
 736                                 WaitNoBusy(cs);
 737                                 stat = ReadReg(cs, HFCD_DATA, cip);
 738                                 sti();
 739                                 if (cs->debug & L1_DEB_ISAC)
 740                                         debugl1(cs, "empty_dfifo chksum %x stat %x",
 741                                                 chksum, stat);
 742                                 if (stat) {
 743                                         debugl1(cs, "FIFO CRC error");
 744                                         dev_kfree_skb_irq(skb);
 745                                         skb = NULL;
 746 #ifdef ERROR_STATISTIC
 747                                         cs->err_crc++;
 748 #endif
 749                                 } else {
 750                                         skb_queue_tail(&cs->rq, skb);
 751                                         sched_event_D(cs, D_RCVBUFREADY);
 752                                 }
 753                         }
 754                 } else
 755                         printk(KERN_WARNING "HFC: D receive out of memory\n");
 756                 sti();
 757                 WaitForBusy(cs);
 758                 cip = HFCD_FIFO | HFCD_F2_INC | HFCD_REC;
 759                 cli();
 760                 WaitNoBusy(cs);
 761                 stat = ReadReg(cs, HFCD_DATA, cip);
 762                 sti();
 763                 WaitForBusy(cs);
 764                 cip = HFCD_FIFO | HFCD_F2 | HFCD_REC;
 765                 cli();
 766                 WaitNoBusy(cs);
 767                 f2 = cs->readisac(cs, cip) & 0xf;
 768         }
 769         test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 770         restore_flags(flags);
 771         return(1);
 772 }
 773
 774 static void
 775 hfc_fill_dfifo(struct IsdnCardState *cs)
 776 {
 777         long flags;
 778         int idx, fcnt;
 779         int count;
 780         u_char cip;
 781
 782         if (!cs->tx_skb)
 783                 return;
 784         if (cs->tx_skb->len <= 0)
 785                 return;
 786
 787         save_flags(flags);
 788         cli();
 789         SelFiFo(cs, 4 | HFCD_SEND);
 790         cip = HFCD_FIFO | HFCD_F1 | HFCD_SEND;
 791         WaitNoBusy(cs);
 792         cs->hw.hfcD.f1 = ReadReg(cs, HFCD_DATA, cip) & 0xf;
 793         WaitNoBusy(cs);
 794         cip = HFCD_FIFO | HFCD_F2 | HFCD_SEND;
 795         cs->hw.hfcD.f2 = ReadReg(cs, HFCD_DATA, cip) & 0xf;
 796         cs->hw.hfcD.send[cs->hw.hfcD.f1] = ReadZReg(cs, HFCD_FIFO | HFCD_Z1 | HFCD_SEND);
 797         sti();
 798         if (cs->debug & L1_DEB_ISAC)
 799                 debugl1(cs, "hfc_fill_Dfifo f1(%d) f2(%d) z1(%x)",
 800                         cs->hw.hfcD.f1, cs->hw.hfcD.f2,
 801                         cs->hw.hfcD.send[cs->hw.hfcD.f1]);
 802         fcnt = cs->hw.hfcD.f1 - cs->hw.hfcD.f2;
 803         if (fcnt < 0)
 804                 fcnt += 16;
 805         if (fcnt > 14) {
 806                 if (cs->debug & L1_DEB_HSCX)
 807                         debugl1(cs, "hfc_fill_Dfifo more as 14 frames");
 808                 restore_flags(flags);
 809                 return;
 810         }
 811         count = GetFreeFifoBytes_D(cs);
 812         if (cs->debug & L1_DEB_ISAC)
 813                 debugl1(cs, "hfc_fill_Dfifo count(%ld/%d)",
 814                         cs->tx_skb->len, count);
 815         if (count < cs->tx_skb->len) {
 816                 if (cs->debug & L1_DEB_ISAC)
 817                         debugl1(cs, "hfc_fill_Dfifo no fifo mem");
 818                 restore_flags(flags);
 819                 return;
 820         }
 821         cip = HFCD_FIFO | HFCD_FIFO_IN | HFCD_SEND;
 822         idx = 0;
 823         cli();
 824         WaitForBusy(cs);
 825         WaitNoBusy(cs);
 826         WriteReg(cs, HFCD_DATA_NODEB, cip, cs->tx_skb->data[idx++]);
 827         while (idx < cs->tx_skb->len) {
 828                 cli();
 829                 if (!(WaitNoBusy(cs)))
 830                         break;
 831                 WriteReg(cs, HFCD_DATA_NODEB, cip, cs->tx_skb->data[idx]);
 832                 sti();
 833                 idx++;
 834         }
 835         if (idx != cs->tx_skb->len) {
 836                 sti();
 837                 debugl1(cs, "DFIFO Send BUSY error");
 838                 printk(KERN_WARNING "HFC S DFIFO channel BUSY Error\n");
 839         }
 840         WaitForBusy(cs);
 841         cli();
 842         WaitNoBusy(cs);
 843         ReadReg(cs, HFCD_DATA, HFCD_FIFO | HFCD_F1_INC | HFCD_SEND);
 844         dev_kfree_skb_any(cs->tx_skb);
 845         cs->tx_skb = NULL;
 846         sti();
 847         WaitForBusy(cs);
 848         restore_flags(flags);
 849         return;
 850 }
 851
 852 static
 853 struct BCState *Sel_BCS(struct IsdnCardState *cs, int channel)
 854 {
 855         if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
 856                 return(&cs->bcs[0]);
 857         else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
 858                 return(&cs->bcs[1]);
 859         else
 860                 return(NULL);
 861 }
 862
 863 void
 864 hfc2bds0_interrupt(struct IsdnCardState *cs, u_char val)
 865 {
 866         u_char exval;
 867         struct BCState *bcs;
 868         int count=15;
 869         long flags;
 870
 871         if (cs->debug & L1_DEB_ISAC)
 872                 debugl1(cs, "HFCD irq %x %s", val,
 873                         test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ?
 874                         "locked" : "unlocked");
 875         val &= cs->hw.hfcD.int_m1;
 876         if (val & 0x40) { /* TE state machine irq */
 877                 exval = cs->readisac(cs, HFCD_STATES) & 0xf;
 878                 if (cs->debug & L1_DEB_ISAC)
 879                         debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcd.ph_state,
 880                                 exval);
 881                 cs->dc.hfcd.ph_state = exval;
 882                 sched_event_D(cs, D_L1STATECHANGE);
 883                 val &= ~0x40;
 884         }
 885         while (val) {
 886                 save_flags(flags);
 887                 cli();
 888                 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 889                         cs->hw.hfcD.int_s1 |= val;
 890                         restore_flags(flags);
 891                         return;
 892                 }
 893                 if (cs->hw.hfcD.int_s1 & 0x18) {
 894                         exval = val;
 895                         val =  cs->hw.hfcD.int_s1;
 896                         cs->hw.hfcD.int_s1 = exval;
 897                 }
 898                 if (val & 0x08) {
 899                         if (!(bcs=Sel_BCS(cs, 0))) {
 900                                 if (cs->debug)
 901                                         debugl1(cs, "hfcd spurious 0x08 IRQ");
 902                         } else
 903                                 main_rec_2bds0(bcs);
 904                 }
 905                 if (val & 0x10) {
 906                         if (!(bcs=Sel_BCS(cs, 1))) {
 907                                 if (cs->debug)
 908                                         debugl1(cs, "hfcd spurious 0x10 IRQ");
 909                         } else
 910                                 main_rec_2bds0(bcs);
 911                 }
 912                 if (val & 0x01) {
 913                         if (!(bcs=Sel_BCS(cs, 0))) {
 914                                 if (cs->debug)
 915                                         debugl1(cs, "hfcd spurious 0x01 IRQ");
 916                         } else {
 917                                 if (bcs->tx_skb) {
 918                                         if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 919                                                 hfc_fill_fifo(bcs);
 920                                                 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 921                                         } else
 922                                                 debugl1(cs,"fill_data %d blocked", bcs->channel);
 923                                 } else {
 924                                         if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
 925                                                 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 926                                                         hfc_fill_fifo(bcs);
 927                                                         test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 928                                                 } else
 929                                                         debugl1(cs,"fill_data %d blocked", bcs->channel);
 930                                         } else {
 931                                                 hfc_sched_event(bcs, B_XMTBUFREADY);
 932                                         }
 933                                 }
 934                         }
 935                 }
 936                 if (val & 0x02) {
 937                         if (!(bcs=Sel_BCS(cs, 1))) {
 938                                 if (cs->debug)
 939                                         debugl1(cs, "hfcd spurious 0x02 IRQ");
 940                         } else {
 941                                 if (bcs->tx_skb) {
 942                                         if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 943                                                 hfc_fill_fifo(bcs);
 944                                                 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 945                                         } else
 946                                                 debugl1(cs,"fill_data %d blocked", bcs->channel);
 947                                 } else {
 948                                         if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
 949                                                 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 950                                                         hfc_fill_fifo(bcs);
 951                                                         test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 952                                                 } else
 953                                                         debugl1(cs,"fill_data %d blocked", bcs->channel);
 954                                         } else {
 955                                                 hfc_sched_event(bcs, B_XMTBUFREADY);
 956                                         }
 957                                 }
 958                         }
 959                 }
 960                 if (val & 0x20) {       /* receive dframe */
 961                         receive_dmsg(cs);
 962                 }
 963                 if (val & 0x04) {       /* dframe transmitted */
 964                         if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
 965                                 del_timer(&cs->dbusytimer);
 966                         if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
 967                                 sched_event_D(cs, D_CLEARBUSY);
 968                         if (cs->tx_skb) {
 969                                 if (cs->tx_skb->len) {
 970                                         if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 971                                                 hfc_fill_dfifo(cs);
 972                                                 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 973                                         } else {
 974                                                 debugl1(cs, "hfc_fill_dfifo irq blocked");
 975                                         }
 976                                         goto afterXPR;
 977                                 } else {
 978                                         dev_kfree_skb_irq(cs->tx_skb);
 979                                         cs->tx_cnt = 0;
 980                                         cs->tx_skb = NULL;
 981                                 }
 982                         }
 983                         if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
 984                                 cs->tx_cnt = 0;
 985                                 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 986                                         hfc_fill_dfifo(cs);
 987                                         test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 988                                 } else {
 989                                         debugl1(cs, "hfc_fill_dfifo irq blocked");
 990                                 }
 991                         } else
 992                                 sched_event_D(cs, D_XMTBUFREADY);
 993                 }
 994       afterXPR:
 995                 if (cs->hw.hfcD.int_s1 && count--) {
 996                         val = cs->hw.hfcD.int_s1;
 997                         cs->hw.hfcD.int_s1 = 0;
 998                         if (cs->debug & L1_DEB_ISAC)
 999                                 debugl1(cs, "HFCD irq %x loop %d", val, 15-count);
1000                 } else
1001                         val = 0;
1002                 restore_flags(flags);
1003         }
1004 }
1005
1006 static void
1007 HFCD_l1hw(struct PStack *st, int pr, void *arg)
1008 {
1009         struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
1010         struct sk_buff *skb = arg;
1011
1012         switch (pr) {
1013                 case (PH_DATA | REQUEST):
1014                         if (cs->debug & DEB_DLOG_HEX)
1015                                 LogFrame(cs, skb->data, skb->len);
1016                         if (cs->debug & DEB_DLOG_VERBOSE)
1017                                 dlogframe(cs, skb, 0);
1018                         if (cs->tx_skb) {
1019                                 skb_queue_tail(&cs->sq, skb);
1020 #ifdef L2FRAME_DEBUG            /* psa */
1021                                 if (cs->debug & L1_DEB_LAPD)
1022                                         Logl2Frame(cs, skb, "PH_DATA Queued", 0);
1023 #endif
1024                         } else {
1025                                 cs->tx_skb = skb;
1026                                 cs->tx_cnt = 0;
1027 #ifdef L2FRAME_DEBUG            /* psa */
1028                                 if (cs->debug & L1_DEB_LAPD)
1029                                         Logl2Frame(cs, skb, "PH_DATA", 0);
1030 #endif
1031                                 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1032                                         hfc_fill_dfifo(cs);
1033                                         test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1034                                 } else
1035                                         debugl1(cs, "hfc_fill_dfifo blocked");
1036
1037                         }
1038                         break;
1039                 case (PH_PULL | INDICATION):
1040                         if (cs->tx_skb) {
1041                                 if (cs->debug & L1_DEB_WARN)
1042                                         debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
1043                                 skb_queue_tail(&cs->sq, skb);
1044                                 break;
1045                         }
1046                         if (cs->debug & DEB_DLOG_HEX)
1047                                 LogFrame(cs, skb->data, skb->len);
1048                         if (cs->debug & DEB_DLOG_VERBOSE)
1049                                 dlogframe(cs, skb, 0);
1050                         cs->tx_skb = skb;
1051                         cs->tx_cnt = 0;
1052 #ifdef L2FRAME_DEBUG            /* psa */
1053                         if (cs->debug & L1_DEB_LAPD)
1054                                 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
1055 #endif
1056                         if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1057                                 hfc_fill_dfifo(cs);
1058                                 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1059                         } else
1060                                 debugl1(cs, "hfc_fill_dfifo blocked");
1061                         break;
1062                 case (PH_PULL | REQUEST):
1063 #ifdef L2FRAME_DEBUG            /* psa */
1064                         if (cs->debug & L1_DEB_LAPD)
1065                                 debugl1(cs, "-> PH_REQUEST_PULL");
1066 #endif
1067                         if (!cs->tx_skb) {
1068                                 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1069                                 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1070                         } else
1071                                 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1072                         break;
1073                 case (HW_RESET | REQUEST):
1074                         cs->writeisac(cs, HFCD_STATES, HFCD_LOAD_STATE | 3); /* HFC ST 3 */
1075                         udelay(6);
1076                         cs->writeisac(cs, HFCD_STATES, 3); /* HFC ST 2 */
1077                         cs->hw.hfcD.mst_m |= HFCD_MASTER;
1078                         cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m);
1079                         cs->writeisac(cs, HFCD_STATES, HFCD_ACTIVATE | HFCD_DO_ACTION);
1080                         l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
1081                         break;
1082                 case (HW_ENABLE | REQUEST):
1083                         cs->writeisac(cs, HFCD_STATES, HFCD_ACTIVATE | HFCD_DO_ACTION);
1084                         break;
1085                 case (HW_DEACTIVATE | REQUEST):
1086                         cs->hw.hfcD.mst_m &= ~HFCD_MASTER;
1087                         cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m);
1088                         break;
1089                 case (HW_INFO3 | REQUEST):
1090                         cs->hw.hfcD.mst_m |= HFCD_MASTER;
1091                         cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m);
1092                         break;
1093                 default:
1094                         if (cs->debug & L1_DEB_WARN)
1095                                 debugl1(cs, "hfcd_l1hw unknown pr %4x", pr);
1096                         break;
1097         }
1098 }
1099
1100 void
1101 setstack_hfcd(struct PStack *st, struct IsdnCardState *cs)
1102 {
1103         st->l1.l1hw = HFCD_l1hw;
1104 }
1105
1106 static void
1107 hfc_dbusy_timer(struct IsdnCardState *cs)
1108 {
1109 }
1110
1111 unsigned int __init
1112 *init_send_hfcd(int cnt)
1113 {
1114         int i, *send;
1115
1116         if (!(send = kmalloc(cnt * sizeof(unsigned int), GFP_ATOMIC))) {
1117                 printk(KERN_WARNING
1118                        "HiSax: No memory for hfcd.send\n");
1119                 return(NULL);
1120         }
1121         for (i = 0; i < cnt; i++)
1122                 send[i] = 0x1fff;
1123         return(send);
1124 }
1125
1126 void __init
1127 init2bds0(struct IsdnCardState *cs)
1128 {
1129         cs->setstack_d = setstack_hfcd;
1130         cs->dbusytimer.function = (void *) hfc_dbusy_timer;
1131         cs->dbusytimer.data = (long) cs;
1132         init_timer(&cs->dbusytimer);
1133         cs->tqueue.routine = (void *) (void *) hfcd_bh;
1134         if (!cs->hw.hfcD.send)
1135                 cs->hw.hfcD.send = init_send_hfcd(16);
1136         if (!cs->bcs[0].hw.hfc.send)
1137                 cs->bcs[0].hw.hfc.send = init_send_hfcd(32);
1138         if (!cs->bcs[1].hw.hfc.send)
1139                 cs->bcs[1].hw.hfc.send = init_send_hfcd(32);
1140         cs->BC_Send_Data = &hfc_send_data;
1141         cs->bcs[0].BC_SetStack = setstack_2b;
1142         cs->bcs[1].BC_SetStack = setstack_2b;
1143         cs->bcs[0].BC_Close = close_2bs0;
1144         cs->bcs[1].BC_Close = close_2bs0;
1145         mode_2bs0(cs->bcs, 0, 0);
1146         mode_2bs0(cs->bcs + 1, 0, 1);
1147 }
1148
1149 void
1150 release2bds0(struct IsdnCardState *cs)
1151 {
1152         if (cs->bcs[0].hw.hfc.send) {
1153                 kfree(cs->bcs[0].hw.hfc.send);
1154                 cs->bcs[0].hw.hfc.send = NULL;
1155         }
1156         if (cs->bcs[1].hw.hfc.send) {
1157                 kfree(cs->bcs[1].hw.hfc.send);
1158                 cs->bcs[1].hw.hfc.send = NULL;
1159         }
1160         if (cs->hw.hfcD.send) {
1161                 kfree(cs->hw.hfcD.send);
1162                 cs->hw.hfcD.send = NULL;
1163         }
1164 }