drivers/isdn/hisax/hfc_pci.c

   1 /* $Id: hfc_pci.c,v 1.1.4.1 2001/11/20 14:19:35 kai Exp $
   2  *
   3  * low level driver for CCD´s hfc-pci based cards
   4  *
   5  * Author       Werner Cornelius
   6  *              based on existing driver for CCD hfc ISA cards
   7  * Copyright    by Werner Cornelius  <werner@isdn4linux.de>
   8  *              by Karsten Keil      <keil@isdn4linux.de>
   9  *
  10  * This software may be used and distributed according to the terms
  11  * of the GNU General Public License, incorporated herein by reference.
  12  *
  13  * For changes and modifications please read
  14  * ../../../Documentation/isdn/HiSax.cert
  15  *
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/config.h>
  20 #define __NO_VERSION__
  21 #include "hisax.h"
  22 #include "hfc_pci.h"
  23 #include "isdnl1.h"
  24 #include <linux/pci.h>
  25 #include <linux/interrupt.h>
  26
  27 extern const char *CardType[];
  28
  29 static const char *hfcpci_revision = "$Revision: 1.1.4.1 $";
  30
  31 /* table entry in the PCI devices list */
  32 typedef struct {
  33         int vendor_id;
  34         int device_id;
  35         char *vendor_name;
  36         char *card_name;
  37 } PCI_ENTRY;
  38
  39 #define NT_T1_COUNT     20      /* number of 3.125ms interrupts for G2 timeout */
  40 #define CLKDEL_TE       0x0e    /* CLKDEL in TE mode */
  41 #define CLKDEL_NT       0x6c    /* CLKDEL in NT mode */
  42
  43 static const PCI_ENTRY id_list[] =
  44 {
  45         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_2BD0, "CCD/Billion/Asuscom", "2BD0"},
  46         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B000, "Billion", "B000"},
  47         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B006, "Billion", "B006"},
  48         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B007, "Billion", "B007"},
  49         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B008, "Billion", "B008"},
  50         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B009, "Billion", "B009"},
  51         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00A, "Billion", "B00A"},
  52         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00B, "Billion", "B00B"},
  53         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00C, "Billion", "B00C"},
  54         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B100, "Seyeon", "B100"},
  55         {PCI_VENDOR_ID_ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1, "Abocom/Magitek", "2BD1"},
  56         {PCI_VENDOR_ID_ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675, "Asuscom/Askey", "675"},
  57         {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT, "German telekom", "T-Concept"},
  58         {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_A1T, "German telekom", "A1T"},
  59         {PCI_VENDOR_ID_ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575, "Motorola MC145575", "MC145575"},
  60         {PCI_VENDOR_ID_ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0, "Zoltrix", "2BD0"},
  61         {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E,"Digi International", "Digi DataFire Micro V IOM2 (Europe)"},
  62         {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_E,"Digi International", "Digi DataFire Micro V (Europe)"},
  63         {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A,"Digi International", "Digi DataFire Micro V IOM2 (North America)"},
  64         {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_A,"Digi International", "Digi DataFire Micro V (North America)"},
  65         {0, 0, NULL, NULL},
  66 };
  67
  68
  69 #if CONFIG_PCI
  70
  71 /******************************************/
  72 /* free hardware resources used by driver */
  73 /******************************************/
  74 void
  75 release_io_hfcpci(struct IsdnCardState *cs)
  76 {
  77         unsigned long flags;
  78
  79         printk(KERN_INFO "HiSax: release hfcpci at %p\n",
  80                 cs->hw.hfcpci.pci_io);
  81         save_flags(flags);
  82         cli();
  83         cs->hw.hfcpci.int_m2 = 0;       /* interrupt output off ! */
  84         Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
  85         restore_flags(flags);
  86         Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET);       /* Reset On */
  87         sti();
  88         set_current_state(TASK_UNINTERRUPTIBLE);
  89         schedule_timeout((30 * HZ) / 1000);     /* Timeout 30ms */
  90         Write_hfc(cs, HFCPCI_CIRM, 0);  /* Reset Off */
  91         pcibios_write_config_word(cs->hw.hfcpci.pci_bus, cs->hw.hfcpci.pci_device_fn, PCI_COMMAND, 0);  /* disable memory mapped ports + busmaster */
  92         del_timer(&cs->hw.hfcpci.timer);
  93         kfree(cs->hw.hfcpci.share_start);
  94         cs->hw.hfcpci.share_start = NULL;
  95         iounmap((void *)cs->hw.hfcpci.pci_io);
  96 }
  97
  98 /********************************************************************************/
  99 /* function called to reset the HFC PCI chip. A complete software reset of chip */
 100 /* and fifos is done.                                                           */
 101 /********************************************************************************/
 102 static void
 103 reset_hfcpci(struct IsdnCardState *cs)
 104 {
 105         long flags;
 106
 107         save_flags(flags);
 108         cli();
 109         pcibios_write_config_word(cs->hw.hfcpci.pci_bus, cs->hw.hfcpci.pci_device_fn, PCI_COMMAND, PCI_ENA_MEMIO);      /* enable memory mapped ports, disable busmaster */
 110         cs->hw.hfcpci.int_m2 = 0;       /* interrupt output off ! */
 111         Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
 112
 113         printk(KERN_INFO "HFC_PCI: resetting card\n");
 114         pcibios_write_config_word(cs->hw.hfcpci.pci_bus, cs->hw.hfcpci.pci_device_fn, PCI_COMMAND, PCI_ENA_MEMIO + PCI_ENA_MASTER);     /* enable memory ports + busmaster */
 115         Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET);       /* Reset On */
 116         sti();
 117         set_current_state(TASK_UNINTERRUPTIBLE);
 118         schedule_timeout((30 * HZ) / 1000);     /* Timeout 30ms */
 119         Write_hfc(cs, HFCPCI_CIRM, 0);  /* Reset Off */
 120         set_current_state(TASK_UNINTERRUPTIBLE);
 121         schedule_timeout((20 * HZ) / 1000);     /* Timeout 20ms */
 122         if (Read_hfc(cs, HFCPCI_STATUS) & 2)
 123                 printk(KERN_WARNING "HFC-PCI init bit busy\n");
 124
 125         cs->hw.hfcpci.fifo_en = 0x30;   /* only D fifos enabled */
 126         Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
 127
 128         cs->hw.hfcpci.trm = 0 + HFCPCI_BTRANS_THRESMASK;        /* no echo connect , threshold */
 129         Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
 130
 131         Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_TE); /* ST-Bit delay for TE-Mode */
 132         cs->hw.hfcpci.sctrl_e = HFCPCI_AUTO_AWAKE;
 133         Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e);   /* S/T Auto awake */
 134         cs->hw.hfcpci.bswapped = 0;     /* no exchange */
 135         cs->hw.hfcpci.nt_mode = 0;      /* we are in TE mode */
 136         cs->hw.hfcpci.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
 137         Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
 138
 139         cs->hw.hfcpci.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
 140             HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
 141         Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
 142
 143         /* Clear already pending ints */
 144         if (Read_hfc(cs, HFCPCI_INT_S1));
 145
 146         Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 2);    /* HFC ST 2 */
 147         udelay(10);
 148         Write_hfc(cs, HFCPCI_STATES, 2);        /* HFC ST 2 */
 149         cs->hw.hfcpci.mst_m = HFCPCI_MASTER;    /* HFC Master Mode */
 150
 151         Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
 152         cs->hw.hfcpci.sctrl = 0x40;     /* set tx_lo mode, error in datasheet ! */
 153         Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
 154         cs->hw.hfcpci.sctrl_r = 0;
 155         Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
 156
 157         /* Init GCI/IOM2 in master mode */
 158         /* Slots 0 and 1 are set for B-chan 1 and 2 */
 159         /* D- and monitor/CI channel are not enabled */
 160         /* STIO1 is used as output for data, B1+B2 from ST->IOM+HFC */
 161         /* STIO2 is used as data input, B1+B2 from IOM->ST */
 162         /* ST B-channel send disabled -> continous 1s */
 163         /* The IOM slots are always enabled */
 164         cs->hw.hfcpci.conn = 0x36;      /* set data flow directions */
 165         Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
 166         Write_hfc(cs, HFCPCI_B1_SSL, 0x80);     /* B1-Slot 0 STIO1 out enabled */
 167         Write_hfc(cs, HFCPCI_B2_SSL, 0x81);     /* B2-Slot 1 STIO1 out enabled */
 168         Write_hfc(cs, HFCPCI_B1_RSL, 0x80);     /* B1-Slot 0 STIO2 in enabled */
 169         Write_hfc(cs, HFCPCI_B2_RSL, 0x81);     /* B2-Slot 1 STIO2 in enabled */
 170
 171         /* Finally enable IRQ output */
 172         cs->hw.hfcpci.int_m2 = HFCPCI_IRQ_ENABLE;
 173         Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
 174         if (Read_hfc(cs, HFCPCI_INT_S2));
 175         restore_flags(flags);
 176 }
 177
 178 /***************************************************/
 179 /* Timer function called when kernel timer expires */
 180 /***************************************************/
 181 static void
 182 hfcpci_Timer(struct IsdnCardState *cs)
 183 {
 184         cs->hw.hfcpci.timer.expires = jiffies + 75;
 185         /* WD RESET */
 186 /*      WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcpci.ctmt | 0x80);
 187    add_timer(&cs->hw.hfcpci.timer);
 188  */
 189 }
 190
 191
 192 /*********************************/
 193 /* schedule a new D-channel task */
 194 /*********************************/
 195 static void
 196 sched_event_D_pci(struct IsdnCardState *cs, int event)
 197 {
 198         test_and_set_bit(event, &cs->event);
 199         queue_task(&cs->tqueue, &tq_immediate);
 200         mark_bh(IMMEDIATE_BH);
 201 }
 202
 203 /*********************************/
 204 /* schedule a new b_channel task */
 205 /*********************************/
 206 static void
 207 hfcpci_sched_event(struct BCState *bcs, int event)
 208 {
 209         bcs->event |= 1 << event;
 210         queue_task(&bcs->tqueue, &tq_immediate);
 211         mark_bh(IMMEDIATE_BH);
 212 }
 213
 214 /************************************************/
 215 /* select a b-channel entry matching and active */
 216 /************************************************/
 217 static
 218 struct BCState *
 219 Sel_BCS(struct IsdnCardState *cs, int channel)
 220 {
 221         if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
 222                 return (&cs->bcs[0]);
 223         else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
 224                 return (&cs->bcs[1]);
 225         else
 226                 return (NULL);
 227 }
 228
 229 /***************************************/
 230 /* clear the desired B-channel rx fifo */
 231 /***************************************/
 232 static void hfcpci_clear_fifo_rx(struct IsdnCardState *cs, int fifo)
 233 {       u_char fifo_state;
 234         bzfifo_type *bzr;
 235
 236         if (fifo) {
 237                 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
 238                 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2RX;
 239         } else {
 240                 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1;
 241                 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1RX;
 242         }
 243         if (fifo_state)
 244                 cs->hw.hfcpci.fifo_en ^= fifo_state;
 245         Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
 246         cs->hw.hfcpci.last_bfifo_cnt[fifo] = 0;
 247         bzr->za[MAX_B_FRAMES].z1 = B_FIFO_SIZE + B_SUB_VAL - 1;
 248         bzr->za[MAX_B_FRAMES].z2 = bzr->za[MAX_B_FRAMES].z1;
 249         bzr->f1 = MAX_B_FRAMES;
 250         bzr->f2 = bzr->f1;      /* init F pointers to remain constant */
 251         if (fifo_state)
 252                 cs->hw.hfcpci.fifo_en |= fifo_state;
 253         Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
 254 }
 255
 256 /***************************************/
 257 /* clear the desired B-channel tx fifo */
 258 /***************************************/
 259 static void hfcpci_clear_fifo_tx(struct IsdnCardState *cs, int fifo)
 260 {       u_char fifo_state;
 261         bzfifo_type *bzt;
 262
 263         if (fifo) {
 264                 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2;
 265                 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2TX;
 266         } else {
 267                 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1;
 268                 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1TX;
 269         }
 270         if (fifo_state)
 271                 cs->hw.hfcpci.fifo_en ^= fifo_state;
 272         Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
 273         bzt->za[MAX_B_FRAMES].z1 = B_FIFO_SIZE + B_SUB_VAL - 1;
 274         bzt->za[MAX_B_FRAMES].z2 = bzt->za[MAX_B_FRAMES].z1;
 275         bzt->f1 = MAX_B_FRAMES;
 276         bzt->f2 = bzt->f1;      /* init F pointers to remain constant */
 277         if (fifo_state)
 278                 cs->hw.hfcpci.fifo_en |= fifo_state;
 279         Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
 280 }
 281
 282 /*********************************************/
 283 /* read a complete B-frame out of the buffer */
 284 /*********************************************/
 285 static struct sk_buff
 286 *
 287 hfcpci_empty_fifo(struct BCState *bcs, bzfifo_type * bz, u_char * bdata, int count)
 288 {
 289         u_char *ptr, *ptr1, new_f2;
 290         struct sk_buff *skb;
 291         struct IsdnCardState *cs = bcs->cs;
 292         unsigned long flags;
 293         int total, maxlen, new_z2;
 294         z_type *zp;
 295
 296         save_flags(flags);
 297         sti();
 298         if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
 299                 debugl1(cs, "hfcpci_empty_fifo");
 300         zp = &bz->za[bz->f2];   /* point to Z-Regs */
 301         new_z2 = zp->z2 + count;        /* new position in fifo */
 302         if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
 303                 new_z2 -= B_FIFO_SIZE;  /* buffer wrap */
 304         new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
 305         if ((count > HSCX_BUFMAX + 3) || (count < 4) ||
 306             (*(bdata + (zp->z1 - B_SUB_VAL)))) {
 307                 if (cs->debug & L1_DEB_WARN)
 308                         debugl1(cs, "hfcpci_empty_fifo: incoming packet invalid length %d or crc", count);
 309 #ifdef ERROR_STATISTIC
 310                 bcs->err_inv++;
 311 #endif
 312                 bz->za[new_f2].z2 = new_z2;
 313                 bz->f2 = new_f2;        /* next buffer */
 314                 skb = NULL;
 315         } else if (!(skb = dev_alloc_skb(count - 3)))
 316                 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
 317         else {
 318                 total = count;
 319                 count -= 3;
 320                 ptr = skb_put(skb, count);
 321
 322                 if (zp->z2 + count <= B_FIFO_SIZE + B_SUB_VAL)
 323                         maxlen = count;         /* complete transfer */
 324                 else
 325                         maxlen = B_FIFO_SIZE + B_SUB_VAL - zp->z2;      /* maximum */
 326
 327                 ptr1 = bdata + (zp->z2 - B_SUB_VAL);    /* start of data */
 328                 memcpy(ptr, ptr1, maxlen);      /* copy data */
 329                 count -= maxlen;
 330
 331                 if (count) {    /* rest remaining */
 332                         ptr += maxlen;
 333                         ptr1 = bdata;   /* start of buffer */
 334                         memcpy(ptr, ptr1, count);       /* rest */
 335                 }
 336                 bz->za[new_f2].z2 = new_z2;
 337                 bz->f2 = new_f2;        /* next buffer */
 338
 339         }
 340         restore_flags(flags);
 341         return (skb);
 342 }
 343
 344 /*******************************/
 345 /* D-channel receive procedure */
 346 /*******************************/
 347 static
 348 int
 349 receive_dmsg(struct IsdnCardState *cs)
 350 {
 351         struct sk_buff *skb;
 352         int maxlen;
 353         int rcnt, total;
 354         int count = 5;
 355         u_char *ptr, *ptr1;
 356         dfifo_type *df;
 357         z_type *zp;
 358
 359         df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_rx;
 360         if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 361                 debugl1(cs, "rec_dmsg blocked");
 362                 return (1);
 363         }
 364         while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
 365                 zp = &df->za[df->f2 & D_FREG_MASK];
 366                 rcnt = zp->z1 - zp->z2;
 367                 if (rcnt < 0)
 368                         rcnt += D_FIFO_SIZE;
 369                 rcnt++;
 370                 if (cs->debug & L1_DEB_ISAC)
 371                         debugl1(cs, "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)",
 372                                 df->f1, df->f2, zp->z1, zp->z2, rcnt);
 373
 374                 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
 375                     (df->data[zp->z1])) {
 376                         if (cs->debug & L1_DEB_WARN)
 377                                 debugl1(cs, "empty_fifo hfcpci paket inv. len %d or crc %d", rcnt, df->data[zp->z1]);
 378 #ifdef ERROR_STATISTIC
 379                         cs->err_rx++;
 380 #endif
 381                         df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) | (MAX_D_FRAMES + 1);    /* next buffer */
 382                         df->za[df->f2 & D_FREG_MASK].z2 = (zp->z2 + rcnt) & (D_FIFO_SIZE - 1);
 383                 } else if ((skb = dev_alloc_skb(rcnt - 3))) {
 384                         total = rcnt;
 385                         rcnt -= 3;
 386                         ptr = skb_put(skb, rcnt);
 387
 388                         if (zp->z2 + rcnt <= D_FIFO_SIZE)
 389                                 maxlen = rcnt;  /* complete transfer */
 390                         else
 391                                 maxlen = D_FIFO_SIZE - zp->z2;  /* maximum */
 392
 393                         ptr1 = df->data + zp->z2;       /* start of data */
 394                         memcpy(ptr, ptr1, maxlen);      /* copy data */
 395                         rcnt -= maxlen;
 396
 397                         if (rcnt) {     /* rest remaining */
 398                                 ptr += maxlen;
 399                                 ptr1 = df->data;        /* start of buffer */
 400                                 memcpy(ptr, ptr1, rcnt);        /* rest */
 401                         }
 402                         df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) | (MAX_D_FRAMES + 1);    /* next buffer */
 403                         df->za[df->f2 & D_FREG_MASK].z2 = (zp->z2 + total) & (D_FIFO_SIZE - 1);
 404
 405                         skb_queue_tail(&cs->rq, skb);
 406                         sched_event_D_pci(cs, D_RCVBUFREADY);
 407                 } else
 408                         printk(KERN_WARNING "HFC-PCI: D receive out of memory\n");
 409         }
 410         test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 411         return (1);
 412 }
 413
 414 /*******************************************************************************/
 415 /* check for transparent receive data and read max one threshold size if avail */
 416 /*******************************************************************************/
 417 int
 418 hfcpci_empty_fifo_trans(struct BCState *bcs, bzfifo_type * bz, u_char * bdata)
 419 {
 420         unsigned short *z1r, *z2r;
 421         int new_z2, fcnt, maxlen;
 422         struct sk_buff *skb;
 423         u_char *ptr, *ptr1;
 424
 425         z1r = &bz->za[MAX_B_FRAMES].z1;         /* pointer to z reg */
 426         z2r = z1r + 1;
 427
 428         if (!(fcnt = *z1r - *z2r))
 429                 return (0);     /* no data avail */
 430
 431         if (fcnt <= 0)
 432                 fcnt += B_FIFO_SIZE;    /* bytes actually buffered */
 433         if (fcnt > HFCPCI_BTRANS_THRESHOLD)
 434                 fcnt = HFCPCI_BTRANS_THRESHOLD;         /* limit size */
 435
 436         new_z2 = *z2r + fcnt;   /* new position in fifo */
 437         if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
 438                 new_z2 -= B_FIFO_SIZE;  /* buffer wrap */
 439
 440         if (!(skb = dev_alloc_skb(fcnt)))
 441                 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
 442         else {
 443                 ptr = skb_put(skb, fcnt);
 444                 if (*z2r + fcnt <= B_FIFO_SIZE + B_SUB_VAL)
 445                         maxlen = fcnt;  /* complete transfer */
 446                 else
 447                         maxlen = B_FIFO_SIZE + B_SUB_VAL - *z2r;        /* maximum */
 448
 449                 ptr1 = bdata + (*z2r - B_SUB_VAL);      /* start of data */
 450                 memcpy(ptr, ptr1, maxlen);      /* copy data */
 451                 fcnt -= maxlen;
 452
 453                 if (fcnt) {     /* rest remaining */
 454                         ptr += maxlen;
 455                         ptr1 = bdata;   /* start of buffer */
 456                         memcpy(ptr, ptr1, fcnt);        /* rest */
 457                 }
 458                 cli();
 459                 skb_queue_tail(&bcs->rqueue, skb);
 460                 sti();
 461                 hfcpci_sched_event(bcs, B_RCVBUFREADY);
 462         }
 463
 464         *z2r = new_z2;          /* new position */
 465         return (1);
 466 }                               /* hfcpci_empty_fifo_trans */
 467
 468 /**********************************/
 469 /* B-channel main receive routine */
 470 /**********************************/
 471 void
 472 main_rec_hfcpci(struct BCState *bcs)
 473 {
 474         long flags;
 475         struct IsdnCardState *cs = bcs->cs;
 476         int rcnt, real_fifo;
 477         int receive, count = 5;
 478         struct sk_buff *skb;
 479         bzfifo_type *bz;
 480         u_char *bdata;
 481         z_type *zp;
 482
 483
 484         save_flags(flags);
 485         if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) {
 486                 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
 487                 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2;
 488                 real_fifo = 1;
 489         } else {
 490                 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1;
 491                 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b1;
 492                 real_fifo = 0;
 493         }
 494       Begin:
 495         count--;
 496         cli();
 497         if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 498                 debugl1(cs, "rec_data %d blocked", bcs->channel);
 499                 restore_flags(flags);
 500                 return;
 501         }
 502         sti();
 503         if (bz->f1 != bz->f2) {
 504                 if (cs->debug & L1_DEB_HSCX)
 505                         debugl1(cs, "hfcpci rec %d f1(%d) f2(%d)",
 506                                 bcs->channel, bz->f1, bz->f2);
 507                 zp = &bz->za[bz->f2];
 508
 509                 rcnt = zp->z1 - zp->z2;
 510                 if (rcnt < 0)
 511                         rcnt += B_FIFO_SIZE;
 512                 rcnt++;
 513                 if (cs->debug & L1_DEB_HSCX)
 514                         debugl1(cs, "hfcpci rec %d z1(%x) z2(%x) cnt(%d)",
 515                                 bcs->channel, zp->z1, zp->z2, rcnt);
 516                 if ((skb = hfcpci_empty_fifo(bcs, bz, bdata, rcnt))) {
 517                         cli();
 518                         skb_queue_tail(&bcs->rqueue, skb);
 519                         sti();
 520                         hfcpci_sched_event(bcs, B_RCVBUFREADY);
 521                 }
 522                 rcnt = bz->f1 - bz->f2;
 523                 if (rcnt < 0)
 524                         rcnt += MAX_B_FRAMES + 1;
 525                 if (cs->hw.hfcpci.last_bfifo_cnt[real_fifo] > rcnt + 1) {
 526                         rcnt = 0;
 527                         hfcpci_clear_fifo_rx(cs, real_fifo);
 528                 }
 529                 cs->hw.hfcpci.last_bfifo_cnt[real_fifo] = rcnt;
 530                 if (rcnt > 1)
 531                         receive = 1;
 532                 else
 533                         receive = 0;
 534         } else if (bcs->mode == L1_MODE_TRANS)
 535                 receive = hfcpci_empty_fifo_trans(bcs, bz, bdata);
 536         else
 537                 receive = 0;
 538         test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 539         if (count && receive)
 540                 goto Begin;
 541         restore_flags(flags);
 542         return;
 543 }
 544
 545 /**************************/
 546 /* D-channel send routine */
 547 /**************************/
 548 static void
 549 hfcpci_fill_dfifo(struct IsdnCardState *cs)
 550 {
 551         long flags;
 552         int fcnt;
 553         int count, new_z1, maxlen;
 554         dfifo_type *df;
 555         u_char *src, *dst, new_f1;
 556
 557         if (!cs->tx_skb)
 558                 return;
 559         if (cs->tx_skb->len <= 0)
 560                 return;
 561
 562         df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_tx;
 563
 564         if (cs->debug & L1_DEB_ISAC)
 565                 debugl1(cs, "hfcpci_fill_Dfifo f1(%d) f2(%d) z1(f1)(%x)",
 566                         df->f1, df->f2,
 567                         df->za[df->f1 & D_FREG_MASK].z1);
 568         fcnt = df->f1 - df->f2; /* frame count actually buffered */
 569         if (fcnt < 0)
 570                 fcnt += (MAX_D_FRAMES + 1);     /* if wrap around */
 571         if (fcnt > (MAX_D_FRAMES - 1)) {
 572                 if (cs->debug & L1_DEB_ISAC)
 573                         debugl1(cs, "hfcpci_fill_Dfifo more as 14 frames");
 574 #ifdef ERROR_STATISTIC
 575                 cs->err_tx++;
 576 #endif
 577                 return;
 578         }
 579         /* now determine free bytes in FIFO buffer */
 580         count = df->za[df->f1 & D_FREG_MASK].z2 - df->za[df->f1 & D_FREG_MASK].z1;
 581         if (count <= 0)
 582                 count += D_FIFO_SIZE;   /* count now contains available bytes */
 583
 584         if (cs->debug & L1_DEB_ISAC)
 585                 debugl1(cs, "hfcpci_fill_Dfifo count(%ld/%d)",
 586                         cs->tx_skb->len, count);
 587         if (count < cs->tx_skb->len) {
 588                 if (cs->debug & L1_DEB_ISAC)
 589                         debugl1(cs, "hfcpci_fill_Dfifo no fifo mem");
 590                 return;
 591         }
 592         count = cs->tx_skb->len;        /* get frame len */
 593         new_z1 = (df->za[df->f1 & D_FREG_MASK].z1 + count) & (D_FIFO_SIZE - 1);
 594         new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
 595         src = cs->tx_skb->data; /* source pointer */
 596         dst = df->data + df->za[df->f1 & D_FREG_MASK].z1;
 597         maxlen = D_FIFO_SIZE - df->za[df->f1 & D_FREG_MASK].z1;         /* end fifo */
 598         if (maxlen > count)
 599                 maxlen = count; /* limit size */
 600         memcpy(dst, src, maxlen);       /* first copy */
 601
 602         count -= maxlen;        /* remaining bytes */
 603         if (count) {
 604                 dst = df->data; /* start of buffer */
 605                 src += maxlen;  /* new position */
 606                 memcpy(dst, src, count);
 607         }
 608         save_flags(flags);
 609         cli();
 610         df->za[new_f1 & D_FREG_MASK].z1 = new_z1;       /* for next buffer */
 611         df->za[df->f1 & D_FREG_MASK].z1 = new_z1;       /* new pos actual buffer */
 612         df->f1 = new_f1;        /* next frame */
 613         restore_flags(flags);
 614
 615         dev_kfree_skb_any(cs->tx_skb);
 616         cs->tx_skb = NULL;
 617         return;
 618 }
 619
 620 /**************************/
 621 /* B-channel send routine */
 622 /**************************/
 623 static void
 624 hfcpci_fill_fifo(struct BCState *bcs)
 625 {
 626         struct IsdnCardState *cs = bcs->cs;
 627         unsigned long flags;
 628         int maxlen, fcnt;
 629         int count, new_z1;
 630         bzfifo_type *bz;
 631         u_char *bdata;
 632         u_char new_f1, *src, *dst;
 633         unsigned short *z1t, *z2t;
 634
 635         if (!bcs->tx_skb)
 636                 return;
 637         if (bcs->tx_skb->len <= 0)
 638                 return;
 639
 640         save_flags(flags);
 641         sti();
 642
 643         if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) {
 644                 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2;
 645                 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b2;
 646         } else {
 647                 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1;
 648                 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b1;
 649         }
 650
 651         if (bcs->mode == L1_MODE_TRANS) {
 652                 z1t = &bz->za[MAX_B_FRAMES].z1;
 653                 z2t = z1t + 1;
 654                 if (cs->debug & L1_DEB_HSCX)
 655                         debugl1(cs, "hfcpci_fill_fifo_trans %d z1(%x) z2(%x)",
 656                                 bcs->channel, *z1t, *z2t);
 657                 fcnt = *z2t - *z1t;
 658                 if (fcnt <= 0)
 659                         fcnt += B_FIFO_SIZE;    /* fcnt contains available bytes in fifo */
 660                 fcnt = B_FIFO_SIZE - fcnt;      /* remaining bytes to send */
 661
 662                 while ((fcnt < 2 * HFCPCI_BTRANS_THRESHOLD) && (bcs->tx_skb)) {
 663                         if (bcs->tx_skb->len < B_FIFO_SIZE - fcnt) {
 664                                 /* data is suitable for fifo */
 665                                 count = bcs->tx_skb->len;
 666
 667                                 new_z1 = *z1t + count;  /* new buffer Position */
 668                                 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
 669                                         new_z1 -= B_FIFO_SIZE;  /* buffer wrap */
 670                                 src = bcs->tx_skb->data;        /* source pointer */
 671                                 dst = bdata + (*z1t - B_SUB_VAL);
 672                                 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - *z1t;      /* end of fifo */
 673                                 if (maxlen > count)
 674                                         maxlen = count;         /* limit size */
 675                                 memcpy(dst, src, maxlen);       /* first copy */
 676
 677                                 count -= maxlen;        /* remaining bytes */
 678                                 if (count) {
 679                                         dst = bdata;    /* start of buffer */
 680                                         src += maxlen;  /* new position */
 681                                         memcpy(dst, src, count);
 682                                 }
 683                                 bcs->tx_cnt -= bcs->tx_skb->len;
 684                                 fcnt += bcs->tx_skb->len;
 685                                 *z1t = new_z1;  /* now send data */
 686                         } else if (cs->debug & L1_DEB_HSCX)
 687                                 debugl1(cs, "hfcpci_fill_fifo_trans %d frame length %d discarded",
 688                                         bcs->channel, bcs->tx_skb->len);
 689
 690                         if (bcs->st->lli.l1writewakeup &&
 691                            (PACKET_NOACK != bcs->tx_skb->pkt_type))
 692                                 bcs->st->lli.l1writewakeup(bcs->st, bcs->tx_skb->len);
 693
 694                         dev_kfree_skb_any(bcs->tx_skb);
 695                         cli();
 696                         bcs->tx_skb = skb_dequeue(&bcs->squeue);        /* fetch next data */
 697                         sti();
 698                 }
 699                 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
 700                 restore_flags(flags);
 701                 return;
 702         }
 703         if (cs->debug & L1_DEB_HSCX)
 704                 debugl1(cs, "hfcpci_fill_fifo_hdlc %d f1(%d) f2(%d) z1(f1)(%x)",
 705                         bcs->channel, bz->f1, bz->f2,
 706                         bz->za[bz->f1].z1);
 707
 708         fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
 709         if (fcnt < 0)
 710                 fcnt += (MAX_B_FRAMES + 1);     /* if wrap around */
 711         if (fcnt > (MAX_B_FRAMES - 1)) {
 712                 if (cs->debug & L1_DEB_HSCX)
 713                         debugl1(cs, "hfcpci_fill_Bfifo more as 14 frames");
 714                 restore_flags(flags);
 715                 return;
 716         }
 717         /* now determine free bytes in FIFO buffer */
 718         count = bz->za[bz->f1].z2 - bz->za[bz->f1].z1;
 719         if (count <= 0)
 720                 count += B_FIFO_SIZE;   /* count now contains available bytes */
 721
 722         if (cs->debug & L1_DEB_HSCX)
 723                 debugl1(cs, "hfcpci_fill_fifo %d count(%ld/%d),%lx",
 724                         bcs->channel, bcs->tx_skb->len,
 725                         count, current->state);
 726
 727         if (count < bcs->tx_skb->len) {
 728                 if (cs->debug & L1_DEB_HSCX)
 729                         debugl1(cs, "hfcpci_fill_fifo no fifo mem");
 730                 restore_flags(flags);
 731                 return;
 732         }
 733         count = bcs->tx_skb->len;       /* get frame len */
 734         new_z1 = bz->za[bz->f1].z1 + count;     /* new buffer Position */
 735         if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
 736                 new_z1 -= B_FIFO_SIZE;  /* buffer wrap */
 737
 738         new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
 739         src = bcs->tx_skb->data;        /* source pointer */
 740         dst = bdata + (bz->za[bz->f1].z1 - B_SUB_VAL);
 741         maxlen = (B_FIFO_SIZE + B_SUB_VAL) - bz->za[bz->f1].z1;         /* end fifo */
 742         if (maxlen > count)
 743                 maxlen = count; /* limit size */
 744         memcpy(dst, src, maxlen);       /* first copy */
 745
 746         count -= maxlen;        /* remaining bytes */
 747         if (count) {
 748                 dst = bdata;    /* start of buffer */
 749                 src += maxlen;  /* new position */
 750                 memcpy(dst, src, count);
 751         }
 752         bcs->tx_cnt -= bcs->tx_skb->len;
 753         if (bcs->st->lli.l1writewakeup &&
 754             (PACKET_NOACK != bcs->tx_skb->pkt_type))
 755                 bcs->st->lli.l1writewakeup(bcs->st, bcs->tx_skb->len);
 756
 757         cli();
 758         bz->za[new_f1].z1 = new_z1;     /* for next buffer */
 759         bz->f1 = new_f1;        /* next frame */
 760         restore_flags(flags);
 761
 762         dev_kfree_skb_any(bcs->tx_skb);
 763         bcs->tx_skb = NULL;
 764         test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
 765         return;
 766 }
 767
 768 /**********************************************/
 769 /* D-channel l1 state call for leased NT-mode */
 770 /**********************************************/
 771 static void
 772 dch_nt_l2l1(struct PStack *st, int pr, void *arg)
 773 {
 774         struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
 775
 776         switch (pr) {
 777                 case (PH_DATA | REQUEST):
 778                 case (PH_PULL | REQUEST):
 779                 case (PH_PULL | INDICATION):
 780                         st->l1.l1hw(st, pr, arg);
 781                         break;
 782                 case (PH_ACTIVATE | REQUEST):
 783                         st->l1.l1l2(st, PH_ACTIVATE | CONFIRM, NULL);
 784                         break;
 785                 case (PH_TESTLOOP | REQUEST):
 786                         if (1 & (long) arg)
 787                                 debugl1(cs, "PH_TEST_LOOP B1");
 788                         if (2 & (long) arg)
 789                                 debugl1(cs, "PH_TEST_LOOP B2");
 790                         if (!(3 & (long) arg))
 791                                 debugl1(cs, "PH_TEST_LOOP DISABLED");
 792                         st->l1.l1hw(st, HW_TESTLOOP | REQUEST, arg);
 793                         break;
 794                 default:
 795                         if (cs->debug)
 796                                 debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr);
 797                         break;
 798         }
 799 }
 800
 801
 802
 803 /***********************/
 804 /* set/reset echo mode */
 805 /***********************/
 806 static int
 807 hfcpci_auxcmd(struct IsdnCardState *cs, isdn_ctrl * ic)
 808 {
 809         unsigned long flags;
 810         int i = *(unsigned int *) ic->parm.num;
 811
 812         if ((ic->arg == 98) &&
 813             (!(cs->hw.hfcpci.int_m1 & (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC + HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC)))) {
 814                 save_flags(flags);
 815                 cli();
 816                 Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_NT); /* ST-Bit delay for NT-Mode */
 817                 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 0);    /* HFC ST G0 */
 818                 udelay(10);
 819                 cs->hw.hfcpci.sctrl |= SCTRL_MODE_NT;
 820                 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);       /* set NT-mode */
 821                 udelay(10);
 822                 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 1);    /* HFC ST G1 */
 823                 udelay(10);
 824                 Write_hfc(cs, HFCPCI_STATES, 1 | HFCPCI_ACTIVATE | HFCPCI_DO_ACTION);
 825                 cs->dc.hfcpci.ph_state = 1;
 826                 cs->hw.hfcpci.nt_mode = 1;
 827                 cs->hw.hfcpci.nt_timer = 0;
 828                 cs->stlist->l2.l2l1 = dch_nt_l2l1;
 829                 restore_flags(flags);
 830                 debugl1(cs, "NT mode activated");
 831                 return (0);
 832         }
 833         if ((cs->chanlimit > 1) || (cs->hw.hfcpci.bswapped) ||
 834             (cs->hw.hfcpci.nt_mode) || (ic->arg != 12))
 835                 return (-EINVAL);
 836
 837         save_flags(flags);
 838         cli();
 839         if (i) {
 840                 cs->logecho = 1;
 841                 cs->hw.hfcpci.trm |= 0x20;      /* enable echo chan */
 842                 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_B2REC;
 843                 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2RX;
 844         } else {
 845                 cs->logecho = 0;
 846                 cs->hw.hfcpci.trm &= ~0x20;     /* disable echo chan */
 847                 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_B2REC;
 848                 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2RX;
 849         }
 850         cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA;
 851         cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA;
 852         cs->hw.hfcpci.conn |= 0x10;     /* B2-IOM -> B2-ST */
 853         cs->hw.hfcpci.ctmt &= ~2;
 854         Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
 855         Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
 856         Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
 857         Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
 858         Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
 859         Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
 860         Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
 861         restore_flags(flags);
 862         return (0);
 863 }                               /* hfcpci_auxcmd */
 864
 865 /*****************************/
 866 /* E-channel receive routine */
 867 /*****************************/
 868 static void
 869 receive_emsg(struct IsdnCardState *cs)
 870 {
 871         long flags;
 872         int rcnt;
 873         int receive, count = 5;
 874         bzfifo_type *bz;
 875         u_char *bdata;
 876         z_type *zp;
 877         u_char *ptr, *ptr1, new_f2;
 878         int total, maxlen, new_z2;
 879         u_char e_buffer[256];
 880
 881         save_flags(flags);
 882         bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
 883         bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2;
 884       Begin:
 885         count--;
 886         cli();
 887         if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 888                 debugl1(cs, "echo_rec_data blocked");
 889                 restore_flags(flags);
 890                 return;
 891         }
 892         sti();
 893         if (bz->f1 != bz->f2) {
 894                 if (cs->debug & L1_DEB_ISAC)
 895                         debugl1(cs, "hfcpci e_rec f1(%d) f2(%d)",
 896                                 bz->f1, bz->f2);
 897                 zp = &bz->za[bz->f2];
 898
 899                 rcnt = zp->z1 - zp->z2;
 900                 if (rcnt < 0)
 901                         rcnt += B_FIFO_SIZE;
 902                 rcnt++;
 903                 if (cs->debug & L1_DEB_ISAC)
 904                         debugl1(cs, "hfcpci e_rec z1(%x) z2(%x) cnt(%d)",
 905                                 zp->z1, zp->z2, rcnt);
 906                 new_z2 = zp->z2 + rcnt;         /* new position in fifo */
 907                 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
 908                         new_z2 -= B_FIFO_SIZE;  /* buffer wrap */
 909                 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
 910                 if ((rcnt > 256 + 3) || (count < 4) ||
 911                     (*(bdata + (zp->z1 - B_SUB_VAL)))) {
 912                         if (cs->debug & L1_DEB_WARN)
 913                                 debugl1(cs, "hfcpci_empty_echan: incoming packet invalid length %d or crc", rcnt);
 914                         bz->za[new_f2].z2 = new_z2;
 915                         bz->f2 = new_f2;        /* next buffer */
 916                 } else {
 917                         total = rcnt;
 918                         rcnt -= 3;
 919                         ptr = e_buffer;
 920
 921                         if (zp->z2 <= B_FIFO_SIZE + B_SUB_VAL)
 922                                 maxlen = rcnt;  /* complete transfer */
 923                         else
 924                                 maxlen = B_FIFO_SIZE + B_SUB_VAL - zp->z2;      /* maximum */
 925
 926                         ptr1 = bdata + (zp->z2 - B_SUB_VAL);    /* start of data */
 927                         memcpy(ptr, ptr1, maxlen);      /* copy data */
 928                         rcnt -= maxlen;
 929
 930                         if (rcnt) {     /* rest remaining */
 931                                 ptr += maxlen;
 932                                 ptr1 = bdata;   /* start of buffer */
 933                                 memcpy(ptr, ptr1, rcnt);        /* rest */
 934                         }
 935                         bz->za[new_f2].z2 = new_z2;
 936                         bz->f2 = new_f2;        /* next buffer */
 937                         if (cs->debug & DEB_DLOG_HEX) {
 938                                 ptr = cs->dlog;
 939                                 if ((total - 3) < MAX_DLOG_SPACE / 3 - 10) {
 940                                         *ptr++ = 'E';
 941                                         *ptr++ = 'C';
 942                                         *ptr++ = 'H';
 943                                         *ptr++ = 'O';
 944                                         *ptr++ = ':';
 945                                         ptr += QuickHex(ptr, e_buffer, total - 3);
 946                                         ptr--;
 947                                         *ptr++ = '\n';
 948                                         *ptr = 0;
 949                                         HiSax_putstatus(cs, NULL, cs->dlog);
 950                                 } else
 951                                         HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", total - 3);
 952                         }
 953                 }
 954
 955                 rcnt = bz->f1 - bz->f2;
 956                 if (rcnt < 0)
 957                         rcnt += MAX_B_FRAMES + 1;
 958                 if (rcnt > 1)
 959                         receive = 1;
 960                 else
 961                         receive = 0;
 962         } else
 963                 receive = 0;
 964         test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 965         if (count && receive)
 966                 goto Begin;
 967         restore_flags(flags);
 968         return;
 969 }                               /* receive_emsg */
 970
 971 /*********************/
 972 /* Interrupt handler */
 973 /*********************/
 974 static void
 975 hfcpci_interrupt(int intno, void *dev_id, struct pt_regs *regs)
 976 {
 977         struct IsdnCardState *cs = dev_id;
 978         u_char exval;
 979         struct BCState *bcs;
 980         int count = 15;
 981         long flags;
 982         u_char val, stat;
 983
 984         if (!cs) {
 985                 printk(KERN_WARNING "HFC-PCI: Spurious interrupt!\n");
 986                 return;
 987         }
 988         if (!(cs->hw.hfcpci.int_m2 & 0x08))
 989                 return;         /* not initialised */
 990
 991         if (HFCPCI_ANYINT & (stat = Read_hfc(cs, HFCPCI_STATUS))) {
 992                 val = Read_hfc(cs, HFCPCI_INT_S1);
 993                 if (cs->debug & L1_DEB_ISAC)
 994                         debugl1(cs, "HFC-PCI: stat(%02x) s1(%02x)", stat, val);
 995         } else
 996                 return;
 997
 998         if (cs->debug & L1_DEB_ISAC)
 999                 debugl1(cs, "HFC-PCI irq %x %s", val,
1000                         test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ?
1001                         "locked" : "unlocked");
1002         val &= cs->hw.hfcpci.int_m1;
1003         if (val & 0x40) {       /* state machine irq */
1004                 exval = Read_hfc(cs, HFCPCI_STATES) & 0xf;
1005                 if (cs->debug & L1_DEB_ISAC)
1006                         debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcpci.ph_state,
1007                                 exval);
1008                 cs->dc.hfcpci.ph_state = exval;
1009                 sched_event_D_pci(cs, D_L1STATECHANGE);
1010                 val &= ~0x40;
1011         }
1012         if (val & 0x80) {       /* timer irq */
1013                 if (cs->hw.hfcpci.nt_mode) {
1014                         if ((--cs->hw.hfcpci.nt_timer) < 0)
1015                                 sched_event_D_pci(cs, D_L1STATECHANGE);
1016                 }
1017                 val &= ~0x80;
1018                 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
1019         }
1020         while (val) {
1021                 save_flags(flags);
1022                 cli();
1023                 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1024                         cs->hw.hfcpci.int_s1 |= val;
1025                         restore_flags(flags);
1026                         return;
1027                 }
1028                 if (cs->hw.hfcpci.int_s1 & 0x18) {
1029                         exval = val;
1030                         val = cs->hw.hfcpci.int_s1;
1031                         cs->hw.hfcpci.int_s1 = exval;
1032                 }
1033                 if (val & 0x08) {
1034                         if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) {
1035                                 if (cs->debug)
1036                                         debugl1(cs, "hfcpci spurious 0x08 IRQ");
1037                         } else
1038                                 main_rec_hfcpci(bcs);
1039                 }
1040                 if (val & 0x10) {
1041                         if (cs->logecho)
1042                                 receive_emsg(cs);
1043                         else if (!(bcs = Sel_BCS(cs, 1))) {
1044                                 if (cs->debug)
1045                                         debugl1(cs, "hfcpci spurious 0x10 IRQ");
1046                         } else
1047                                 main_rec_hfcpci(bcs);
1048                 }
1049                 if (val & 0x01) {
1050                         if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) {
1051                                 if (cs->debug)
1052                                         debugl1(cs, "hfcpci spurious 0x01 IRQ");
1053                         } else {
1054                                 if (bcs->tx_skb) {
1055                                         if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1056                                                 hfcpci_fill_fifo(bcs);
1057                                                 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1058                                         } else
1059                                                 debugl1(cs, "fill_data %d blocked", bcs->channel);
1060                                 } else {
1061                                         if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
1062                                                 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1063                                                         hfcpci_fill_fifo(bcs);
1064                                                         test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1065                                                 } else
1066                                                         debugl1(cs, "fill_data %d blocked", bcs->channel);
1067                                         } else {
1068                                                 hfcpci_sched_event(bcs, B_XMTBUFREADY);
1069                                         }
1070                                 }
1071                         }
1072                 }
1073                 if (val & 0x02) {
1074                         if (!(bcs = Sel_BCS(cs, 1))) {
1075                                 if (cs->debug)
1076                                         debugl1(cs, "hfcpci spurious 0x02 IRQ");
1077                         } else {
1078                                 if (bcs->tx_skb) {
1079                                         if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1080                                                 hfcpci_fill_fifo(bcs);
1081                                                 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1082                                         } else
1083                                                 debugl1(cs, "fill_data %d blocked", bcs->channel);
1084                                 } else {
1085                                         if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
1086                                                 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1087                                                         hfcpci_fill_fifo(bcs);
1088                                                         test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1089                                                 } else
1090                                                         debugl1(cs, "fill_data %d blocked", bcs->channel);
1091                                         } else {
1092                                                 hfcpci_sched_event(bcs, B_XMTBUFREADY);
1093                                         }
1094                                 }
1095                         }
1096                 }
1097                 if (val & 0x20) {       /* receive dframe */
1098                         receive_dmsg(cs);
1099                 }
1100                 if (val & 0x04) {       /* dframe transmitted */
1101                         if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
1102                                 del_timer(&cs->dbusytimer);
1103                         if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
1104                                 sched_event_D_pci(cs, D_CLEARBUSY);
1105                         if (cs->tx_skb) {
1106                                 if (cs->tx_skb->len) {
1107                                         if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1108                                                 hfcpci_fill_dfifo(cs);
1109                                                 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1110                                         } else {
1111                                                 debugl1(cs, "hfcpci_fill_dfifo irq blocked");
1112                                         }
1113                                         goto afterXPR;
1114                                 } else {
1115                                         dev_kfree_skb_irq(cs->tx_skb);
1116                                         cs->tx_cnt = 0;
1117                                         cs->tx_skb = NULL;
1118                                 }
1119                         }
1120                         if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
1121                                 cs->tx_cnt = 0;
1122                                 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1123                                         hfcpci_fill_dfifo(cs);
1124                                         test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1125                                 } else {
1126                                         debugl1(cs, "hfcpci_fill_dfifo irq blocked");
1127                                 }
1128                         } else
1129                                 sched_event_D_pci(cs, D_XMTBUFREADY);
1130                 }
1131               afterXPR:
1132                 if (cs->hw.hfcpci.int_s1 && count--) {
1133                         val = cs->hw.hfcpci.int_s1;
1134                         cs->hw.hfcpci.int_s1 = 0;
1135                         if (cs->debug & L1_DEB_ISAC)
1136                                 debugl1(cs, "HFC-PCI irq %x loop %d", val, 15 - count);
1137                 } else
1138                         val = 0;
1139                 restore_flags(flags);
1140         }
1141 }
1142
1143 /********************************************************************/
1144 /* timer callback for D-chan busy resolution. Currently no function */
1145 /********************************************************************/
1146 static void
1147 hfcpci_dbusy_timer(struct IsdnCardState *cs)
1148 {
1149 }
1150
1151 /*************************************/
1152 /* Layer 1 D-channel hardware access */
1153 /*************************************/
1154 static void
1155 HFCPCI_l1hw(struct PStack *st, int pr, void *arg)
1156 {
1157         struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
1158         struct sk_buff *skb = arg;
1159         unsigned long flags;
1160
1161         switch (pr) {
1162                 case (PH_DATA | REQUEST):
1163                         if (cs->debug & DEB_DLOG_HEX)
1164                                 LogFrame(cs, skb->data, skb->len);
1165                         if (cs->debug & DEB_DLOG_VERBOSE)
1166                                 dlogframe(cs, skb, 0);
1167                         if (cs->tx_skb) {
1168                                 skb_queue_tail(&cs->sq, skb);
1169 #ifdef L2FRAME_DEBUG            /* psa */
1170                                 if (cs->debug & L1_DEB_LAPD)
1171                                         Logl2Frame(cs, skb, "PH_DATA Queued", 0);
1172 #endif
1173                         } else {
1174                                 cs->tx_skb = skb;
1175                                 cs->tx_cnt = 0;
1176 #ifdef L2FRAME_DEBUG            /* psa */
1177                                 if (cs->debug & L1_DEB_LAPD)
1178                                         Logl2Frame(cs, skb, "PH_DATA", 0);
1179 #endif
1180                                 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1181                                         hfcpci_fill_dfifo(cs);
1182                                         test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1183                                 } else
1184                                         debugl1(cs, "hfcpci_fill_dfifo blocked");
1185
1186                         }
1187                         break;
1188                 case (PH_PULL | INDICATION):
1189                         if (cs->tx_skb) {
1190                                 if (cs->debug & L1_DEB_WARN)
1191                                         debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
1192                                 skb_queue_tail(&cs->sq, skb);
1193                                 break;
1194                         }
1195                         if (cs->debug & DEB_DLOG_HEX)
1196                                 LogFrame(cs, skb->data, skb->len);
1197                         if (cs->debug & DEB_DLOG_VERBOSE)
1198                                 dlogframe(cs, skb, 0);
1199                         cs->tx_skb = skb;
1200                         cs->tx_cnt = 0;
1201 #ifdef L2FRAME_DEBUG            /* psa */
1202                         if (cs->debug & L1_DEB_LAPD)
1203                                 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
1204 #endif
1205                         if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1206                                 hfcpci_fill_dfifo(cs);
1207                                 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1208                         } else
1209                                 debugl1(cs, "hfcpci_fill_dfifo blocked");
1210                         break;
1211                 case (PH_PULL | REQUEST):
1212 #ifdef L2FRAME_DEBUG            /* psa */
1213                         if (cs->debug & L1_DEB_LAPD)
1214                                 debugl1(cs, "-> PH_REQUEST_PULL");
1215 #endif
1216                         if (!cs->tx_skb) {
1217                                 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1218                                 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1219                         } else
1220                                 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1221                         break;
1222                 case (HW_RESET | REQUEST):
1223                         Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3);    /* HFC ST 3 */
1224                         udelay(6);
1225                         Write_hfc(cs, HFCPCI_STATES, 3);        /* HFC ST 2 */
1226                         cs->hw.hfcpci.mst_m |= HFCPCI_MASTER;
1227                         Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1228                         Write_hfc(cs, HFCPCI_STATES, HFCPCI_ACTIVATE | HFCPCI_DO_ACTION);
1229                         l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
1230                         break;
1231                 case (HW_ENABLE | REQUEST):
1232                         Write_hfc(cs, HFCPCI_STATES, HFCPCI_DO_ACTION);
1233                         break;
1234                 case (HW_DEACTIVATE | REQUEST):
1235                         cs->hw.hfcpci.mst_m &= ~HFCPCI_MASTER;
1236                         Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1237                         break;
1238                 case (HW_INFO3 | REQUEST):
1239                         cs->hw.hfcpci.mst_m |= HFCPCI_MASTER;
1240                         Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1241                         break;
1242                 case (HW_TESTLOOP | REQUEST):
1243                         switch ((int) arg) {
1244                                 case (1):
1245                                         Write_hfc(cs, HFCPCI_B1_SSL, 0x80);     /* tx slot */
1246                                         Write_hfc(cs, HFCPCI_B1_RSL, 0x80);     /* rx slot */
1247                                         save_flags(flags);
1248                                         cli();
1249                                         cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~7) | 1;
1250                                         Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1251                                         restore_flags(flags);
1252                                         break;
1253
1254                                 case (2):
1255                                         Write_hfc(cs, HFCPCI_B2_SSL, 0x81);     /* tx slot */
1256                                         Write_hfc(cs, HFCPCI_B2_RSL, 0x81);     /* rx slot */
1257                                         save_flags(flags);
1258                                         cli();
1259                                         cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~0x38) | 0x08;
1260                                         Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1261                                         restore_flags(flags);
1262                                         break;
1263
1264                                 default:
1265                                         if (cs->debug & L1_DEB_WARN)
1266                                                 debugl1(cs, "hfcpci_l1hw loop invalid %4x", (int) arg);
1267                                         return;
1268                         }
1269                         save_flags(flags);
1270                         cli();
1271                         cs->hw.hfcpci.trm |= 0x80;      /* enable IOM-loop */
1272                         Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
1273                         restore_flags(flags);
1274                         break;
1275                 default:
1276                         if (cs->debug & L1_DEB_WARN)
1277                                 debugl1(cs, "hfcpci_l1hw unknown pr %4x", pr);
1278                         break;
1279         }
1280 }
1281
1282 /***********************************************/
1283 /* called during init setting l1 stack pointer */
1284 /***********************************************/
1285 void
1286 setstack_hfcpci(struct PStack *st, struct IsdnCardState *cs)
1287 {
1288         st->l1.l1hw = HFCPCI_l1hw;
1289 }
1290
1291 /**************************************/
1292 /* send B-channel data if not blocked */
1293 /**************************************/
1294 static void
1295 hfcpci_send_data(struct BCState *bcs)
1296 {
1297         struct IsdnCardState *cs = bcs->cs;
1298
1299         if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1300                 hfcpci_fill_fifo(bcs);
1301                 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1302         } else
1303                 debugl1(cs, "send_data %d blocked", bcs->channel);
1304 }
1305
1306 /***************************************************************/
1307 /* activate/deactivate hardware for selected channels and mode */
1308 /***************************************************************/
1309 void
1310 mode_hfcpci(struct BCState *bcs, int mode, int bc)
1311 {
1312         struct IsdnCardState *cs = bcs->cs;
1313         unsigned long flags;
1314         int fifo2;
1315
1316         if (cs->debug & L1_DEB_HSCX)
1317                 debugl1(cs, "HFCPCI bchannel mode %d bchan %d/%d",
1318                         mode, bc, bcs->channel);
1319         bcs->mode = mode;
1320         bcs->channel = bc;
1321         fifo2 = bc;
1322         save_flags(flags);
1323         cli();
1324         if (cs->chanlimit > 1) {
1325                 cs->hw.hfcpci.bswapped = 0;     /* B1 and B2 normal mode */
1326                 cs->hw.hfcpci.sctrl_e &= ~0x80;
1327         } else {
1328                 if (bc) {
1329                         if (mode != L1_MODE_NULL) {
1330                                 cs->hw.hfcpci.bswapped = 1;     /* B1 and B2 exchanged */
1331                                 cs->hw.hfcpci.sctrl_e |= 0x80;
1332                         } else {
1333                                 cs->hw.hfcpci.bswapped = 0;     /* B1 and B2 normal mode */
1334                                 cs->hw.hfcpci.sctrl_e &= ~0x80;
1335                         }
1336                         fifo2 = 0;
1337                 } else {
1338                         cs->hw.hfcpci.bswapped = 0;     /* B1 and B2 normal mode */
1339                         cs->hw.hfcpci.sctrl_e &= ~0x80;
1340                 }
1341         }
1342         switch (mode) {
1343                 case (L1_MODE_NULL):
1344                         if (bc) {
1345                                 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA;
1346                                 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA;
1347                         } else {
1348                                 cs->hw.hfcpci.sctrl &= ~SCTRL_B1_ENA;
1349                                 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B1_ENA;
1350                         }
1351                         if (fifo2) {
1352                                 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2;
1353                                 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1354                         } else {
1355                                 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1;
1356                                 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1357                         }
1358                         break;
1359                 case (L1_MODE_TRANS):
1360                         hfcpci_clear_fifo_rx(cs, fifo2);
1361                         hfcpci_clear_fifo_tx(cs, fifo2);
1362                         if (bc) {
1363                                 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1364                                 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1365                         } else {
1366                                 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1367                                 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1368                         }
1369                         if (fifo2) {
1370                                 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2;
1371                                 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1372                                 cs->hw.hfcpci.ctmt |= 2;
1373                                 cs->hw.hfcpci.conn &= ~0x18;
1374                         } else {
1375                                 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1;
1376                                 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1377                                 cs->hw.hfcpci.ctmt |= 1;
1378                                 cs->hw.hfcpci.conn &= ~0x03;
1379                         }
1380                         break;
1381                 case (L1_MODE_HDLC):
1382                         hfcpci_clear_fifo_rx(cs, fifo2);
1383                         hfcpci_clear_fifo_tx(cs, fifo2);
1384                         if (bc) {
1385                                 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1386                                 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1387                         } else {
1388                                 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1389                                 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1390                         }
1391                         if (fifo2) {
1392                                 cs->hw.hfcpci.last_bfifo_cnt[1] = 0;
1393                                 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2;
1394                                 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1395                                 cs->hw.hfcpci.ctmt &= ~2;
1396                                 cs->hw.hfcpci.conn &= ~0x18;
1397                         } else {
1398                                 cs->hw.hfcpci.last_bfifo_cnt[0] = 0;
1399                                 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1;
1400                                 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1401                                 cs->hw.hfcpci.ctmt &= ~1;
1402                                 cs->hw.hfcpci.conn &= ~0x03;
1403                         }
1404                         break;
1405                 case (L1_MODE_EXTRN):
1406                         if (bc) {
1407                                 cs->hw.hfcpci.conn |= 0x10;
1408                                 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1409                                 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1410                                 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2;
1411                                 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1412                         } else {
1413                                 cs->hw.hfcpci.conn |= 0x02;
1414                                 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1415                                 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1416                                 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1;
1417                                 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1418                         }
1419                         break;
1420         }
1421         Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e);
1422         Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1423         Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
1424         Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
1425         Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
1426         Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
1427         Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1428         restore_flags(flags);
1429 }
1430
1431 /******************************/
1432 /* Layer2 -> Layer 1 Transfer */
1433 /******************************/
1434 static void
1435 hfcpci_l2l1(struct PStack *st, int pr, void *arg)
1436 {
1437         struct sk_buff *skb = arg;
1438         long flags;
1439
1440         switch (pr) {
1441                 case (PH_DATA | REQUEST):
1442                         save_flags(flags);
1443                         cli();
1444                         if (st->l1.bcs->tx_skb) {
1445                                 skb_queue_tail(&st->l1.bcs->squeue, skb);
1446                                 restore_flags(flags);
1447                         } else {
1448                                 st->l1.bcs->tx_skb = skb;
1449 /*                              test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1450  */ st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
1451                                 restore_flags(flags);
1452                         }
1453                         break;
1454                 case (PH_PULL | INDICATION):
1455                         if (st->l1.bcs->tx_skb) {
1456                                 printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n");
1457                                 break;
1458                         }
1459                         save_flags(flags);
1460                         cli();
1461 /*                      test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1462  */ st->l1.bcs->tx_skb = skb;
1463                         st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
1464                         restore_flags(flags);
1465                         break;
1466                 case (PH_PULL | REQUEST):
1467                         if (!st->l1.bcs->tx_skb) {
1468                                 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1469                                 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1470                         } else
1471                                 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1472                         break;
1473                 case (PH_ACTIVATE | REQUEST):
1474                         test_and_set_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
1475                         mode_hfcpci(st->l1.bcs, st->l1.mode, st->l1.bc);
1476                         l1_msg_b(st, pr, arg);
1477                         break;
1478                 case (PH_DEACTIVATE | REQUEST):
1479                         l1_msg_b(st, pr, arg);
1480                         break;
1481                 case (PH_DEACTIVATE | CONFIRM):
1482                         test_and_clear_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
1483                         test_and_clear_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1484                         mode_hfcpci(st->l1.bcs, 0, st->l1.bc);
1485                         st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
1486                         break;
1487         }
1488 }
1489
1490 /******************************************/
1491 /* deactivate B-channel access and queues */
1492 /******************************************/
1493 static void
1494 close_hfcpci(struct BCState *bcs)
1495 {
1496         mode_hfcpci(bcs, 0, bcs->channel);
1497         if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
1498                 skb_queue_purge(&bcs->rqueue);
1499                 skb_queue_purge(&bcs->squeue);
1500                 if (bcs->tx_skb) {
1501                         dev_kfree_skb_any(bcs->tx_skb);
1502                         bcs->tx_skb = NULL;
1503                         test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1504                 }
1505         }
1506 }
1507
1508 /*************************************/
1509 /* init B-channel queues and control */
1510 /*************************************/
1511 static int
1512 open_hfcpcistate(struct IsdnCardState *cs, struct BCState *bcs)
1513 {
1514         if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
1515                 skb_queue_head_init(&bcs->rqueue);
1516                 skb_queue_head_init(&bcs->squeue);
1517         }
1518         bcs->tx_skb = NULL;
1519         test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1520         bcs->event = 0;
1521         bcs->tx_cnt = 0;
1522         return (0);
1523 }
1524
1525 /*********************************/
1526 /* inits the stack for B-channel */
1527 /*********************************/
1528 static int
1529 setstack_2b(struct PStack *st, struct BCState *bcs)
1530 {
1531         bcs->channel = st->l1.bc;
1532         if (open_hfcpcistate(st->l1.hardware, bcs))
1533                 return (-1);
1534         st->l1.bcs = bcs;
1535         st->l2.l2l1 = hfcpci_l2l1;
1536         setstack_manager(st);
1537         bcs->st = st;
1538         setstack_l1_B(st);
1539         return (0);
1540 }
1541
1542 /***************************/
1543 /* handle L1 state changes */
1544 /***************************/
1545 static void
1546 hfcpci_bh(struct IsdnCardState *cs)
1547 {
1548         unsigned long flags;
1549 /*      struct PStack *stptr;
1550  */
1551         if (!cs)
1552                 return;
1553         if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
1554                 if (!cs->hw.hfcpci.nt_mode)
1555                         switch (cs->dc.hfcpci.ph_state) {
1556                                 case (0):
1557                                         l1_msg(cs, HW_RESET | INDICATION, NULL);
1558                                         break;
1559                                 case (3):
1560                                         l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
1561                                         break;
1562                                 case (8):
1563                                         l1_msg(cs, HW_RSYNC | INDICATION, NULL);
1564                                         break;
1565                                 case (6):
1566                                         l1_msg(cs, HW_INFO2 | INDICATION, NULL);
1567                                         break;
1568                                 case (7):
1569                                         l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
1570                                         break;
1571                                 default:
1572                                         break;
1573                 } else {
1574                         switch (cs->dc.hfcpci.ph_state) {
1575                                 case (2):
1576                                         save_flags(flags);
1577                                         cli();
1578                                         if (cs->hw.hfcpci.nt_timer < 0) {
1579                                                 cs->hw.hfcpci.nt_timer = 0;
1580                                                 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1581                                                 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1582                                                 /* Clear already pending ints */
1583                                                 if (Read_hfc(cs, HFCPCI_INT_S1));
1584
1585                                                 Write_hfc(cs, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
1586                                                 udelay(10);
1587                                                 Write_hfc(cs, HFCPCI_STATES, 4);
1588                                                 cs->dc.hfcpci.ph_state = 4;
1589                                         } else {
1590                                                 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_TIMER;
1591                                                 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1592                                                 cs->hw.hfcpci.ctmt &= ~HFCPCI_AUTO_TIMER;
1593                                                 cs->hw.hfcpci.ctmt |= HFCPCI_TIM3_125;
1594                                                 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
1595                                                 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
1596                                                 cs->hw.hfcpci.nt_timer = NT_T1_COUNT;
1597                                                 Write_hfc(cs, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);      /* allow G2 -> G3 transition */
1598                                         }
1599                                         restore_flags(flags);
1600                                         break;
1601                                 case (1):
1602                                 case (3):
1603                                 case (4):
1604                                         save_flags(flags);
1605                                         cli();
1606                                         cs->hw.hfcpci.nt_timer = 0;
1607                                         cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1608                                         Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1609                                         restore_flags(flags);
1610                                         break;
1611                                 default:
1612                                         break;
1613                         }
1614                 }
1615         }
1616         if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
1617                 DChannel_proc_rcv(cs);
1618         if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
1619                 DChannel_proc_xmt(cs);
1620 }
1621
1622
1623 /********************************/
1624 /* called for card init message */
1625 /********************************/
1626 void __init
1627 inithfcpci(struct IsdnCardState *cs)
1628 {
1629         cs->setstack_d = setstack_hfcpci;
1630         cs->dbusytimer.function = (void *) hfcpci_dbusy_timer;
1631         cs->dbusytimer.data = (long) cs;
1632         init_timer(&cs->dbusytimer);
1633         cs->tqueue.routine = (void *) (void *) hfcpci_bh;
1634         cs->BC_Send_Data = &hfcpci_send_data;
1635         cs->bcs[0].BC_SetStack = setstack_2b;
1636         cs->bcs[1].BC_SetStack = setstack_2b;
1637         cs->bcs[0].BC_Close = close_hfcpci;
1638         cs->bcs[1].BC_Close = close_hfcpci;
1639         mode_hfcpci(cs->bcs, 0, 0);
1640         mode_hfcpci(cs->bcs + 1, 0, 1);
1641 }
1642
1643
1644
1645 /*******************************************/
1646 /* handle card messages from control layer */
1647 /*******************************************/
1648 static int
1649 hfcpci_card_msg(struct IsdnCardState *cs, int mt, void *arg)
1650 {
1651         long flags;
1652
1653         if (cs->debug & L1_DEB_ISAC)
1654                 debugl1(cs, "HFCPCI: card_msg %x", mt);
1655         switch (mt) {
1656                 case CARD_RESET:
1657                         reset_hfcpci(cs);
1658                         return (0);
1659                 case CARD_RELEASE:
1660                         release_io_hfcpci(cs);
1661                         return (0);
1662                 case CARD_INIT:
1663                         inithfcpci(cs);
1664                         save_flags(flags);
1665                         sti();
1666                         set_current_state(TASK_UNINTERRUPTIBLE);
1667                         schedule_timeout((80 * HZ) / 1000);     /* Timeout 80ms */
1668                         /* now switch timer interrupt off */
1669                         cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1670                         Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1671                         /* reinit mode reg */
1672                         Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1673                         restore_flags(flags);
1674                         return (0);
1675                 case CARD_TEST:
1676                         return (0);
1677         }
1678         return (0);
1679 }
1680
1681
1682 /* this variable is used as card index when more than one cards are present */
1683 static struct pci_dev *dev_hfcpci __initdata = NULL;
1684
1685 #endif                          /* CONFIG_PCI */
1686
1687 int __init
1688 setup_hfcpci(struct IsdnCard *card)
1689 {
1690         struct IsdnCardState *cs = card->cs;
1691         char tmp[64];
1692         int i;
1693         struct pci_dev *tmp_hfcpci = NULL;
1694
1695 #ifdef __BIG_ENDIAN
1696 #error "not running on big endian machines now"
1697 #endif
1698         strcpy(tmp, hfcpci_revision);
1699         printk(KERN_INFO "HiSax: HFC-PCI driver Rev. %s\n", HiSax_getrev(tmp));
1700 #if CONFIG_PCI
1701         cs->hw.hfcpci.int_s1 = 0;
1702         cs->dc.hfcpci.ph_state = 0;
1703         cs->hw.hfcpci.fifo = 255;
1704         if (cs->typ == ISDN_CTYPE_HFC_PCI) {
1705                 i = 0;
1706                 while (id_list[i].vendor_id) {
1707                         tmp_hfcpci = pci_find_device(id_list[i].vendor_id,
1708                                                      id_list[i].device_id,
1709                                                      dev_hfcpci);
1710                         i++;
1711                         if (tmp_hfcpci) {
1712                                 if (pci_enable_device(tmp_hfcpci))
1713                                         continue;
1714                                 pci_set_master(tmp_hfcpci);
1715                                 if ((card->para[0]) && (card->para[0] != (tmp_hfcpci->resource[ 0].start & PCI_BASE_ADDRESS_IO_MASK)))
1716                                         continue;
1717                                 else
1718                                         break;
1719                         }
1720                 }
1721
1722                 if (tmp_hfcpci) {
1723                         i--;
1724                         dev_hfcpci = tmp_hfcpci;        /* old device */
1725                         cs->hw.hfcpci.pci_bus = dev_hfcpci->bus->number;
1726                         cs->hw.hfcpci.pci_device_fn = dev_hfcpci->devfn;
1727                         cs->irq = dev_hfcpci->irq;
1728                         if (!cs->irq) {
1729                                 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
1730                                 return (0);
1731                         }
1732                         cs->hw.hfcpci.pci_io = (char *) dev_hfcpci->resource[ 1].start;
1733                         printk(KERN_INFO "HiSax: HFC-PCI card manufacturer: %s card name: %s\n", id_list[i].vendor_name, id_list[i].card_name);
1734                 } else {
1735                         printk(KERN_WARNING "HFC-PCI: No PCI card found\n");
1736                         return (0);
1737                 }
1738                 if (!cs->hw.hfcpci.pci_io) {
1739                         printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
1740                         return (0);
1741                 }
1742                 /* Allocate memory for FIFOS */
1743                 /* Because the HFC-PCI needs a 32K physical alignment, we */
1744                 /* need to allocate the double mem and align the address */
1745                 if (!(cs->hw.hfcpci.share_start = kmalloc(65536, GFP_KERNEL))) {
1746                         printk(KERN_WARNING "HFC-PCI: Error allocating memory for FIFO!\n");
1747                         return 0;
1748                 }
1749                 cs->hw.hfcpci.fifos = (void *)
1750                     (((ulong) cs->hw.hfcpci.share_start) & ~0x7FFF) + 0x8000;
1751                 pcibios_write_config_dword(cs->hw.hfcpci.pci_bus,
1752                                        cs->hw.hfcpci.pci_device_fn, 0x80,
1753                                (u_int) virt_to_bus(cs->hw.hfcpci.fifos));
1754                 cs->hw.hfcpci.pci_io = ioremap((ulong) cs->hw.hfcpci.pci_io, 256);
1755                 printk(KERN_INFO
1756                        "HFC-PCI: defined at mem %#x fifo %#x(%#x) IRQ %d HZ %d\n",
1757                        (u_int) cs->hw.hfcpci.pci_io,
1758                        (u_int) cs->hw.hfcpci.fifos,
1759                        (u_int) virt_to_bus(cs->hw.hfcpci.fifos),
1760                        cs->irq, HZ);
1761                 pcibios_write_config_word(cs->hw.hfcpci.pci_bus, cs->hw.hfcpci.pci_device_fn, PCI_COMMAND, PCI_ENA_MEMIO);      /* enable memory mapped ports, disable busmaster */
1762                 cs->hw.hfcpci.int_m2 = 0;       /* disable alle interrupts */
1763                 cs->hw.hfcpci.int_m1 = 0;
1764                 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1765                 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
1766                 /* At this point the needed PCI config is done */
1767                 /* fifos are still not enabled */
1768         } else
1769                 return (0);     /* no valid card type */
1770
1771
1772         cs->readisac = NULL;
1773         cs->writeisac = NULL;
1774         cs->readisacfifo = NULL;
1775         cs->writeisacfifo = NULL;
1776         cs->BC_Read_Reg = NULL;
1777         cs->BC_Write_Reg = NULL;
1778         cs->irq_func = &hfcpci_interrupt;
1779         cs->irq_flags |= SA_SHIRQ;
1780
1781         cs->hw.hfcpci.timer.function = (void *) hfcpci_Timer;
1782         cs->hw.hfcpci.timer.data = (long) cs;
1783         init_timer(&cs->hw.hfcpci.timer);
1784
1785         reset_hfcpci(cs);
1786         cs->cardmsg = &hfcpci_card_msg;
1787         cs->auxcmd = &hfcpci_auxcmd;
1788         return (1);
1789 #else
1790         printk(KERN_WARNING "HFC-PCI: NO_PCI_BIOS\n");
1791         return (0);
1792 #endif                          /* CONFIG_PCI */
1793 }