1 /* $Id: jade.c,v 1.1.4.1 2001/11/20 14:19:36 kai Exp $
3 * JADE stuff (derived from original hscx.c)
5 * Author Roland Klabunde
6 * Copyright by Roland Klabunde <R.Klabunde@Berkom.de>
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
14 #define __NO_VERSION__
15 #include <linux/init.h>
20 #include <linux/interrupt.h>
24 JadeVersion(struct IsdnCardState *cs, char *s)
28 cs->BC_Write_Reg(cs, -1, 0x50, 0x19);
32 ver = cs->BC_Read_Reg(cs, -1, 0x60);
37 printk(KERN_INFO "%s JADE version not obtainable\n", s);
41 /* Wait for the JADE */
44 ver = cs->BC_Read_Reg(cs, -1, 0x60);
45 printk(KERN_INFO "%s JADE version: %d\n", s, ver);
49 /* Write to indirect accessible jade register set */
51 jade_write_indirect(struct IsdnCardState *cs, u_char reg, u_char value)
59 cs->BC_Write_Reg(cs, -1, COMM_JADE+1, value);
60 /* Say JADE we wanna write indirect reg 'reg' */
61 cs->BC_Write_Reg(cs, -1, COMM_JADE, reg);
63 /* Wait for RDY goes high */
66 ret = cs->BC_Read_Reg(cs, -1, COMM_JADE);
73 printk(KERN_INFO "Can not see ready bit from JADE DSP (reg=0x%X, value=0x%X)\n", reg, value);
83 modejade(struct BCState *bcs, int mode, int bc)
85 struct IsdnCardState *cs = bcs->cs;
86 int jade = bcs->hw.hscx.hscx;
88 if (cs->debug & L1_DEB_HSCX) {
90 sprintf(tmp, "jade %c mode %d ichan %d",
91 'A' + jade, mode, bc);
97 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (mode == L1_MODE_TRANS ? jadeMODE_TMO:0x00));
98 cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR0, (jadeCCR0_PU|jadeCCR0_ITF));
99 cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR1, 0x00);
101 jade_write_indirect(cs, jade_HDLC1SERRXPATH, 0x08);
102 jade_write_indirect(cs, jade_HDLC2SERRXPATH, 0x08);
103 jade_write_indirect(cs, jade_HDLC1SERTXPATH, 0x00);
104 jade_write_indirect(cs, jade_HDLC2SERTXPATH, 0x00);
106 cs->BC_Write_Reg(cs, jade, jade_HDLC_XCCR, 0x07);
107 cs->BC_Write_Reg(cs, jade, jade_HDLC_RCCR, 0x07);
110 cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x00);
111 cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x00);
113 cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x04);
114 cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x04);
118 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, jadeMODE_TMO);
120 case (L1_MODE_TRANS):
121 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_TMO|jadeMODE_RAC|jadeMODE_XAC));
124 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_RAC|jadeMODE_XAC));
128 cs->BC_Write_Reg(cs, jade, jade_HDLC_RCMD, (jadeRCMD_RRES|jadeRCMD_RMC));
129 cs->BC_Write_Reg(cs, jade, jade_HDLC_XCMD, jadeXCMD_XRES);
131 cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0xF8);
135 cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0x00);
139 jade_sched_event(struct BCState *bcs, int event)
141 bcs->event |= 1 << event;
142 queue_task(&bcs->tqueue, &tq_immediate);
143 mark_bh(IMMEDIATE_BH);
147 jade_l2l1(struct PStack *st, int pr, void *arg)
149 struct sk_buff *skb = arg;
153 case (PH_DATA | REQUEST):
156 if (st->l1.bcs->tx_skb) {
157 skb_queue_tail(&st->l1.bcs->squeue, skb);
158 restore_flags(flags);
160 st->l1.bcs->tx_skb = skb;
161 test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
162 st->l1.bcs->hw.hscx.count = 0;
163 restore_flags(flags);
164 st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
167 case (PH_PULL | INDICATION):
168 if (st->l1.bcs->tx_skb) {
169 printk(KERN_WARNING "jade_l2l1: this shouldn't happen\n");
172 test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
173 st->l1.bcs->tx_skb = skb;
174 st->l1.bcs->hw.hscx.count = 0;
175 st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
177 case (PH_PULL | REQUEST):
178 if (!st->l1.bcs->tx_skb) {
179 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
180 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
182 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
184 case (PH_ACTIVATE | REQUEST):
185 test_and_set_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
186 modejade(st->l1.bcs, st->l1.mode, st->l1.bc);
187 l1_msg_b(st, pr, arg);
189 case (PH_DEACTIVATE | REQUEST):
190 l1_msg_b(st, pr, arg);
192 case (PH_DEACTIVATE | CONFIRM):
193 test_and_clear_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
194 test_and_clear_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
195 modejade(st->l1.bcs, 0, st->l1.bc);
196 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
202 close_jadestate(struct BCState *bcs)
204 modejade(bcs, 0, bcs->channel);
205 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
206 if (bcs->hw.hscx.rcvbuf) {
207 kfree(bcs->hw.hscx.rcvbuf);
208 bcs->hw.hscx.rcvbuf = NULL;
214 skb_queue_purge(&bcs->rqueue);
215 skb_queue_purge(&bcs->squeue);
217 dev_kfree_skb_any(bcs->tx_skb);
219 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
225 open_jadestate(struct IsdnCardState *cs, struct BCState *bcs)
227 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
228 if (!(bcs->hw.hscx.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
230 "HiSax: No memory for hscx.rcvbuf\n");
231 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
234 if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
236 "HiSax: No memory for bcs->blog\n");
237 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
238 kfree(bcs->hw.hscx.rcvbuf);
239 bcs->hw.hscx.rcvbuf = NULL;
242 skb_queue_head_init(&bcs->rqueue);
243 skb_queue_head_init(&bcs->squeue);
246 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
248 bcs->hw.hscx.rcvidx = 0;
255 setstack_jade(struct PStack *st, struct BCState *bcs)
257 bcs->channel = st->l1.bc;
258 if (open_jadestate(st->l1.hardware, bcs))
261 st->l2.l2l1 = jade_l2l1;
262 setstack_manager(st);
269 clear_pending_jade_ints(struct IsdnCardState *cs)
274 cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0x00);
275 cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0x00);
277 val = cs->BC_Read_Reg(cs, 1, jade_HDLC_ISR);
278 sprintf(tmp, "jade B ISTA %x", val);
280 val = cs->BC_Read_Reg(cs, 0, jade_HDLC_ISR);
281 sprintf(tmp, "jade A ISTA %x", val);
283 val = cs->BC_Read_Reg(cs, 1, jade_HDLC_STAR);
284 sprintf(tmp, "jade B STAR %x", val);
286 val = cs->BC_Read_Reg(cs, 0, jade_HDLC_STAR);
287 sprintf(tmp, "jade A STAR %x", val);
290 cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0xF8);
291 cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0xF8);
295 initjade(struct IsdnCardState *cs)
297 cs->bcs[0].BC_SetStack = setstack_jade;
298 cs->bcs[1].BC_SetStack = setstack_jade;
299 cs->bcs[0].BC_Close = close_jadestate;
300 cs->bcs[1].BC_Close = close_jadestate;
301 cs->bcs[0].hw.hscx.hscx = 0;
302 cs->bcs[1].hw.hscx.hscx = 1;
304 /* Stop DSP audio tx/rx */
305 jade_write_indirect(cs, 0x11, 0x0f);
306 jade_write_indirect(cs, 0x17, 0x2f);
308 /* Transparent Mode, RxTx inactive, No Test, No RFS/TFS */
309 cs->BC_Write_Reg(cs, 0, jade_HDLC_MODE, jadeMODE_TMO);
310 cs->BC_Write_Reg(cs, 1, jade_HDLC_MODE, jadeMODE_TMO);
311 /* Power down, 1-Idle, RxTx least significant bit first */
312 cs->BC_Write_Reg(cs, 0, jade_HDLC_CCR0, 0x00);
313 cs->BC_Write_Reg(cs, 1, jade_HDLC_CCR0, 0x00);
314 /* Mask all interrupts */
315 cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0x00);
316 cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0x00);
317 /* Setup host access to hdlc controller */
318 jade_write_indirect(cs, jade_HDLCCNTRACCESS, (jadeINDIRECT_HAH1|jadeINDIRECT_HAH2));
319 /* Unmask HDLC int (donĀ“t forget DSP int later on)*/
320 cs->BC_Write_Reg(cs, -1,jade_INT, (jadeINT_HDLC1|jadeINT_HDLC2));
322 /* once again TRANSPARENT */
323 modejade(cs->bcs, 0, 0);
324 modejade(cs->bcs + 1, 0, 0);