drivers/mtd/maps/nettel.c

   1 /****************************************************************************/
   2
   3 /*
   4  *      nettel.c -- mappings for NETtel/SecureEdge/SnapGear (x86) boards.
   5  *
   6  *      (C) Copyright 2000-2001, Greg Ungerer (gerg@snapgear.com)
   7  *      (C) Copyright 2001-2002, SnapGear (www.snapgear.com)
   8  *
   9  *      $Id: nettel.c,v 1.1 2002/08/08 06:30:13 gerg Exp $
  10  */
  11
  12 /****************************************************************************/
  13
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/types.h>
  17 #include <linux/kernel.h>
  18 #include <linux/mtd/mtd.h>
  19 #include <linux/mtd/map.h>
  20 #include <linux/mtd/partitions.h>
  21 #include <linux/mtd/cfi.h>
  22 #include <linux/reboot.h>
  23 #include <asm/io.h>
  24
  25 /****************************************************************************/
  26
  27 #define INTEL_BUSWIDTH          1
  28 #define AMD_WINDOW_MAXSIZE      0x00200000
  29 #define AMD_BUSWIDTH            1
  30
  31 /*
  32  *      PAR masks and shifts, assuming 64K pages.
  33  */
  34 #define SC520_PAR_ADDR_MASK     0x00003fff
  35 #define SC520_PAR_ADDR_SHIFT    16
  36 #define SC520_PAR_TO_ADDR(par) \
  37         (((par)&SC520_PAR_ADDR_MASK) << SC520_PAR_ADDR_SHIFT)
  38
  39 #define SC520_PAR_SIZE_MASK     0x01ffc000
  40 #define SC520_PAR_SIZE_SHIFT    2
  41 #define SC520_PAR_TO_SIZE(par) \
  42         ((((par)&SC520_PAR_SIZE_MASK) << SC520_PAR_SIZE_SHIFT) + (64*1024))
  43
  44 #define SC520_PAR(cs, addr, size) \
  45         ((cs) | \
  46         ((((size)-(64*1024)) >> SC520_PAR_SIZE_SHIFT) & SC520_PAR_SIZE_MASK) | \
  47         (((addr) >> SC520_PAR_ADDR_SHIFT) & SC520_PAR_ADDR_MASK))
  48
  49 #define SC520_PAR_BOOTCS        0x8a000000
  50 #define SC520_PAR_ROMCS1        0xaa000000
  51 #define SC520_PAR_ROMCS2        0xca000000      /* Cache disabled, 64K page */
  52
  53 static void *nettel_mmcrp = NULL;
  54
  55 #ifdef CONFIG_MTD_CFI_INTELEXT
  56 static struct mtd_info *intel_mtd;
  57 #endif
  58 static struct mtd_info *amd_mtd;
  59
  60 /****************************************************************************/
  61
  62 static __u8 nettel_read8(struct map_info *map, unsigned long ofs)
  63 {
  64         return(readb(map->map_priv_1 + ofs));
  65 }
  66
  67 static __u16 nettel_read16(struct map_info *map, unsigned long ofs)
  68 {
  69         return(readw(map->map_priv_1 + ofs));
  70 }
  71
  72 static __u32 nettel_read32(struct map_info *map, unsigned long ofs)
  73 {
  74         return(readl(map->map_priv_1 + ofs));
  75 }
  76
  77 static void nettel_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
  78 {
  79         memcpy_fromio(to, map->map_priv_1 + from, len);
  80 }
  81
  82 static void nettel_write8(struct map_info *map, __u8 d, unsigned long adr)
  83 {
  84         writeb(d, map->map_priv_1 + adr);
  85 }
  86
  87 static void nettel_write16(struct map_info *map, __u16 d, unsigned long adr)
  88 {
  89         writew(d, map->map_priv_1 + adr);
  90 }
  91
  92 static void nettel_write32(struct map_info *map, __u32 d, unsigned long adr)
  93 {
  94         writel(d, map->map_priv_1 + adr);
  95 }
  96
  97 static void nettel_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
  98 {
  99         memcpy_toio(map->map_priv_1 + to, from, len);
 100 }
 101
 102 /****************************************************************************/
 103
 104 #ifdef CONFIG_MTD_CFI_INTELEXT
 105 static struct map_info nettel_intel_map = {
 106         name: "SnapGear Intel",
 107         size: 0,
 108         buswidth: INTEL_BUSWIDTH,
 109         read8: nettel_read8,
 110         read16: nettel_read16,
 111         read32: nettel_read32,
 112         copy_from: nettel_copy_from,
 113         write8: nettel_write8,
 114         write16: nettel_write16,
 115         write32: nettel_write32,
 116         copy_to: nettel_copy_to
 117 };
 118
 119 static struct mtd_partition nettel_intel_partitions[] = {
 120         {
 121                 name: "SnapGear kernel",
 122                 offset: 0,
 123                 size: 0x000e0000
 124         },
 125         {
 126                 name: "SnapGear filesystem",
 127                 offset: 0x00100000,
 128         },
 129         {
 130                 name: "SnapGear config",
 131                 offset: 0x000e0000,
 132                 size: 0x00020000
 133         },
 134         {
 135                 name: "SnapGear Intel",
 136                 offset: 0
 137         },
 138         {
 139                 name: "SnapGear BIOS Config",
 140                 offset: 0x007e0000,
 141                 size: 0x00020000
 142         },
 143         {
 144                 name: "SnapGear BIOS",
 145                 offset: 0x007e0000,
 146                 size: 0x00020000
 147         },
 148 };
 149 #endif
 150
 151 static struct map_info nettel_amd_map = {
 152         name: "SnapGear AMD",
 153         size: AMD_WINDOW_MAXSIZE,
 154         buswidth: AMD_BUSWIDTH,
 155         read8: nettel_read8,
 156         read16: nettel_read16,
 157         read32: nettel_read32,
 158         copy_from: nettel_copy_from,
 159         write8: nettel_write8,
 160         write16: nettel_write16,
 161         write32: nettel_write32,
 162         copy_to: nettel_copy_to
 163 };
 164
 165 static struct mtd_partition nettel_amd_partitions[] = {
 166         {
 167                 name: "SnapGear BIOS config",
 168                 offset: 0x000e0000,
 169                 size: 0x00010000
 170         },
 171         {
 172                 name: "SnapGear BIOS",
 173                 offset: 0x000f0000,
 174                 size: 0x00010000
 175         },
 176         {
 177                 name: "SnapGear AMD",
 178                 offset: 0
 179         },
 180         {
 181                 name: "SnapGear high BIOS",
 182                 offset: 0x001f0000,
 183                 size: 0x00010000
 184         }
 185 };
 186
 187 #define NUM_AMD_PARTITIONS \
 188         (sizeof(nettel_amd_partitions)/sizeof(nettel_amd_partitions[0]))
 189
 190 /****************************************************************************/
 191
 192 #ifdef CONFIG_MTD_CFI_INTELEXT
 193
 194 /*
 195  *      Set the Intel flash back to read mode since some old boot
 196  *      loaders don't.
 197  */
 198 static int nettel_reboot_notifier(struct notifier_block *nb, unsigned long val, void *v)
 199 {
 200         struct cfi_private *cfi = nettel_intel_map.fldrv_priv;
 201         unsigned long b;
 202
 203         /* Make sure all FLASH chips are put back into read mode */
 204         for (b = 0; (b < nettel_intel_partitions[3].size); b += 0x100000) {
 205                 cfi_send_gen_cmd(0xff, 0x55, b, &nettel_intel_map, cfi,
 206                         cfi->device_type, NULL);
 207         }
 208         return(NOTIFY_OK);
 209 }
 210
 211 static struct notifier_block nettel_notifier_block = {
 212         nettel_reboot_notifier, NULL, 0
 213 };
 214
 215 /*
 216  *      Erase the configuration file system.
 217  *      Used to support the software reset button.
 218  */
 219 static void nettel_erasecallback(struct erase_info *done)
 220 {
 221         wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv;
 222         wake_up(wait_q);
 223 }
 224
 225 static struct erase_info nettel_erase;
 226
 227 int nettel_eraseconfig(void)
 228 {
 229         struct mtd_info *mtd;
 230         DECLARE_WAITQUEUE(wait, current);
 231         wait_queue_head_t wait_q;
 232         int ret;
 233
 234         init_waitqueue_head(&wait_q);
 235         mtd = get_mtd_device(NULL, 2);
 236         if (mtd) {
 237                 nettel_erase.mtd = mtd;
 238                 nettel_erase.callback = nettel_erasecallback;
 239                 nettel_erase.callback = 0;
 240                 nettel_erase.addr = 0;
 241                 nettel_erase.len = mtd->size;
 242                 nettel_erase.priv = (u_long) &wait_q;
 243                 nettel_erase.priv = 0;
 244
 245                 set_current_state(TASK_INTERRUPTIBLE);
 246                 add_wait_queue(&wait_q, &wait);
 247
 248                 ret = MTD_ERASE(mtd, &nettel_erase);
 249                 if (ret) {
 250                         set_current_state(TASK_RUNNING);
 251                         remove_wait_queue(&wait_q, &wait);
 252                         put_mtd_device(mtd);
 253                         return(ret);
 254                 }
 255
 256                 schedule();  /* Wait for erase to finish. */
 257                 remove_wait_queue(&wait_q, &wait);
 258
 259                 put_mtd_device(mtd);
 260         }
 261
 262         return(0);
 263 }
 264
 265 #else
 266
 267 int nettel_eraseconfig(void)
 268 {
 269         return(0);
 270 }
 271
 272 #endif
 273
 274 /****************************************************************************/
 275
 276 int __init nettel_init(void)
 277 {
 278         volatile unsigned long *amdpar;
 279         unsigned long amdaddr, maxsize;
 280         int num_amd_partitions=0;
 281 #ifdef CONFIG_MTD_CFI_INTELEXT
 282         volatile unsigned long *intel0par, *intel1par;
 283         unsigned long orig_bootcspar, orig_romcs1par;
 284         unsigned long intel0addr, intel0size;
 285         unsigned long intel1addr, intel1size;
 286         int intelboot, intel0cs, intel1cs;
 287         int num_intel_partitions;
 288 #endif
 289         int rc = 0;
 290
 291         nettel_mmcrp = (void *) ioremap_nocache(0xfffef000, 4096);
 292         if (nettel_mmcrp == NULL) {
 293                 printk("SNAPGEAR: failed to disable MMCR cache??\n");
 294                 return(-EIO);
 295         }
 296
 297         /* Set CPU clock to be 33.000MHz */
 298         *((unsigned char *) (nettel_mmcrp + 0xc64)) = 0x01;
 299
 300         amdpar = (volatile unsigned long *) (nettel_mmcrp + 0xc4);
 301
 302 #ifdef CONFIG_MTD_CFI_INTELEXT
 303         intelboot = 0;
 304         intel0cs = SC520_PAR_ROMCS1;
 305         intel0par = (volatile unsigned long *) (nettel_mmcrp + 0xc0);
 306         intel1cs = SC520_PAR_ROMCS2;
 307         intel1par = (volatile unsigned long *) (nettel_mmcrp + 0xbc);
 308
 309         /*
 310          *      Save the CS settings then ensure ROMCS1 and ROMCS2 are off,
 311          *      otherwise they might clash with where we try to map BOOTCS.
 312          */
 313         orig_bootcspar = *amdpar;
 314         orig_romcs1par = *intel0par;
 315         *intel0par = 0;
 316         *intel1par = 0;
 317 #endif
 318
 319         /*
 320          *      The first thing to do is determine if we have a separate
 321          *      boot FLASH device. Typically this is a small (1 to 2MB)
 322          *      AMD FLASH part. It seems that device size is about the
 323          *      only way to tell if this is the case...
 324          */
 325         amdaddr = 0x20000000;
 326         maxsize = AMD_WINDOW_MAXSIZE;
 327
 328         *amdpar = SC520_PAR(SC520_PAR_BOOTCS, amdaddr, maxsize);
 329         __asm__ ("wbinvd");
 330
 331         nettel_amd_map.map_priv_1 = (unsigned long)
 332                 ioremap_nocache(amdaddr, maxsize);
 333         if (!nettel_amd_map.map_priv_1) {
 334                 printk("SNAPGEAR: failed to ioremap() BOOTCS\n");
 335                 return(-EIO);
 336         }
 337
 338         if ((amd_mtd = do_map_probe("jedec_probe", &nettel_amd_map))) {
 339                 printk(KERN_NOTICE "SNAPGEAR: AMD flash device size = %dK\n",
 340                         amd_mtd->size>>10);
 341
 342                 amd_mtd->module = THIS_MODULE;
 343
 344                 /* The high BIOS partition is only present for 2MB units */
 345                 num_amd_partitions = NUM_AMD_PARTITIONS;
 346                 if (amd_mtd->size < AMD_WINDOW_MAXSIZE)
 347                         num_amd_partitions--;
 348                 /* Don't add the partition until after the primary INTEL's */
 349
 350 #ifdef CONFIG_MTD_CFI_INTELEXT
 351                 /*
 352                  *      Map the Intel flash into memory after the AMD
 353                  *      It has to start on a multiple of maxsize.
 354                  */
 355                 maxsize = SC520_PAR_TO_SIZE(orig_romcs1par);
 356                 if (maxsize < (32 * 1024 * 1024))
 357                         maxsize = (32 * 1024 * 1024);
 358                 intel0addr = amdaddr + maxsize;
 359 #endif
 360         } else {
 361 #ifdef CONFIG_MTD_CFI_INTELEXT
 362                 /* INTEL boot FLASH */
 363                 intelboot++;
 364
 365                 if (!orig_romcs1par) {
 366                         intel0cs = SC520_PAR_BOOTCS;
 367                         intel0par = (volatile unsigned long *)
 368                                 (nettel_mmcrp + 0xc4);
 369                         intel1cs = SC520_PAR_ROMCS1;
 370                         intel1par = (volatile unsigned long *)
 371                                 (nettel_mmcrp + 0xc0);
 372
 373                         intel0addr = SC520_PAR_TO_ADDR(orig_bootcspar);
 374                         maxsize = SC520_PAR_TO_SIZE(orig_bootcspar);
 375                 } else {
 376                         /* Kernel base is on ROMCS1, not BOOTCS */
 377                         intel0cs = SC520_PAR_ROMCS1;
 378                         intel0par = (volatile unsigned long *)
 379                                 (nettel_mmcrp + 0xc0);
 380                         intel1cs = SC520_PAR_BOOTCS;
 381                         intel1par = (volatile unsigned long *)
 382                                 (nettel_mmcrp + 0xc4);
 383
 384                         intel0addr = SC520_PAR_TO_ADDR(orig_romcs1par);
 385                         maxsize = SC520_PAR_TO_SIZE(orig_romcs1par);
 386                 }
 387
 388                 /* Destroy useless AMD MTD mapping */
 389                 amd_mtd = NULL;
 390                 iounmap((void *) nettel_amd_map.map_priv_1);
 391                 nettel_amd_map.map_priv_1 = (unsigned long) NULL;
 392 #else
 393                 /* Only AMD flash supported */
 394                 return(-ENXIO);
 395 #endif
 396         }
 397
 398 #ifdef CONFIG_MTD_CFI_INTELEXT
 399         /*
 400          *      We have determined the INTEL FLASH configuration, so lets
 401          *      go ahead and probe for them now.
 402          */
 403
 404         /* Set PAR to the maximum size */
 405         if (maxsize < (32 * 1024 * 1024))
 406                 maxsize = (32 * 1024 * 1024);
 407         *intel0par = SC520_PAR(intel0cs, intel0addr, maxsize);
 408
 409         /* Turn other PAR off so the first probe doesn't find it */
 410         *intel1par = 0;
 411
 412         /* Probe for the the size of the first Intel flash */
 413         nettel_intel_map.size = maxsize;
 414         nettel_intel_map.map_priv_1 = (unsigned long)
 415                 ioremap_nocache(intel0addr, maxsize);
 416         if (!nettel_intel_map.map_priv_1) {
 417                 printk("SNAPGEAR: failed to ioremap() ROMCS1\n");
 418                 return(-EIO);
 419         }
 420
 421         intel_mtd = do_map_probe("cfi_probe", &nettel_intel_map);
 422         if (! intel_mtd) {
 423                 iounmap((void *) nettel_intel_map.map_priv_1);
 424                 return(-ENXIO);
 425         }
 426
 427         /* Set PAR to the detected size */
 428         intel0size = intel_mtd->size;
 429         *intel0par = SC520_PAR(intel0cs, intel0addr, intel0size);
 430
 431         /*
 432          *      Map second Intel FLASH right after first. Set its size to the
 433          *      same maxsize used for the first Intel FLASH.
 434          */
 435         intel1addr = intel0addr + intel0size;
 436         *intel1par = SC520_PAR(intel1cs, intel1addr, maxsize);
 437         __asm__ ("wbinvd");
 438
 439         maxsize += intel0size;
 440
 441         /* Delete the old map and probe again to do both chips */
 442         map_destroy(intel_mtd);
 443         intel_mtd = NULL;
 444         iounmap((void *) nettel_intel_map.map_priv_1);
 445
 446         nettel_intel_map.size = maxsize;
 447         nettel_intel_map.map_priv_1 = (unsigned long)
 448                 ioremap_nocache(intel0addr, maxsize);
 449         if (!nettel_intel_map.map_priv_1) {
 450                 printk("SNAPGEAR: failed to ioremap() ROMCS1/2\n");
 451                 return(-EIO);
 452         }
 453
 454         intel_mtd = do_map_probe("cfi_probe", &nettel_intel_map);
 455         if (! intel_mtd) {
 456                 iounmap((void *) nettel_intel_map.map_priv_1);
 457                 return(-ENXIO);
 458         }
 459
 460         intel1size = intel_mtd->size - intel0size;
 461         if (intel1size > 0) {
 462                 *intel1par = SC520_PAR(intel1cs, intel1addr, intel1size);
 463                 __asm__ ("wbinvd");
 464         } else {
 465                 *intel1par = 0;
 466         }
 467
 468         printk(KERN_NOTICE "SNAPGEAR: Intel flash device size = %dK\n",
 469                 (intel_mtd->size >> 10));
 470
 471         intel_mtd->module = THIS_MODULE;
 472
 473 #ifndef CONFIG_BLK_DEV_INITRD
 474         ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, 1);
 475 #endif
 476
 477         num_intel_partitions = sizeof(nettel_intel_partitions) /
 478                 sizeof(nettel_intel_partitions[0]);
 479
 480         if (intelboot) {
 481                 /*
 482                  *      Adjust offset and size of last boot partition.
 483                  *      Must allow for BIOS region at end of FLASH.
 484                  */
 485                 nettel_intel_partitions[1].size = (intel0size + intel1size) -
 486                         (1024*1024 + intel_mtd->erasesize);
 487                 nettel_intel_partitions[3].size = intel0size + intel1size;
 488                 nettel_intel_partitions[4].offset =
 489                         (intel0size + intel1size) - intel_mtd->erasesize;
 490                 nettel_intel_partitions[4].size = intel_mtd->erasesize;
 491                 nettel_intel_partitions[5].offset =
 492                         nettel_intel_partitions[4].offset;
 493                 nettel_intel_partitions[5].size =
 494                         nettel_intel_partitions[4].size;
 495         } else {
 496                 /* No BIOS regions when AMD boot */
 497                 num_intel_partitions -= 2;
 498         }
 499         rc = add_mtd_partitions(intel_mtd, nettel_intel_partitions,
 500                 num_intel_partitions);
 501 #endif
 502
 503         if (amd_mtd) {
 504                 rc = add_mtd_partitions(amd_mtd, nettel_amd_partitions,
 505                         num_amd_partitions);
 506         }
 507
 508 #ifdef CONFIG_MTD_CFI_INTELEXT
 509         register_reboot_notifier(&nettel_notifier_block);
 510 #endif
 511
 512         return(rc);
 513 }
 514
 515 /****************************************************************************/
 516
 517 void __exit nettel_cleanup(void)
 518 {
 519 #ifdef CONFIG_MTD_CFI_INTELEXT
 520         unregister_reboot_notifier(&nettel_notifier_block);
 521 #endif
 522         if (amd_mtd) {
 523                 del_mtd_partitions(amd_mtd);
 524                 map_destroy(amd_mtd);
 525         }
 526         if (nettel_amd_map.map_priv_1) {
 527                 iounmap((void *)nettel_amd_map.map_priv_1);
 528                 nettel_amd_map.map_priv_1 = 0;
 529         }
 530 #ifdef CONFIG_MTD_CFI_INTELEXT
 531         if (intel_mtd) {
 532                 del_mtd_partitions(intel_mtd);
 533                 map_destroy(intel_mtd);
 534         }
 535         if (nettel_intel_map.map_priv_1) {
 536                 iounmap((void *)nettel_intel_map.map_priv_1);
 537                 nettel_intel_map.map_priv_1 = 0;
 538         }
 539 #endif
 540 }
 541
 542 /****************************************************************************/
 543
 544 module_init(nettel_init);
 545 module_exit(nettel_cleanup);
 546
 547 MODULE_LICENSE("GPL");
 548 MODULE_AUTHOR("Greg Ungerer <gerg@snapgear.com>");
 549 MODULE_DESCRIPTION("SnapGear/SecureEdge FLASH support");
 550
 551 /****************************************************************************/