1 /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
3 Copyright (c) 2001, 2002 by D-Link Corporation
4 Written by Edward Peng.<edward_peng@dlink.com.tw>
5 Created 03-May-2001, base on Linux' sundance.c.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
14 ==========================================================================
15 0.01 2001/05/03 Created DL2000-based linux driver
16 0.02 2001/05/21 Added VLAN and hardware checksum support.
17 1.00 2001/06/26 Added jumbo frame support.
18 1.01 2001/08/21 Added two parameters, rx_coalesce and rx_timeout.
19 1.02 2001/10/08 Supported fiber media.
20 Added flow control parameters.
21 1.03 2001/10/12 Changed the default media to 1000mbps_fd for
23 1.04 2001/11/08 Fixed Tx stopped when tx very busy.
24 1.05 2001/11/22 Fixed Tx stopped when unidirectional tx busy.
25 1.06 2001/12/13 Fixed disconnect bug at 10Mbps mode.
26 Fixed tx_full flag incorrect.
27 Added tx_coalesce paramter.
28 1.07 2002/01/03 Fixed miscount of RX frame error.
29 1.08 2002/01/17 Fixed the multicast bug.
30 1.09 2002/03/07 Move rx-poll-now to re-fill loop.
31 Added rio_timer() to watch rx buffers.
32 1.10 2002/04/16 Fixed miscount of carrier error.
33 1.11 2002/05/23 Added ISR schedule scheme
34 Fixed miscount of rx frame error for DGE-550SX.
36 1.12 2002/06/13 Lock tx_coalesce=1 on 10/100Mbps mode.
37 1.13 2002/08/13 1. Fix disconnection (many tx:carrier/rx:frame
38 errs) with some mainboards.
39 2. Use definition "DRV_NAME" "DRV_VERSION"
40 "DRV_RELDATE" for flexibility.
41 1.14 2002/08/14 Support ethtool.
42 1.15 2002/08/27 Changed the default media to Auto-Negotiation
43 for the fiber devices.
44 1.16 2002/09/04 More power down time for fiber devices auto-
46 Fix disconnect bug after ifup and ifdown.
47 1.17 2002/10/03 Fix RMON statistics overflow.
48 Always use I/O mapping to access eeprom,
49 avoid system freezing with some chipsets.
52 #define DRV_NAME "D-Link DL2000-based linux driver"
53 #define DRV_VERSION "v1.17a"
54 #define DRV_RELDATE "2002/10/04"
57 static char version[] __devinitdata =
58 KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
60 static int mtu[MAX_UNITS];
61 static int vlan[MAX_UNITS];
62 static int jumbo[MAX_UNITS];
63 static char *media[MAX_UNITS];
64 static int tx_flow=-1;
65 static int rx_flow=-1;
66 static int copy_thresh;
67 static int rx_coalesce=10; /* Rx frame count each interrupt */
68 static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
69 static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
72 MODULE_AUTHOR ("Edward Peng");
73 MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
74 MODULE_LICENSE("GPL");
75 MODULE_PARM (mtu, "1-" __MODULE_STRING (MAX_UNITS) "i");
76 MODULE_PARM (media, "1-" __MODULE_STRING (MAX_UNITS) "s");
77 MODULE_PARM (vlan, "1-" __MODULE_STRING (MAX_UNITS) "i");
78 MODULE_PARM (jumbo, "1-" __MODULE_STRING (MAX_UNITS) "i");
79 MODULE_PARM (tx_flow, "i");
80 MODULE_PARM (rx_flow, "i");
81 MODULE_PARM (copy_thresh, "i");
82 MODULE_PARM (rx_coalesce, "i"); /* Rx frame count each interrupt */
83 MODULE_PARM (rx_timeout, "i"); /* Rx DMA wait time in 64ns increments */
84 MODULE_PARM (tx_coalesce, "i"); /* HW xmit count each TxDMAComplete */
87 /* Enable the default interrupts */
88 #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
89 UpdateStats | LinkEvent)
91 writew(DEFAULT_INTR, ioaddr + IntEnable)
93 static int max_intrloop = 50;
94 static int multicast_filter_limit = 0x40;
96 static int rio_open (struct net_device *dev);
97 static void rio_timer (unsigned long data);
98 static void rio_tx_timeout (struct net_device *dev);
99 static void alloc_list (struct net_device *dev);
100 static int start_xmit (struct sk_buff *skb, struct net_device *dev);
101 static void rio_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
102 static void rio_free_tx (struct net_device *dev, int irq);
103 static void tx_error (struct net_device *dev, int tx_status);
104 static int receive_packet (struct net_device *dev);
105 static void rio_error (struct net_device *dev, int int_status);
106 static int change_mtu (struct net_device *dev, int new_mtu);
107 static void set_multicast (struct net_device *dev);
108 static struct net_device_stats *get_stats (struct net_device *dev);
109 static int clear_stats (struct net_device *dev);
110 static int rio_ethtool_ioctl (struct net_device *dev, void *useraddr);
111 static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
112 static int rio_close (struct net_device *dev);
113 static int find_miiphy (struct net_device *dev);
114 static int parse_eeprom (struct net_device *dev);
115 static int read_eeprom (long ioaddr, int eep_addr);
116 static int mii_wait_link (struct net_device *dev, int wait);
117 static int mii_set_media (struct net_device *dev);
118 static int mii_get_media (struct net_device *dev);
119 static int mii_set_media_pcs (struct net_device *dev);
120 static int mii_get_media_pcs (struct net_device *dev);
121 static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
122 static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
126 rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
128 struct net_device *dev;
129 struct netdev_private *np;
131 int chip_idx = ent->driver_data;
134 static int version_printed;
138 if (!version_printed++)
139 printk ("%s", version);
141 err = pci_enable_device (pdev);
146 err = pci_request_regions (pdev, "dl2k");
148 goto err_out_disable;
150 pci_set_master (pdev);
151 dev = alloc_etherdev (sizeof (*np));
156 SET_MODULE_OWNER (dev);
159 ioaddr = pci_resource_start (pdev, 1);
160 ioaddr = (long) ioremap (ioaddr, RIO_IO_SIZE);
166 ioaddr = pci_resource_start (pdev, 0);
168 dev->base_addr = ioaddr;
171 np->chip_id = chip_idx;
173 spin_lock_init (&np->tx_lock);
174 spin_lock_init (&np->rx_lock);
176 /* Parse manual configuration */
179 if (card_idx < MAX_UNITS) {
180 if (media[card_idx] != NULL) {
182 if (strcmp (media[card_idx], "auto") == 0 ||
183 strcmp (media[card_idx], "autosense") == 0 ||
184 strcmp (media[card_idx], "0") == 0 ) {
186 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
187 strcmp (media[card_idx], "4") == 0) {
190 } else if (strcmp (media[card_idx], "100mbps_hd") == 0
191 || strcmp (media[card_idx], "3") == 0) {
194 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
195 strcmp (media[card_idx], "2") == 0) {
198 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
199 strcmp (media[card_idx], "1") == 0) {
202 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
203 strcmp (media[card_idx], "6") == 0) {
206 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
207 strcmp (media[card_idx], "5") == 0) {
214 if (jumbo[card_idx] != 0) {
216 dev->mtu = MAX_JUMBO;
219 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
220 dev->mtu = mtu[card_idx];
222 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
224 if (rx_coalesce > 0 && rx_timeout > 0) {
225 np->rx_coalesce = rx_coalesce;
226 np->rx_timeout = rx_timeout;
229 np->tx_flow = (tx_flow == 0) ? 0 : 1;
230 np->rx_flow = (rx_flow == 0) ? 0 : 1;
234 else if (tx_coalesce > TX_RING_SIZE-1)
235 tx_coalesce = TX_RING_SIZE - 1;
237 dev->open = &rio_open;
238 dev->hard_start_xmit = &start_xmit;
239 dev->stop = &rio_close;
240 dev->get_stats = &get_stats;
241 dev->set_multicast_list = &set_multicast;
242 dev->do_ioctl = &rio_ioctl;
243 dev->tx_timeout = &rio_tx_timeout;
244 dev->watchdog_timeo = TX_TIMEOUT;
245 dev->change_mtu = &change_mtu;
247 dev->features = NETIF_F_IP_CSUM;
249 pci_set_drvdata (pdev, dev);
251 ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
253 goto err_out_iounmap;
254 np->tx_ring = (struct netdev_desc *) ring_space;
255 np->tx_ring_dma = ring_dma;
257 ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
259 goto err_out_unmap_tx;
260 np->rx_ring = (struct netdev_desc *) ring_space;
261 np->rx_ring_dma = ring_dma;
263 /* Parse eeprom data */
266 /* Find PHY address */
267 err = find_miiphy (dev);
269 goto err_out_unmap_rx;
272 np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0;
274 /* Set media and reset PHY */
276 /* default Auto-Negotiation for fiber deivices */
277 if (np->an_enable == 2) {
280 mii_set_media_pcs (dev);
282 /* Auto-Negotiation is mandatory for 1000BASE-T,
283 IEEE 802.3ab Annex 28D page 14 */
284 if (np->speed == 1000)
288 pci_read_config_byte(pdev, PCI_REVISION_ID, &np->pci_rev_id);
290 err = register_netdev (dev);
292 goto err_out_unmap_rx;
296 printk (KERN_INFO "%s: %s, %02x:%02x:%02x:%02x:%02x:%02x, IRQ %d\n",
298 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
299 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], irq);
301 printk(KERN_INFO "tx_coalesce:\t%d packets\n",
304 printk(KERN_INFO "rx_coalesce:\t%d packets\n"
305 KERN_INFO "rx_timeout: \t%d ns\n",
306 np->rx_coalesce, np->rx_timeout*640);
308 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
312 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
314 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
317 iounmap ((void *) ioaddr);
324 pci_release_regions (pdev);
327 pci_disable_device (pdev);
332 find_miiphy (struct net_device *dev)
334 int i, phy_found = 0;
335 struct netdev_private *np;
338 ioaddr = dev->base_addr;
341 for (i = 31; i >= 0; i--) {
342 int mii_status = mii_read (dev, i, 1);
343 if (mii_status != 0xffff && mii_status != 0x0000) {
349 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
356 parse_eeprom (struct net_device *dev)
359 long ioaddr = dev->base_addr;
363 PSROM_t psrom = (PSROM_t) sromdata;
364 struct netdev_private *np = dev->priv;
369 ioaddr = pci_resource_start (np->pdev, 0);
372 for (i = 0; i < 128; i++) {
373 ((u16 *) sromdata)[i] = le16_to_cpu (read_eeprom (ioaddr, i));
376 ioaddr = dev->base_addr;
379 crc = ~ether_crc_le (256 - 4, sromdata);
380 if (psrom->crc != crc) {
381 printk (KERN_ERR "%s: EEPROM data CRC error.\n", dev->name);
385 /* Set MAC address */
386 for (i = 0; i < 6; i++)
387 dev->dev_addr[i] = psrom->mac_addr[i];
389 /* Parse Software Infomation Block */
391 psib = (u8 *) sromdata;
395 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
396 printk (KERN_ERR "Cell data error\n");
400 case 0: /* Format version */
402 case 1: /* End of cell */
404 case 2: /* Duplex Polarity */
405 np->duplex_polarity = psib[i];
406 writeb (readb (ioaddr + PhyCtrl) | psib[i],
409 case 3: /* Wake Polarity */
410 np->wake_polarity = psib[i];
412 case 9: /* Adapter description */
413 j = (next - i > 255) ? 255 : next - i;
414 memcpy (np->name, &(psib[i]), j);
420 case 8: /* Reversed */
422 default: /* Unknown cell */
432 rio_open (struct net_device *dev)
434 struct netdev_private *np = dev->priv;
435 long ioaddr = dev->base_addr;
439 i = request_irq (dev->irq, &rio_interrupt, SA_SHIRQ, dev->name, dev);
443 /* Reset all logic functions */
444 writew (GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset,
445 ioaddr + ASICCtrl + 2);
448 /* DebugCtrl bit 4, 5, 9 must set */
449 writel (readl (ioaddr + DebugCtrl) | 0x0230, ioaddr + DebugCtrl);
453 writew (MAX_JUMBO+14, ioaddr + MaxFrameSize);
457 /* Get station address */
458 for (i = 0; i < 6; i++)
459 writeb (dev->dev_addr[i], ioaddr + StationAddr0 + i);
463 writel (np->rx_coalesce | np->rx_timeout << 16,
464 ioaddr + RxDMAIntCtrl);
466 /* Set RIO to poll every N*320nsec. */
467 writeb (0x20, ioaddr + RxDMAPollPeriod);
468 writeb (0xff, ioaddr + TxDMAPollPeriod);
469 writeb (0x30, ioaddr + RxDMABurstThresh);
470 writeb (0x30, ioaddr + RxDMAUrgentThresh);
471 writel (0x0007ffff, ioaddr + RmonStatMask);
472 /* clear statistics */
477 /* priority field in RxDMAIntCtrl */
478 writel (readl(ioaddr + RxDMAIntCtrl) | 0x7 << 10,
479 ioaddr + RxDMAIntCtrl);
481 writew (np->vlan, ioaddr + VLANId);
482 /* Length/Type should be 0x8100 */
483 writel (0x8100 << 16 | np->vlan, ioaddr + VLANTag);
484 /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
485 VLAN information tagged by TFC' VID, CFI fields. */
486 writel (readl (ioaddr + MACCtrl) | AutoVLANuntagging,
490 init_timer (&np->timer);
491 np->timer.expires = jiffies + 1*HZ;
492 np->timer.data = (unsigned long) dev;
493 np->timer.function = &rio_timer;
494 add_timer (&np->timer);
497 writel (readl (ioaddr + MACCtrl) | StatsEnable | RxEnable | TxEnable,
501 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
502 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
503 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
504 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
505 writew(macctrl, ioaddr + MACCtrl);
507 netif_start_queue (dev);
509 /* Enable default interrupts */
515 rio_timer (unsigned long data)
517 struct net_device *dev = (struct net_device *)data;
518 struct netdev_private *np = dev->priv;
520 int next_tick = 1*HZ;
523 spin_lock_irqsave(&np->rx_lock, flags);
524 /* Recover rx ring exhausted error */
525 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
526 printk(KERN_INFO "Try to recover rx ring exhausted...\n");
527 /* Re-allocate skbuffs to fill the descriptor ring */
528 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
530 entry = np->old_rx % RX_RING_SIZE;
531 /* Dropped packets don't need to re-allocate */
532 if (np->rx_skbuff[entry] == NULL) {
533 skb = dev_alloc_skb (np->rx_buf_sz);
535 np->rx_ring[entry].fraginfo = 0;
537 "%s: Still unable to re-allocate Rx skbuff.#%d\n",
541 np->rx_skbuff[entry] = skb;
543 /* 16 byte align the IP header */
544 skb_reserve (skb, 2);
545 np->rx_ring[entry].fraginfo =
546 cpu_to_le64 (pci_map_single
547 (np->pdev, skb->tail, np->rx_buf_sz,
548 PCI_DMA_FROMDEVICE));
550 np->rx_ring[entry].fraginfo |=
551 cpu_to_le64 (np->rx_buf_sz) << 48;
552 np->rx_ring[entry].status = 0;
555 spin_unlock_irqrestore (&np->rx_lock, flags);
556 np->timer.expires = jiffies + next_tick;
557 add_timer(&np->timer);
561 rio_tx_timeout (struct net_device *dev)
563 long ioaddr = dev->base_addr;
565 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
566 dev->name, readl (ioaddr + TxStatus));
569 dev->trans_start = jiffies;
572 /* allocate and initialize Tx and Rx descriptors */
574 alloc_list (struct net_device *dev)
576 struct netdev_private *np = dev->priv;
579 np->cur_rx = np->cur_tx = 0;
580 np->old_rx = np->old_tx = 0;
581 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
583 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
584 for (i = 0; i < TX_RING_SIZE; i++) {
585 np->tx_skbuff[i] = 0;
586 np->tx_ring[i].status = cpu_to_le64 (TFDDone);
587 np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma +
588 ((i+1)%TX_RING_SIZE) *
589 sizeof (struct netdev_desc));
592 /* Initialize Rx descriptors */
593 for (i = 0; i < RX_RING_SIZE; i++) {
594 np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma +
595 ((i + 1) % RX_RING_SIZE) *
596 sizeof (struct netdev_desc));
597 np->rx_ring[i].status = 0;
598 np->rx_ring[i].fraginfo = 0;
599 np->rx_skbuff[i] = 0;
602 /* Allocate the rx buffers */
603 for (i = 0; i < RX_RING_SIZE; i++) {
604 /* Allocated fixed size of skbuff */
605 struct sk_buff *skb = dev_alloc_skb (np->rx_buf_sz);
606 np->rx_skbuff[i] = skb;
609 "%s: alloc_list: allocate Rx buffer error! ",
613 skb->dev = dev; /* Mark as being used by this device. */
614 skb_reserve (skb, 2); /* 16 byte align the IP header. */
615 /* Rubicon now supports 40 bits of addressing space. */
616 np->rx_ring[i].fraginfo =
617 cpu_to_le64 ( pci_map_single (
618 np->pdev, skb->tail, np->rx_buf_sz,
619 PCI_DMA_FROMDEVICE));
620 np->rx_ring[i].fraginfo |= cpu_to_le64 (np->rx_buf_sz) << 48;
624 writel (cpu_to_le32 (np->rx_ring_dma), dev->base_addr + RFDListPtr0);
625 writel (0, dev->base_addr + RFDListPtr1);
631 start_xmit (struct sk_buff *skb, struct net_device *dev)
633 struct netdev_private *np = dev->priv;
634 struct netdev_desc *txdesc;
637 u64 tfc_vlan_tag = 0;
639 if (np->link_status == 0) { /* Link Down */
643 ioaddr = dev->base_addr;
644 entry = np->cur_tx % TX_RING_SIZE;
645 np->tx_skbuff[entry] = skb;
646 txdesc = &np->tx_ring[entry];
649 if (skb->ip_summed == CHECKSUM_HW) {
651 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
657 cpu_to_le64 (VLANTagInsert) |
658 (cpu_to_le64 (np->vlan) << 32) |
659 (cpu_to_le64 (skb->priority) << 45);
661 txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
664 txdesc->fraginfo |= cpu_to_le64 (skb->len) << 48;
666 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
667 * Work around: Always use 1 descriptor in 10Mbps mode */
668 if (entry % np->tx_coalesce == 0 || np->speed == 10)
669 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
672 (1 << FragCountShift));
674 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
676 (1 << FragCountShift));
679 writel (readl (ioaddr + DMACtrl) | 0x00001000, ioaddr + DMACtrl);
681 writel(10000, ioaddr + CountDown);
682 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
683 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
684 < TX_QUEUE_LEN - 1 && np->speed != 10) {
686 } else if (!netif_queue_stopped(dev)) {
687 netif_stop_queue (dev);
690 /* The first TFDListPtr */
691 if (readl (dev->base_addr + TFDListPtr0) == 0) {
692 writel (np->tx_ring_dma + entry * sizeof (struct netdev_desc),
693 dev->base_addr + TFDListPtr0);
694 writel (0, dev->base_addr + TFDListPtr1);
697 /* NETDEV WATCHDOG timer */
698 dev->trans_start = jiffies;
703 rio_interrupt (int irq, void *dev_instance, struct pt_regs *rgs)
705 struct net_device *dev = dev_instance;
706 struct netdev_private *np;
709 int cnt = max_intrloop;
711 ioaddr = dev->base_addr;
714 int_status = readw (ioaddr + IntStatus);
715 writew (int_status, ioaddr + IntStatus);
716 int_status &= DEFAULT_INTR;
717 if (int_status == 0 || --cnt < 0)
719 /* Processing received packets */
720 if (int_status & RxDMAComplete)
721 receive_packet (dev);
722 /* TxDMAComplete interrupt */
723 if ((int_status & (TxDMAComplete|IntRequested))) {
725 tx_status = readl (ioaddr + TxStatus);
726 if (tx_status & 0x01)
727 tx_error (dev, tx_status);
728 /* Free used tx skbuffs */
729 rio_free_tx (dev, 1);
732 /* Handle uncommon events */
734 (HostError | LinkEvent | UpdateStats))
735 rio_error (dev, int_status);
737 if (np->cur_tx != np->old_tx)
738 writel (100, ioaddr + CountDown);
742 rio_free_tx (struct net_device *dev, int irq)
744 struct netdev_private *np = (struct netdev_private *) dev->priv;
745 int entry = np->old_tx % TX_RING_SIZE;
750 spin_lock(&np->tx_lock);
752 spin_lock_irqsave(&np->tx_lock, flag);
754 /* Free used tx skbuffs */
755 while (entry != np->cur_tx) {
758 if (!(np->tx_ring[entry].status & TFDDone))
760 skb = np->tx_skbuff[entry];
761 pci_unmap_single (np->pdev,
762 np->tx_ring[entry].fraginfo,
763 skb->len, PCI_DMA_TODEVICE);
765 dev_kfree_skb_irq (skb);
769 np->tx_skbuff[entry] = 0;
770 entry = (entry + 1) % TX_RING_SIZE;
774 spin_unlock(&np->tx_lock);
776 spin_unlock_irqrestore(&np->tx_lock, flag);
779 /* If the ring is no longer full, clear tx_full and
780 call netif_wake_queue() */
782 if (netif_queue_stopped(dev) &&
783 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
784 < TX_QUEUE_LEN - 1 || np->speed == 10)) {
785 netif_wake_queue (dev);
790 tx_error (struct net_device *dev, int tx_status)
792 struct netdev_private *np;
793 long ioaddr = dev->base_addr;
799 frame_id = (tx_status & 0xffff0000);
800 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
801 dev->name, tx_status, frame_id);
802 np->stats.tx_errors++;
803 /* Ttransmit Underrun */
804 if (tx_status & 0x10) {
805 np->stats.tx_fifo_errors++;
806 writew (readw (ioaddr + TxStartThresh) + 0x10,
807 ioaddr + TxStartThresh);
808 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
809 writew (TxReset | DMAReset | FIFOReset | NetworkReset,
810 ioaddr + ASICCtrl + 2);
811 /* Wait for ResetBusy bit clear */
812 for (i = 50; i > 0; i--) {
813 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
817 rio_free_tx (dev, 1);
818 /* Reset TFDListPtr */
819 writel (np->tx_ring_dma +
820 np->old_tx * sizeof (struct netdev_desc),
821 dev->base_addr + TFDListPtr0);
822 writel (0, dev->base_addr + TFDListPtr1);
824 /* Let TxStartThresh stay default value */
827 if (tx_status & 0x04) {
828 np->stats.tx_fifo_errors++;
829 /* TxReset and clear FIFO */
830 writew (TxReset | FIFOReset, ioaddr + ASICCtrl + 2);
831 /* Wait reset done */
832 for (i = 50; i > 0; i--) {
833 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
837 /* Let TxStartThresh stay default value */
839 /* Maximum Collisions */
841 if (tx_status & 0x08)
842 np->stats.collisions16++;
844 if (tx_status & 0x08)
845 np->stats.collisions++;
848 writel (readw (dev->base_addr + MACCtrl) | TxEnable, ioaddr + MACCtrl);
852 receive_packet (struct net_device *dev)
854 struct netdev_private *np = (struct netdev_private *) dev->priv;
855 int entry = np->cur_rx % RX_RING_SIZE;
858 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
860 struct netdev_desc *desc = &np->rx_ring[entry];
864 if (!(desc->status & RFDDone) ||
865 !(desc->status & FrameStart) || !(desc->status & FrameEnd))
868 /* Chip omits the CRC. */
869 pkt_len = le64_to_cpu (desc->status & 0xffff);
870 frame_status = le64_to_cpu (desc->status);
873 pci_dma_sync_single (np->pdev, desc->fraginfo, np->rx_buf_sz,
875 /* Update rx error statistics, drop packet. */
876 if (frame_status & RFS_Errors) {
877 np->stats.rx_errors++;
878 if (frame_status & (RxRuntFrame | RxLengthError))
879 np->stats.rx_length_errors++;
880 if (frame_status & RxFCSError)
881 np->stats.rx_crc_errors++;
882 if (frame_status & RxAlignmentError && np->speed != 1000)
883 np->stats.rx_frame_errors++;
884 if (frame_status & RxFIFOOverrun)
885 np->stats.rx_fifo_errors++;
889 /* Small skbuffs for short packets */
890 if (pkt_len > copy_thresh) {
891 pci_unmap_single (np->pdev, desc->fraginfo,
894 skb_put (skb = np->rx_skbuff[entry], pkt_len);
895 np->rx_skbuff[entry] = NULL;
896 } else if ((skb = dev_alloc_skb (pkt_len + 2)) != NULL) {
898 /* 16 byte align the IP header */
899 skb_reserve (skb, 2);
900 eth_copy_and_sum (skb,
901 np->rx_skbuff[entry]->tail,
903 skb_put (skb, pkt_len);
905 skb->protocol = eth_type_trans (skb, dev);
907 /* Checksum done by hw, but csum value unavailable. */
908 if (np->pci_rev_id >= 0x0c &&
909 !(frame_status & (TCPError | UDPError | IPError))) {
910 skb->ip_summed = CHECKSUM_UNNECESSARY;
914 dev->last_rx = jiffies;
916 entry = (entry + 1) % RX_RING_SIZE;
918 spin_lock(&np->rx_lock);
920 /* Re-allocate skbuffs to fill the descriptor ring */
922 while (entry != np->cur_rx) {
924 /* Dropped packets don't need to re-allocate */
925 if (np->rx_skbuff[entry] == NULL) {
926 skb = dev_alloc_skb (np->rx_buf_sz);
928 np->rx_ring[entry].fraginfo = 0;
930 "%s: receive_packet: "
931 "Unable to re-allocate Rx skbuff.#%d\n",
935 np->rx_skbuff[entry] = skb;
937 /* 16 byte align the IP header */
938 skb_reserve (skb, 2);
939 np->rx_ring[entry].fraginfo =
940 cpu_to_le64 (pci_map_single
941 (np->pdev, skb->tail, np->rx_buf_sz,
942 PCI_DMA_FROMDEVICE));
944 np->rx_ring[entry].fraginfo |=
945 cpu_to_le64 (np->rx_buf_sz) << 48;
946 np->rx_ring[entry].status = 0;
947 entry = (entry + 1) % RX_RING_SIZE;
950 spin_unlock(&np->rx_lock);
955 rio_error (struct net_device *dev, int int_status)
957 long ioaddr = dev->base_addr;
958 struct netdev_private *np = dev->priv;
961 /* Link change event */
962 if (int_status & LinkEvent) {
963 if (mii_wait_link (dev, 10) == 0) {
964 printk (KERN_INFO "%s: Link up\n", dev->name);
966 mii_get_media_pcs (dev);
969 if (np->speed == 1000)
970 np->tx_coalesce = tx_coalesce;
974 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
975 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
976 macctrl |= (np->tx_flow) ?
977 TxFlowControlEnable : 0;
978 macctrl |= (np->rx_flow) ?
979 RxFlowControlEnable : 0;
980 writew(macctrl, ioaddr + MACCtrl);
982 netif_carrier_on(dev);
984 printk (KERN_INFO "%s: Link off\n", dev->name);
986 netif_carrier_off(dev);
990 /* UpdateStats statistics registers */
991 if (int_status & UpdateStats) {
995 /* PCI Error, a catastronphic error related to the bus interface
996 occurs, set GlobalReset and HostReset to reset. */
997 if (int_status & HostError) {
998 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
999 dev->name, int_status);
1000 writew (GlobalReset | HostReset, ioaddr + ASICCtrl + 2);
1005 static struct net_device_stats *
1006 get_stats (struct net_device *dev)
1008 long ioaddr = dev->base_addr;
1009 struct netdev_private *np = dev->priv;
1013 unsigned int stat_reg;
1015 /* All statistics registers need to be acknowledged,
1016 else statistic overflow could cause problems */
1018 np->stats.rx_packets += readl (ioaddr + FramesRcvOk);
1019 np->stats.tx_packets += readl (ioaddr + FramesXmtOk);
1020 np->stats.rx_bytes += readl (ioaddr + OctetRcvOk);
1021 np->stats.tx_bytes += readl (ioaddr + OctetXmtOk);
1023 np->stats.multicast = readl (ioaddr + McstFramesRcvdOk);
1024 np->stats.collisions += readl (ioaddr + SingleColFrames)
1025 + readl (ioaddr + MultiColFrames);
1027 /* detailed tx errors */
1028 stat_reg = readw (ioaddr + FramesAbortXSColls);
1029 np->stats.tx_aborted_errors += stat_reg;
1030 np->stats.tx_errors += stat_reg;
1032 stat_reg = readw (ioaddr + CarrierSenseErrors);
1033 np->stats.tx_carrier_errors += stat_reg;
1034 np->stats.tx_errors += stat_reg;
1036 /* Clear all other statistic register. */
1037 readl (ioaddr + McstOctetXmtOk);
1038 readw (ioaddr + BcstFramesXmtdOk);
1039 readl (ioaddr + McstFramesXmtdOk);
1040 readw (ioaddr + BcstFramesRcvdOk);
1041 readw (ioaddr + MacControlFramesRcvd);
1042 readw (ioaddr + FrameTooLongErrors);
1043 readw (ioaddr + InRangeLengthErrors);
1044 readw (ioaddr + FramesCheckSeqErrors);
1045 readw (ioaddr + FramesLostRxErrors);
1046 readl (ioaddr + McstOctetXmtOk);
1047 readl (ioaddr + BcstOctetXmtOk);
1048 readl (ioaddr + McstFramesXmtdOk);
1049 readl (ioaddr + FramesWDeferredXmt);
1050 readl (ioaddr + LateCollisions);
1051 readw (ioaddr + BcstFramesXmtdOk);
1052 readw (ioaddr + MacControlFramesXmtd);
1053 readw (ioaddr + FramesWEXDeferal);
1056 for (i = 0x100; i <= 0x150; i += 4)
1059 readw (ioaddr + TxJumboFrames);
1060 readw (ioaddr + RxJumboFrames);
1061 readw (ioaddr + TCPCheckSumErrors);
1062 readw (ioaddr + UDPCheckSumErrors);
1063 readw (ioaddr + IPCheckSumErrors);
1068 clear_stats (struct net_device *dev)
1070 long ioaddr = dev->base_addr;
1075 /* All statistics registers need to be acknowledged,
1076 else statistic overflow could cause problems */
1077 readl (ioaddr + FramesRcvOk);
1078 readl (ioaddr + FramesXmtOk);
1079 readl (ioaddr + OctetRcvOk);
1080 readl (ioaddr + OctetXmtOk);
1082 readl (ioaddr + McstFramesRcvdOk);
1083 readl (ioaddr + SingleColFrames);
1084 readl (ioaddr + MultiColFrames);
1085 readl (ioaddr + LateCollisions);
1086 /* detailed rx errors */
1087 readw (ioaddr + FrameTooLongErrors);
1088 readw (ioaddr + InRangeLengthErrors);
1089 readw (ioaddr + FramesCheckSeqErrors);
1090 readw (ioaddr + FramesLostRxErrors);
1092 /* detailed tx errors */
1093 readw (ioaddr + FramesAbortXSColls);
1094 readw (ioaddr + CarrierSenseErrors);
1096 /* Clear all other statistic register. */
1097 readl (ioaddr + McstOctetXmtOk);
1098 readw (ioaddr + BcstFramesXmtdOk);
1099 readl (ioaddr + McstFramesXmtdOk);
1100 readw (ioaddr + BcstFramesRcvdOk);
1101 readw (ioaddr + MacControlFramesRcvd);
1102 readl (ioaddr + McstOctetXmtOk);
1103 readl (ioaddr + BcstOctetXmtOk);
1104 readl (ioaddr + McstFramesXmtdOk);
1105 readl (ioaddr + FramesWDeferredXmt);
1106 readw (ioaddr + BcstFramesXmtdOk);
1107 readw (ioaddr + MacControlFramesXmtd);
1108 readw (ioaddr + FramesWEXDeferal);
1110 for (i = 0x100; i <= 0x150; i += 4)
1113 readw (ioaddr + TxJumboFrames);
1114 readw (ioaddr + RxJumboFrames);
1115 readw (ioaddr + TCPCheckSumErrors);
1116 readw (ioaddr + UDPCheckSumErrors);
1117 readw (ioaddr + IPCheckSumErrors);
1123 change_mtu (struct net_device *dev, int new_mtu)
1125 struct netdev_private *np = dev->priv;
1126 int max = (np->jumbo) ? MAX_JUMBO : 1536;
1128 if ((new_mtu < 68) || (new_mtu > max)) {
1138 set_multicast (struct net_device *dev)
1140 long ioaddr = dev->base_addr;
1146 struct dev_mc_list *mclist;
1147 struct netdev_private *np = dev->priv;
1149 hash_table[0] = hash_table[1] = 0;
1150 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
1151 hash_table[1] |= cpu_to_le32(0x02000000);
1152 if (dev->flags & IFF_PROMISC) {
1153 /* Receive all frames promiscuously. */
1154 rx_mode = ReceiveAllFrames;
1155 } else if ((dev->flags & IFF_ALLMULTI) ||
1156 (dev->mc_count > multicast_filter_limit)) {
1157 /* Receive broadcast and multicast frames */
1158 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
1159 } else if (dev->mc_count > 0) {
1160 /* Receive broadcast frames and multicast frames filtering
1163 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
1164 for (i=0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1165 i++, mclist=mclist->next)
1167 crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr);
1168 /* The inverted high significant 6 bits of CRC are
1169 used as an index to hashtable */
1170 for (index=0, bit=0; bit < 6; bit++) {
1171 if (test_bit(31-bit, &crc)) {
1172 set_bit(bit, &index);
1175 hash_table[index / 32] |= (1 << (index % 32));
1178 rx_mode = ReceiveBroadcast | ReceiveUnicast;
1181 /* ReceiveVLANMatch field in ReceiveMode */
1182 rx_mode |= ReceiveVLANMatch;
1185 writel (hash_table[0], ioaddr + HashTable0);
1186 writel (hash_table[1], ioaddr + HashTable1);
1187 writew (rx_mode, ioaddr + ReceiveMode);
1191 rio_ethtool_ioctl (struct net_device *dev, void *useraddr)
1193 struct netdev_private *np = dev->priv;
1196 if (copy_from_user (ðcmd, useraddr, sizeof (ethcmd)))
1199 case ETHTOOL_GDRVINFO: {
1200 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
1201 strcpy(info.driver, "DL2K");
1202 strcpy(info.version, DRV_VERSION);
1203 strcpy(info.bus_info, np->pdev->slot_name);
1204 memset(&info.fw_version, 0, sizeof(info.fw_version));
1205 if (copy_to_user(useraddr, &info, sizeof(info)))
1210 case ETHTOOL_GSET: {
1211 struct ethtool_cmd cmd = { ETHTOOL_GSET };
1212 if (np->phy_media) {
1214 cmd.supported = SUPPORTED_Autoneg |
1216 cmd.advertising= ADVERTISED_Autoneg |
1218 cmd.port = PORT_FIBRE;
1219 cmd.transceiver = XCVR_INTERNAL;
1222 cmd.supported = SUPPORTED_10baseT_Half |
1223 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
1224 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
1225 SUPPORTED_Autoneg | SUPPORTED_MII;
1226 cmd.advertising = ADVERTISED_10baseT_Half |
1227 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
1228 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
1229 ADVERTISED_Autoneg | ADVERTISED_MII;
1230 cmd.port = PORT_MII;
1231 cmd.transceiver = XCVR_INTERNAL;
1233 if ( np->link_status ) {
1234 cmd.speed = np->speed;
1235 cmd.duplex = np->full_duplex ?
1236 DUPLEX_FULL : DUPLEX_HALF;
1242 cmd.autoneg = AUTONEG_ENABLE;
1244 cmd.autoneg = AUTONEG_DISABLE;
1246 cmd.phy_address = np->phy_addr;
1248 if (copy_to_user(useraddr, &cmd,
1253 case ETHTOOL_SSET: {
1254 struct ethtool_cmd cmd;
1255 if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
1257 netif_carrier_off(dev);
1258 if (cmd.autoneg == AUTONEG_ENABLE) {
1268 if (np->speed == 1000){
1269 cmd.speed = SPEED_100;
1270 cmd.duplex = DUPLEX_FULL;
1271 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manul 100Mbps, Full duplex.\n");
1273 switch(cmd.speed + cmd.duplex){
1275 case SPEED_10 + DUPLEX_HALF:
1277 np->full_duplex = 0;
1280 case SPEED_10 + DUPLEX_FULL:
1282 np->full_duplex = 1;
1284 case SPEED_100 + DUPLEX_HALF:
1286 np->full_duplex = 0;
1288 case SPEED_100 + DUPLEX_FULL:
1290 np->full_duplex = 1;
1292 case SPEED_1000 + DUPLEX_HALF:/* not supported */
1293 case SPEED_1000 + DUPLEX_FULL:/* not supported */
1301 #ifdef ETHTOOL_GLINK
1302 case ETHTOOL_GLINK:{
1303 struct ethtool_value link = { ETHTOOL_GLINK };
1304 link.data = np->link_status;
1305 if (copy_to_user(useraddr, &link, sizeof(link)))
1317 rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1320 struct netdev_private *np = dev->priv;
1321 struct mii_data *miidata = (struct mii_data *) &rq->ifr_data;
1323 struct netdev_desc *desc;
1326 phy_addr = np->phy_addr;
1329 return rio_ethtool_ioctl (dev, (void *) rq->ifr_data);
1330 case SIOCDEVPRIVATE:
1333 case SIOCDEVPRIVATE + 1:
1334 miidata->out_value = mii_read (dev, phy_addr, miidata->reg_num);
1336 case SIOCDEVPRIVATE + 2:
1337 mii_write (dev, phy_addr, miidata->reg_num, miidata->in_value);
1339 case SIOCDEVPRIVATE + 3:
1341 case SIOCDEVPRIVATE + 4:
1343 case SIOCDEVPRIVATE + 5:
1344 netif_stop_queue (dev);
1346 case SIOCDEVPRIVATE + 6:
1347 netif_wake_queue (dev);
1349 case SIOCDEVPRIVATE + 7:
1351 ("tx_full=%x cur_tx=%lx old_tx=%lx cur_rx=%lx old_rx=%lx\n",
1352 netif_queue_stopped(dev), np->cur_tx, np->old_tx, np->cur_rx,
1355 case SIOCDEVPRIVATE + 8:
1356 printk("TX ring:\n");
1357 for (i = 0; i < TX_RING_SIZE; i++) {
1358 desc = &np->tx_ring[i];
1360 ("%02x:cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x",
1362 (u32) (np->tx_ring_dma + i * sizeof (*desc)),
1363 (u32) desc->next_desc,
1364 (u32) desc->status, (u32) (desc->fraginfo >> 32),
1365 (u32) desc->fraginfo);
1377 #define EEP_READ 0x0200
1378 #define EEP_BUSY 0x8000
1379 /* Read the EEPROM word */
1380 /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
1382 read_eeprom (long ioaddr, int eep_addr)
1385 outw (EEP_READ | (eep_addr & 0xff), ioaddr + EepromCtrl);
1387 if (!(inw (ioaddr + EepromCtrl) & EEP_BUSY)) {
1388 return inw (ioaddr + EepromData);
1394 enum phy_ctrl_bits {
1395 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
1399 #define mii_delay() readb(ioaddr)
1401 mii_sendbit (struct net_device *dev, u32 data)
1403 long ioaddr = dev->base_addr + PhyCtrl;
1404 data = (data) ? MII_DATA1 : 0;
1406 data |= (readb (ioaddr) & 0xf8) | MII_WRITE;
1407 writeb (data, ioaddr);
1409 writeb (data | MII_CLK, ioaddr);
1414 mii_getbit (struct net_device *dev)
1416 long ioaddr = dev->base_addr + PhyCtrl;
1419 data = (readb (ioaddr) & 0xf8) | MII_READ;
1420 writeb (data, ioaddr);
1422 writeb (data | MII_CLK, ioaddr);
1424 return ((readb (ioaddr) >> 1) & 1);
1428 mii_send_bits (struct net_device *dev, u32 data, int len)
1431 for (i = len - 1; i >= 0; i--) {
1432 mii_sendbit (dev, data & (1 << i));
1437 mii_read (struct net_device *dev, int phy_addr, int reg_num)
1444 mii_send_bits (dev, 0xffffffff, 32);
1445 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1446 /* ST,OP = 0110'b for read operation */
1447 cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
1448 mii_send_bits (dev, cmd, 14);
1450 if (mii_getbit (dev))
1453 for (i = 0; i < 16; i++) {
1454 retval |= mii_getbit (dev);
1459 return (retval >> 1) & 0xffff;
1465 mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
1470 mii_send_bits (dev, 0xffffffff, 32);
1471 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1472 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1473 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
1474 mii_send_bits (dev, cmd, 32);
1480 mii_wait_link (struct net_device *dev, int wait)
1484 struct netdev_private *np;
1487 phy_addr = np->phy_addr;
1490 bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
1491 if (bmsr.bits.link_status)
1494 } while (--wait > 0);
1498 mii_get_media (struct net_device *dev)
1506 struct netdev_private *np;
1509 phy_addr = np->phy_addr;
1511 bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
1512 if (np->an_enable) {
1513 if (!bmsr.bits.an_complete) {
1514 /* Auto-Negotiation not completed */
1517 negotiate.image = mii_read (dev, phy_addr, MII_ANAR) &
1518 mii_read (dev, phy_addr, MII_ANLPAR);
1519 mscr.image = mii_read (dev, phy_addr, MII_MSCR);
1520 mssr.image = mii_read (dev, phy_addr, MII_MSSR);
1521 if (mscr.bits.media_1000BT_FD & mssr.bits.lp_1000BT_FD) {
1523 np->full_duplex = 1;
1524 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1525 } else if (mscr.bits.media_1000BT_HD & mssr.bits.lp_1000BT_HD) {
1527 np->full_duplex = 0;
1528 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
1529 } else if (negotiate.bits.media_100BX_FD) {
1531 np->full_duplex = 1;
1532 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
1533 } else if (negotiate.bits.media_100BX_HD) {
1535 np->full_duplex = 0;
1536 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
1537 } else if (negotiate.bits.media_10BT_FD) {
1539 np->full_duplex = 1;
1540 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
1541 } else if (negotiate.bits.media_10BT_HD) {
1543 np->full_duplex = 0;
1544 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
1546 if (negotiate.bits.pause) {
1549 } else if (negotiate.bits.asymmetric) {
1553 /* else tx_flow, rx_flow = user select */
1555 bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
1556 if (bmcr.bits.speed100 == 1 && bmcr.bits.speed1000 == 0) {
1557 printk (KERN_INFO "Operating at 100 Mbps, ");
1558 } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 0) {
1559 printk (KERN_INFO "Operating at 10 Mbps, ");
1560 } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 1) {
1561 printk (KERN_INFO "Operating at 1000 Mbps, ");
1563 if (bmcr.bits.duplex_mode) {
1564 printk ("Full duplex\n");
1566 printk ("Half duplex\n");
1570 printk(KERN_INFO "Enable Tx Flow Control\n");
1572 printk(KERN_INFO "Disable Tx Flow Control\n");
1574 printk(KERN_INFO "Enable Rx Flow Control\n");
1576 printk(KERN_INFO "Disable Rx Flow Control\n");
1582 mii_set_media (struct net_device *dev)
1589 struct netdev_private *np;
1591 phy_addr = np->phy_addr;
1593 /* Does user set speed? */
1594 if (np->an_enable) {
1595 /* Advertise capabilities */
1596 bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
1597 anar.image = mii_read (dev, phy_addr, MII_ANAR);
1598 anar.bits.media_100BX_FD = bmsr.bits.media_100BX_FD;
1599 anar.bits.media_100BX_HD = bmsr.bits.media_100BX_HD;
1600 anar.bits.media_100BT4 = bmsr.bits.media_100BT4;
1601 anar.bits.media_10BT_FD = bmsr.bits.media_10BT_FD;
1602 anar.bits.media_10BT_HD = bmsr.bits.media_10BT_HD;
1603 anar.bits.pause = 1;
1604 anar.bits.asymmetric = 1;
1605 mii_write (dev, phy_addr, MII_ANAR, anar.image);
1607 /* Enable Auto crossover */
1608 pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
1609 pscr.bits.mdi_crossover_mode = 3; /* 11'b */
1610 mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
1612 /* Soft reset PHY */
1613 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1615 bmcr.bits.an_enable = 1;
1616 bmcr.bits.restart_an = 1;
1617 bmcr.bits.reset = 1;
1618 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1621 /* Force speed setting */
1622 /* 1) Disable Auto crossover */
1623 pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
1624 pscr.bits.mdi_crossover_mode = 0;
1625 mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
1628 bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
1629 bmcr.bits.reset = 1;
1630 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1633 bmcr.image = 0x1940; /* must be 0x1940 */
1634 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1635 mdelay (100); /* wait a certain time */
1637 /* 4) Advertise nothing */
1638 mii_write (dev, phy_addr, MII_ANAR, 0);
1640 /* 5) Set media and Power Up */
1642 bmcr.bits.power_down = 1;
1643 if (np->speed == 100) {
1644 bmcr.bits.speed100 = 1;
1645 bmcr.bits.speed1000 = 0;
1646 printk (KERN_INFO "Manual 100 Mbps, ");
1647 } else if (np->speed == 10) {
1648 bmcr.bits.speed100 = 0;
1649 bmcr.bits.speed1000 = 0;
1650 printk (KERN_INFO "Manual 10 Mbps, ");
1652 if (np->full_duplex) {
1653 bmcr.bits.duplex_mode = 1;
1654 printk ("Full duplex\n");
1656 bmcr.bits.duplex_mode = 0;
1657 printk ("Half duplex\n");
1660 /* Set 1000BaseT Master/Slave setting */
1661 mscr.image = mii_read (dev, phy_addr, MII_MSCR);
1662 mscr.bits.cfg_enable = 1;
1663 mscr.bits.cfg_value = 0;
1665 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1672 mii_get_media_pcs (struct net_device *dev)
1674 ANAR_PCS_t negotiate;
1678 struct netdev_private *np;
1681 phy_addr = np->phy_addr;
1683 bmsr.image = mii_read (dev, phy_addr, PCS_BMSR);
1684 if (np->an_enable) {
1685 if (!bmsr.bits.an_complete) {
1686 /* Auto-Negotiation not completed */
1689 negotiate.image = mii_read (dev, phy_addr, PCS_ANAR) &
1690 mii_read (dev, phy_addr, PCS_ANLPAR);
1692 if (negotiate.bits.full_duplex) {
1693 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1694 np->full_duplex = 1;
1696 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
1697 np->full_duplex = 0;
1699 if (negotiate.bits.pause) {
1702 } else if (negotiate.bits.asymmetric) {
1706 /* else tx_flow, rx_flow = user select */
1708 bmcr.image = mii_read (dev, phy_addr, PCS_BMCR);
1709 printk (KERN_INFO "Operating at 1000 Mbps, ");
1710 if (bmcr.bits.duplex_mode) {
1711 printk ("Full duplex\n");
1713 printk ("Half duplex\n");
1717 printk(KERN_INFO "Enable Tx Flow Control\n");
1719 printk(KERN_INFO "Disable Tx Flow Control\n");
1721 printk(KERN_INFO "Enable Rx Flow Control\n");
1723 printk(KERN_INFO "Disable Rx Flow Control\n");
1729 mii_set_media_pcs (struct net_device *dev)
1735 struct netdev_private *np;
1737 phy_addr = np->phy_addr;
1739 /* Auto-Negotiation? */
1740 if (np->an_enable) {
1741 /* Advertise capabilities */
1742 esr.image = mii_read (dev, phy_addr, PCS_ESR);
1743 anar.image = mii_read (dev, phy_addr, MII_ANAR);
1744 anar.bits.half_duplex =
1745 esr.bits.media_1000BT_HD | esr.bits.media_1000BX_HD;
1746 anar.bits.full_duplex =
1747 esr.bits.media_1000BT_FD | esr.bits.media_1000BX_FD;
1748 anar.bits.pause = 1;
1749 anar.bits.asymmetric = 1;
1750 mii_write (dev, phy_addr, MII_ANAR, anar.image);
1752 /* Soft reset PHY */
1753 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1755 bmcr.bits.an_enable = 1;
1756 bmcr.bits.restart_an = 1;
1757 bmcr.bits.reset = 1;
1758 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1761 /* Force speed setting */
1764 bmcr.bits.reset = 1;
1765 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1768 bmcr.bits.an_enable = 0;
1769 if (np->full_duplex) {
1770 bmcr.bits.duplex_mode = 1;
1771 printk (KERN_INFO "Manual full duplex\n");
1773 bmcr.bits.duplex_mode = 0;
1774 printk (KERN_INFO "Manual half duplex\n");
1776 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1779 /* Advertise nothing */
1780 mii_write (dev, phy_addr, MII_ANAR, 0);
1787 rio_close (struct net_device *dev)
1789 long ioaddr = dev->base_addr;
1790 struct netdev_private *np = dev->priv;
1791 struct sk_buff *skb;
1794 netif_stop_queue (dev);
1796 /* Disable interrupts */
1797 writew (0, ioaddr + IntEnable);
1799 /* Stop Tx and Rx logics */
1800 writel (TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl);
1802 free_irq (dev->irq, dev);
1803 del_timer_sync (&np->timer);
1805 /* Free all the skbuffs in the queue. */
1806 for (i = 0; i < RX_RING_SIZE; i++) {
1807 np->rx_ring[i].status = 0;
1808 np->rx_ring[i].fraginfo = 0;
1809 skb = np->rx_skbuff[i];
1811 pci_unmap_single (np->pdev, np->rx_ring[i].fraginfo,
1812 skb->len, PCI_DMA_FROMDEVICE);
1813 dev_kfree_skb (skb);
1814 np->rx_skbuff[i] = 0;
1817 for (i = 0; i < TX_RING_SIZE; i++) {
1818 skb = np->tx_skbuff[i];
1820 pci_unmap_single (np->pdev, np->tx_ring[i].fraginfo,
1821 skb->len, PCI_DMA_TODEVICE);
1822 dev_kfree_skb (skb);
1823 np->tx_skbuff[i] = 0;
1830 static void __devexit
1831 rio_remove1 (struct pci_dev *pdev)
1833 struct net_device *dev = pci_get_drvdata (pdev);
1836 struct netdev_private *np = dev->priv;
1838 unregister_netdev (dev);
1839 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
1841 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
1844 iounmap ((char *) (dev->base_addr));
1847 pci_release_regions (pdev);
1848 pci_disable_device (pdev);
1850 pci_set_drvdata (pdev, NULL);
1853 static struct pci_driver rio_driver = {
1855 id_table: rio_pci_tbl,
1857 remove: __devexit_p(rio_remove1),
1863 return pci_module_init (&rio_driver);
1869 pci_unregister_driver (&rio_driver);
1872 module_init (rio_init);
1873 module_exit (rio_exit);
1879 gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
1881 Read Documentation/networking/dl2k.txt for details.