1 /* Driver for EVB64260 ethernet ports
2 Copyright (C)2000, 2001 Rabeeh Khoury, Marvell */
4 * drivers/net/gt64260_eth.h
6 * Author: Rabeeh Khoury from Marvell
7 * Modified by: Mark A. Greer <mgreer@mvista.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/spinlock.h>
20 #include <asm/gt64260.h>
22 #define DESCRIPTOR_SIZE sizeof(gt_dma_desc)
23 #define Q_INDEX_LIMIT (PAGE_SIZE / DESCRIPTOR_SIZE)
25 #define NUM_TX_QUEUES 2
26 #define NUM_RX_QUEUES 4
27 #define GT64260_INT_THRE 5
28 #define GT_ENET_DESC_OWNERSHIP (1<<31)
29 #define GT_ENET_DESC_INT_ENABLE (1<<23)
30 #define GT_ENET_DESC_ERROR_SUMMARY (1<<15)
31 #define MAX_BUFF_SIZE 1536
33 #define ETH_ADDR_GAP ( GT64260_ENET_E1PCR - GT64260_ENET_E0PCR )
35 const char gt64260_eth0_name[] = "GEth0";
36 const char gt64260_eth1_name[] = "GEth1";
38 s32 gt64260_eth_init(struct net_device *);
39 s32 gt64260_eth_open(struct net_device *);
40 s32 gt64260_eth_start_xmit(struct sk_buff *, struct net_device *);
41 s32 gt64260_eth_stop(struct net_device *);
42 void gt64260_eth_int_handler(s32, void *, struct pt_regs *);
43 s32 gt64260_eth_set_mac_address(struct net_device *, void *);
44 struct net_device_stats *gt64260_eth_get_stats(struct net_device *);
46 typedef volatile struct gt_dma_desc_struct {
58 volatile u32 command_status;
59 volatile u32 next; /* Physical address, only read by the DMA engine. */
60 volatile void *data; /* Physical address, only read by the DMA engine. */
63 * Force sizeof(gt64260enetDMAdescriptor) == sizeof(cacheline)
64 * Not yet sure exactly why this is necessary but the GT64260-B
65 * part apparently has (yet another) bug that shows itself without
66 * this padding. The symptom is that all Enet comms simply stop.
68 u32 cachelineSizePadding[4];
71 typedef struct gt_eth_priv_struct {
72 gt_dma_desc *TXqueue[NUM_TX_QUEUES];
73 gt_dma_desc *RXqueue[NUM_RX_QUEUES];
74 struct sk_buff *TXskbuff[NUM_TX_QUEUES][Q_INDEX_LIMIT];
75 struct sk_buff *RXskbuff[NUM_RX_QUEUES][Q_INDEX_LIMIT];
76 u32 TXindex[NUM_TX_QUEUES];
77 u32 RXindex[NUM_RX_QUEUES];
78 u32 TXskbIndex[NUM_TX_QUEUES];
81 struct net_device_stats stat;
83 struct mii_if_info mii_if;
88 * ----------------------------------------------------------------------------
89 * addressTable.h - this file has all the declarations of the address table
93 #define ADDRESS_TABLE_ALIGNMENT 8
94 #define HASH_DEFAULT_MODE 14
98 #define MAC_ADDRESS_STRING_SIZE 12
99 #define MAC_ENTRY_SIZE sizeof(addrTblEntry)
100 #define MAX_NUMBER_OF_ADDRESSES_TO_STORE 1000
101 #define PROMISCUOUS_MODE 0
107 * ----------------------------------------------------------------------------
108 * XXX_MIKE - potential sign-extension bugs lurk here...
110 #define NIBBLE_SWAPPING_32_BIT(X) ( (((X) & 0xf0f0f0f0) >> 4) \
111 | (((X) & 0x0f0f0f0f) << 4) )
113 #define NIBBLE_SWAPPING_16_BIT(X) ( (((X) & 0x0000f0f0) >> 4) \
114 | (((X) & 0x00000f0f) << 4) )
116 #define FLIP_4_BITS(X) ( (((X) & 0x01) << 3) | (((X) & 0x002) << 1) \
117 | (((X) & 0x04) >> 1) | (((X) & 0x008) >> 3) )
119 #define FLIP_6_BITS(X) ( (((X) & 0x01) << 5) | (((X) & 0x020) >> 5) \
120 | (((X) & 0x02) << 3) | (((X) & 0x010) >> 3) \
121 | (((X) & 0x04) << 1) | (((X) & 0x008) >> 1) )
123 #define FLIP_9_BITS(X) ( (((X) & 0x01) << 8) | (((X) & 0x100) >> 8) \
124 | (((X) & 0x02) << 6) | (((X) & 0x080) >> 6) \
125 | (((X) & 0x04) << 4) | (((X) & 0x040) >> 4) \
126 | ((X) & 0x10) | (((X) & 0x08) << 2) | (((X) & 0x020) >> 2) )
129 * V: value we're operating on
130 * O: offset of rightmost bit in field
131 * W: width of field to shift
132 * S: distance to shift left
134 #define MASK( fieldWidth ) ((1 << (fieldWidth)) - 1)
135 #define leftShiftedBitfield( V,O,W,S) (((V) & (MASK(W) << (O))) << (S))
136 #define rightShiftedBitfield(V,O,W,S) (((u32)((V) & (MASK(W) << (O)))) >> (S))
138 /* cache flushing helpers */
140 #define flush_dcache_addr_size( A, N ) \
141 flush_dcache_range( ((u32)A), ((u32)(A)+(N)) )
143 #define flush_dcache(x) flush_dcache_range( ((u32)x) , ((u32)x) + sizeof(*(x)))
145 #define invalidate_dcache(x) invalidate_dcache_range( ((u32)x) , ((u32)x) + sizeof(*(x)))
147 static u32 uncachedPages(u32 pages);
149 static u32 hashTableFunction(u32 macH, u32 macL, u32 HashSize, u32 hash_mode);
151 static void addressTableClear(u32 port);
154 initAddressTable(u32 port, u32 hashMode, u32 hashSize, u32 hashDefaultMode);
157 addAddressTableEntry(u32 port, u32 macH, u32 macL, u32 rd, u32 skip);
159 /* this file has all the ethernet low level definitions */
162 #define ETHERNET_PORTS_DIFFERENCE_OFFSETS 0x400
164 #define ETHERNET0_HH_PRIORITY 11
165 #define ETHERNET0_LL_PRIORITY 2
166 #define ETHERNET1_HH_PRIORITY 12
168 /* this macros are used to enable access to SMI_REG */
169 #define SMI_OP_CODE_BIT_READ 1
170 #define SMI_OP_CODE_BIT_WRITE 0
171 #define SMI_BUSY 1<<28
172 #define READ_VALID 1<<27
174 #ifdef CONFIG_ZUMA_V2
178 #elif CONFIG_MOT_MVP || CONFIG_HXEB100
188 /* this macros are used to enable access to ETHERNET_PCXR */
189 #define OVERRIDE_RX_PRIORITY 1<<8
190 #define MIB_CLEAR_MODE 1<<16
192 /* this macros are used to enable access to ETHERNET_SDCMR */
193 #define START_TX_HIGH 1<<23
194 #define START_TX_LOW 1<<24
195 #define ENABLE_RX_DMA 1<<7
196 #define ABORT_RECEIVE 1<<15
197 #define STOP_TX_HIGH 1<<16
198 #define STOP_TX_LOW 1<<17
199 #define ABORT_TRANSMIT 1<<31
201 /* this macros are used to enable access to ETHERNET_SDCR */
202 #define ETHERNET_SDMA_BURST_SIZE 3
204 typedef unsigned int ETHERNET_PCR;
205 typedef unsigned int ETHERNET_PCXR;
206 typedef unsigned int ETHERNET_PCMR;
207 typedef unsigned int ETHERNET_PSR;
208 typedef unsigned int ETHERNET_SDCMR;
209 typedef unsigned int ETHERNET_SDCR;
211 typedef unsigned int PHY_ADD_REG;
212 typedef unsigned int SMI_REG;
214 typedef struct mibCounters {
215 unsigned int byteReceived;
216 unsigned int byteSent;
217 unsigned int framesReceived;
218 unsigned int framesSent;
219 unsigned int totalByteReceived;
220 unsigned int totalFramesReceived;
221 unsigned int broadcastFramesReceived;
222 unsigned int multicastFramesReceived;
223 unsigned int cRCError;
224 unsigned int oversizeFrames;
225 unsigned int fragments;
227 unsigned int collision;
228 unsigned int lateCollision;
229 unsigned int frames64;
230 unsigned int frames65_127;
231 unsigned int frames128_255;
232 unsigned int frames256_511;
233 unsigned int frames512_1023;
234 unsigned int frames1024_MaxSize;
235 unsigned int macRxError;
236 unsigned int droppedFrames;
237 unsigned int outMulticastFrames;
238 unsigned int outBroadcastFrames;
239 unsigned int undersizeFrames;
240 } STRUCT_MIB_COUNTERS;
242 static int etherReadMIIReg(unsigned int portNum, unsigned int miiReg,
243 unsigned int *value);
245 static int etherWriteMIIReg(unsigned int portNum, unsigned int miiReg,
249 #undef THREE_ETHERNET_RMII_PORTS
250 #define TWO_ETHERNET_MII_PORTS
252 #define THREE_ETHERNET_RMII_PORTS
253 #undef TWO_ETHERNET_MII_PORTS
256 #define ETHERNET_PORT2 2
257 #define ETHERNET_PORT1 1
258 #define ETHERNET_PORT0 0
260 #define MAX_NUMBER_OF_MPSC_PORTS 3
261 #define MAX_NUMBER_OF_ETHERNET_PORTS 3
263 #ifdef THREE_ETHERNET_RMII_PORTS
268 #define NUMBER_OF_ETHERNET_PORTS 3
269 #define NUMBER_OF_MPSC_PORTS 2
270 #define MRR_REG_VALUE 0x7ffe38
272 /* connect MPSC0 + 3 ports of RMII */
273 #define SERIAL_PORT_MULTIPLEX_REGISTER_VALUE 0x1102
275 // 0000 0000 0001 0001 20 - RMII
276 // 16 - clear MIB counters
277 // 1000 1000 0000 0000 15:14 - 2048 (10)
278 //#define PORT_CONTROL_EXTEND_VALUE 0x00118000
281 // 0000 0000 0000 0001 20 - RMII
282 // 0100 1101 0000 0000 15:14 - 1536 (01)
283 // 11 - dont force link pass
284 // 10 - disable FC AN
286 //#define PORT_CONTROL_EXTEND_VALUE 0x00104d00
288 /* Montavista value */
289 // 0000 0000 0011 0000 21 - DSCP
291 // 0100 1100 0010 0010 15:14 - 1536 (01)
292 // 11 - dont force link pass
293 // 10 - disable fc AN
294 // 5:3 - 8pkt high, 1 low (100)
296 #define PORT_CONTROL_EXTEND_VALUE 0x00304c20
298 #define ETHERNET_DOWNLOADING_PORT ETHERNET_PORT2
300 #else /* if !THREE_ETHERNET_RMII_PORTS */
302 #ifdef TWO_ETHERNET_MII_PORTS
307 #define NUMBER_OF_ETHERNET_PORTS 2
308 #define NUMBER_OF_MPSC_PORTS 2
309 #define MRR_REG_VALUE 0x7ffe38
310 /* connect MPSC0 + 2 ports of MII */
311 #define SERIAL_PORT_MULTIPLEX_REGISTER_VALUE 0x1101
313 // 0000 0000 0000 0001 16 - clear MIB counters
314 // 1000 1000 0000 0000 15:14 - 2048 (10)
315 //#define PORT_CONTROL_EXTEND_VALUE 0x00018000
317 /* PPCBoot (ZUMA) value */
318 // 0000 0000 0000 0000
319 // 0100 1101 0000 0000 15:14 - 1536 (01)
320 // 11 - dont force link pass
321 // 10 - disable FC AN
323 //#define PORT_CONTROL_EXTEND_VALUE 0x00004d00
325 /* Montavista (ZUMA) value */
326 // 0000 0000 0010 0000 21 - DSCP
327 // 0100 1100 0010 0010 15:14 - 1536 (01)
328 // 11 - dont force link pass
329 // 10 - disable fc AN
330 // 5:3 - 8pkt high, 1 low (100)
332 #ifndef CONFIG_MOT_MVP
333 #define PORT_CONTROL_EXTEND_VALUE 0x00204c20
335 /* Hack, don't allow 10mbit for now */
336 // 0000 0000 0010 1100 21 - DSCP
337 // 0100 1100 0010 0010 18 - Speed (1-> 100mbit)
338 // 19 - SpeedEn (1-> disable speed AN)
340 // 11 - dont force link pass
341 // 10 - disable fc AN
342 // 5:3 - 8pkt high, 1 low (100)
345 #define PORT_CONTROL_EXTEND_VALUE 0x002c4c20
348 #define ETHERNET_DOWNLOADING_PORT ETHERNET_PORT1
350 #endif /* endif TWO_ETHERNET_MII_PORTS */
351 #endif /* endif !THREE_ETHERNET_RMII_PORTS */
353 #define LL_QUEUE_PRIORITY 1
354 #define L_QUEUE_PRIORITY 2
355 #define H_QUEUE_PRIORITY 3
356 #define HH_QUEUE_PRIORITY 4
358 #define NUMBER_OF_MIB_COUNTERS 25
360 #define TIME_OUT 10 /* 1/6 SEC */
363 #endif /* #ifndef GT64260_ETH_H */