5 * Include file with tunable driver parameters for Gigabit Ethernet
\r
6 * device driver for Network Interface Cards (NICs) utilizing the
\r
7 * Tamarack Microelectronics Inc. IPG Gigabit or Triple Speed
\r
8 * Ethernet Media Access Controller.
\r
11 * Sundance Technology, Inc.
\r
12 * 1485 Saratoga Avenue
\r
14 * San Jose, CA 95129
\r
16 * www.sundanceti.com
\r
17 * craig_rich@sundanceti.com
\r
19 * Rev Date Description
\r
20 * --------------------------------------------------------------
\r
21 * 0.1 3/30/01 New file created from original ipg.h
\r
23 * 0.2 5/22/01 Added PCI_DEVICE_ID_TAMARACK_TC9020_9021_ALT.
\r
25 * 0.3 6/20/01 Added IPG_ADD_IPCHECKSUM_ON_TX,
\r
26 * IPG_ADD_TCPCHECKSUM_ON_TX, and
\r
27 * IPG_ADD_UDPCHECKSUM_ON_TX.
\r
29 * 0.4 8/11/01 Added comments about avoiding use of TCP/UDP
\r
30 * checksums for silicon revs B3 and earlier.
\r
32 * 0.5 10/30/01 Optimized numerous settings.
\r
35 /* Define PCI vendor and device IDs if not already
\r
39 #ifndef PCI_VENDOR_ID_ICPLUS
\r
40 # define PCI_VENDOR_ID_ICPLUS 0x13F0
\r
42 #ifndef PCI_DEVICE_ID_IP1000
\r
43 # define PCI_DEVICE_ID_IP1000 0x1023
\r
45 #ifndef PCI_VENDOR_ID_SUNDANCE
\r
46 # define PCI_VENDOR_ID_SUNDANCE 0x13F0
\r
48 #ifndef PCI_DEVICE_ID_SUNDANCE_IPG
\r
49 # define PCI_DEVICE_ID_SUNDANCE_ST2021 0x2021
\r
51 #ifndef PCI_DEVICE_ID_TAMARACK_TC9020_9021_ALT
\r
52 # define PCI_DEVICE_ID_TAMARACK_TC9020_9021_ALT 0x9021
\r
54 #ifndef PCI_DEVICE_ID_TAMARACK_TC9020_9021
\r
55 # define PCI_DEVICE_ID_TAMARACK_TC9020_9021 0x1021
\r
57 #ifndef PCI_VENDOR_ID_DLINK
\r
58 # define PCI_VENDOR_ID_DLINK 0x1186
\r
60 #ifndef PCI_DEVICE_ID_DLINK_1002
\r
61 # define PCI_DEVICE_ID_DLINK_1002 0x4000
\r
63 #ifndef PCI_DEVICE_ID_DLINK_IP1000A
\r
64 # define PCI_DEVICE_ID_DLINK_IP1000A 0x4020
\r
67 /* Miscellaneous Constants. */
\r
71 /* Assign IPG_APPEND_FCS_ON_TX > 0 for auto FCS append on TX. */
\r
72 #define IPG_APPEND_FCS_ON_TX TRUE
\r
74 /* Assign IPG_APPEND_FCS_ON_TX > 0 for auto FCS strip on RX. */
\r
75 #define IPG_STRIP_FCS_ON_RX TRUE
\r
77 /* Assign IPG_DROP_ON_RX_ETH_ERRORS > 0 to drop RX frames with
\r
80 #define IPG_DROP_ON_RX_ETH_ERRORS TRUE
\r
82 /* Assign IPG_INSERT_MANUAL_VLAN_TAG > 0 to insert VLAN tags manually
\r
85 #define IPG_INSERT_MANUAL_VLAN_TAG FALSE
\r
87 /* Assign IPG_ADD_IPCHECKSUM_ON_TX > 0 for auto IP checksum on TX. */
\r
88 #define IPG_ADD_IPCHECKSUM_ON_TX FALSE
\r
90 /* Assign IPG_ADD_TCPCHECKSUM_ON_TX > 0 for auto TCP checksum on TX.
\r
91 * DO NOT USE FOR SILICON REVISIONS B3 AND EARLIER.
\r
93 #define IPG_ADD_TCPCHECKSUM_ON_TX FALSE
\r
95 /* Assign IPG_ADD_UDPCHECKSUM_ON_TX > 0 for auto UDP checksum on TX.
\r
96 * DO NOT USE FOR SILICON REVISIONS B3 AND EARLIER.
\r
98 #define IPG_ADD_UDPCHECKSUM_ON_TX FALSE
\r
100 /* If inserting VLAN tags manually, assign the IPG_MANUAL_VLAN_xx
\r
101 * constants as desired.
\r
103 #define IPG_MANUAL_VLAN_VID 0xABC
\r
104 #define IPG_MANUAL_VLAN_CFI 0x1
\r
105 #define IPG_MANUAL_VLAN_USERPRIORITY 0x5
\r
107 #define IPG_IO_REG_RANGE 0xFF
\r
108 #define IPG_MEM_REG_RANGE 0x154
\r
109 #define IPG_DRIVER_NAME "Sundance Technology IPG Triple-Speed Ethernet"
\r
110 #define IPG_NIC_PHY_ADDRESS 0x01
\r
111 #define IPG_DMALIST_ALIGN_PAD 0x07
\r
112 #define IPG_MULTICAST_HASHTABLE_SIZE 0x40
\r
114 /* Number of miliseconds to wait after issuing a software reset.
\r
115 * 0x05 <= IPG_AC_RESETWAIT to account for proper 10Mbps operation.
\r
117 #define IPG_AC_RESETWAIT 0x05
\r
119 /* Number of IPG_AC_RESETWAIT timeperiods before declaring timeout. */
\r
120 #define IPG_AC_RESET_TIMEOUT 0x0A
\r
122 /* Minimum number of miliseconds used to toggle MDC clock during
\r
123 * MII/GMII register access.
\r
125 #define IPG_PC_PHYCTRLWAIT 0x01
\r
127 #define IPG_TFDLIST_LENGTH 0x100
\r
129 /* Number of frames between TxDMAComplete interrupt.
\r
130 * 0 < IPG_FRAMESBETWEENTXDMACOMPLETES <= IPG_TFDLIST_LENGTH
\r
132 #define IPG_FRAMESBETWEENTXDMACOMPLETES 0x1
\r
136 # ifdef JUMBO_FRAME_SIZE_2K
\r
137 # define JUMBO_FRAME_SIZE 2048
\r
138 # define __IPG_RXFRAG_SIZE 2048
\r
140 # ifdef JUMBO_FRAME_SIZE_3K
\r
141 # define JUMBO_FRAME_SIZE 3072
\r
142 # define __IPG_RXFRAG_SIZE 3072
\r
144 # ifdef JUMBO_FRAME_SIZE_4K
\r
145 # define JUMBO_FRAME_SIZE 4096
\r
146 # define __IPG_RXFRAG_SIZE 4088
\r
148 # ifdef JUMBO_FRAME_SIZE_5K
\r
149 # define JUMBO_FRAME_SIZE 5120
\r
150 # define __IPG_RXFRAG_SIZE 4088
\r
152 # ifdef JUMBO_FRAME_SIZE_6K
\r
153 # define JUMBO_FRAME_SIZE 6144
\r
154 # define __IPG_RXFRAG_SIZE 4088
\r
156 # ifdef JUMBO_FRAME_SIZE_7K
\r
157 # define JUMBO_FRAME_SIZE 7168
\r
158 # define __IPG_RXFRAG_SIZE 4088
\r
160 # ifdef JUMBO_FRAME_SIZE_8K
\r
161 # define JUMBO_FRAME_SIZE 8192
\r
162 # define __IPG_RXFRAG_SIZE 4088
\r
164 # ifdef JUMBO_FRAME_SIZE_9K
\r
165 # define JUMBO_FRAME_SIZE 9216
\r
166 # define __IPG_RXFRAG_SIZE 4088
\r
168 # ifdef JUMBO_FRAME_SIZE_10K
\r
169 # define JUMBO_FRAME_SIZE 10240
\r
170 # define __IPG_RXFRAG_SIZE 4088
\r
172 # define JUMBO_FRAME_SIZE 4096
\r
184 /* Size of allocated received buffers. Nominally 0x0600.
\r
185 * Define larger if expecting jumbo frames.
\r
188 //IPG_TXFRAG_SIZE must <= 0x2b00, or TX will crash
\r
189 #define IPG_TXFRAG_SIZE JUMBO_FRAME_SIZE
\r
193 /* Size of allocated received buffers. Nominally 0x0600.
\r
194 * Define larger if expecting jumbo frames.
\r
198 #define IPG_RXFRAG_SIZE __IPG_RXFRAG_SIZE
\r
199 #define IPG_RXSUPPORT_SIZE IPG_MAX_RXFRAME_SIZE
\r
201 #define IPG_RXFRAG_SIZE 0x0600
\r
202 #define IPG_RXSUPPORT_SIZE IPG_RXFRAG_SIZE
\r
205 /* IPG_MAX_RXFRAME_SIZE <= IPG_RXFRAG_SIZE */
\r
207 #define IPG_MAX_RXFRAME_SIZE JUMBO_FRAME_SIZE
\r
209 #define IPG_MAX_RXFRAME_SIZE 0x0600
\r
212 #define IPG_RFDLIST_LENGTH 0x100
\r
214 /* Maximum number of RFDs to process per interrupt.
\r
215 * 1 < IPG_MAXRFDPROCESS_COUNT < IPG_RFDLIST_LENGTH
\r
217 #define IPG_MAXRFDPROCESS_COUNT 0x80
\r
219 /* Minimum margin between last freed RFD, and current RFD.
\r
220 * 1 < IPG_MINUSEDRFDSTOFREE < IPG_RFDLIST_LENGTH
\r
222 #define IPG_MINUSEDRFDSTOFREE 0x80
\r
224 /* Specify priority threshhold for a RxDMAPriority interrupt. */
\r
225 #define IPG_PRIORITY_THRESH 0x07
\r
227 /* Specify the number of receive frames transferred via DMA
\r
228 * before a RX interrupt is issued.
\r
230 #define IPG_RXFRAME_COUNT 0x08
\r
232 /* specify the jumbo frame maximum size
\r
233 * per unit is 0x600 (the RxBuffer size that one RFD can carry)
\r
235 #define MAX_JUMBOSIZE 0x8 // max is 12K
\r
237 /* Specify the maximum amount of time (in 64ns increments) to wait
\r
238 * before issuing a RX interrupt if number of frames received
\r
239 * is less than IPG_RXFRAME_COUNT.
\r
242 * -------------------
\r
248 #define IPG_RXDMAWAIT_TIME 0x009C
\r
250 /* Key register values loaded at driver start up. */
\r
252 /* TXDMAPollPeriod is specified in 320ns increments.
\r
255 * ---------------------
\r
261 #define IPG_TXDMAPOLLPERIOD_VALUE 0x26
\r
262 #define IPG_TXSTARTTHRESH_VALUE 0x0FFF
\r
264 /* TxDMAUrgentThresh specifies the minimum amount of
\r
265 * data in the transmit FIFO before asserting an
\r
266 * urgent transmit DMA request.
\r
268 * Value Min TxFIFO occupied space before urgent TX request
\r
269 * ---------------------------------------------------------------
\r
270 * 0x00-0x04 128 bytes (1024 bits)
\r
271 * 0x27 1248 bytes (~10000 bits)
\r
272 * 0x30 1536 bytes (12288 bits)
\r
273 * 0xFF 8192 bytes (65535 bits)
\r
275 #define IPG_TXDMAURGENTTHRESH_VALUE 0x04
\r
277 /* TxDMABurstThresh specifies the minimum amount of
\r
278 * free space in the transmit FIFO before asserting an
\r
279 * transmit DMA request.
\r
281 * Value Min TxFIFO free space before TX request
\r
282 * ----------------------------------------------------
\r
283 * 0x00-0x08 256 bytes
\r
287 #define IPG_TXDMABURSTTHRESH_VALUE 0x30
\r
289 /* RXDMAPollPeriod is specified in 320ns increments.
\r
292 * ---------------------
\r
298 #define IPG_RXDMAPOLLPERIOD_VALUE 0x01
\r
299 #define IPG_RXEARLYTHRESH_VALUE 0x07FF
\r
301 /* RxDMAUrgentThresh specifies the minimum amount of
\r
302 * free space within the receive FIFO before asserting
\r
303 * a urgent receive DMA request.
\r
305 * Value Min RxFIFO free space before urgent RX request
\r
306 * ---------------------------------------------------------------
\r
307 * 0x00-0x04 128 bytes (1024 bits)
\r
308 * 0x27 1248 bytes (~10000 bits)
\r
309 * 0x30 1536 bytes (12288 bits)
\r
310 * 0xFF 8192 bytes (65535 bits)
\r
312 #define IPG_RXDMAURGENTTHRESH_VALUE 0x30
\r
314 /* RxDMABurstThresh specifies the minimum amount of
\r
315 * occupied space within the receive FIFO before asserting
\r
316 * a receive DMA request.
\r
318 * Value Min TxFIFO free space before TX request
\r
319 * ----------------------------------------------------
\r
320 * 0x00-0x08 256 bytes
\r
324 #define IPG_RXDMABURSTTHRESH_VALUE 0x30
\r
326 /* FlowOnThresh specifies the maximum amount of occupied
\r
327 * space in the receive FIFO before a PAUSE frame with
\r
328 * maximum pause time transmitted.
\r
330 * Value Max RxFIFO occupied space before PAUSE
\r
331 * ---------------------------------------------------
\r
333 * 0x0740 29,696 bytes
\r
334 * 0x07FF 32,752 bytes
\r
336 #define IPG_FLOWONTHRESH_VALUE 0x0740
\r
338 /* FlowOffThresh specifies the minimum amount of occupied
\r
339 * space in the receive FIFO before a PAUSE frame with
\r
340 * zero pause time is transmitted.
\r
342 * Value Max RxFIFO occupied space before PAUSE
\r
343 * ---------------------------------------------------
\r
345 * 0x00BF 3056 bytes
\r
346 * 0x07FF 32,752 bytes
\r
348 #define IPG_FLOWOFFTHRESH_VALUE 0x00BF
\r
350 /* end ipg_tune.h */
\r