2 * Driver for the Macintosh 68K onboard MACE controller with PSC
3 * driven DMA. The MACE driver code is derived from mace.c. The
4 * Mac68k theory of operation is courtesy of the MacBSD wizards.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 * Copyright (C) 1996 Paul Mackerras.
12 * Copyright (C) 1998 Alan Cox <alan@redhat.com>
14 * Modified heavily by Joshua M. Thompson based on Dave Huang's NetBSD driver
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/netdevice.h>
21 #include <linux/etherdevice.h>
22 #include <linux/delay.h>
23 #include <linux/string.h>
24 #include <linux/crc32.h>
26 #include <asm/pgtable.h>
28 #include <asm/macintosh.h>
29 #include <asm/macints.h>
30 #include <asm/mac_psc.h>
36 #define N_RX_PAGES ((N_RX_RING * 0x0800 + PAGE_SIZE - 1) / PAGE_SIZE)
39 /* Bits in transmit DMA status */
40 #define TX_DMA_ERR 0x80
42 /* The MACE is simply wired down on a Mac68K box */
44 #define MACE_BASE (void *)(0x50F1C000)
45 #define MACE_PROM (void *)(0x50F08001)
48 volatile struct mace *mace;
49 volatile unsigned char *tx_ring;
50 volatile unsigned char *tx_ring_phys;
51 volatile unsigned char *rx_ring;
52 volatile unsigned char *rx_ring_phys;
54 struct net_device_stats stats;
56 int tx_slot, tx_sloti, tx_count;
67 /* And frame continues.. */
70 #define PRIV_BYTES sizeof(struct mace_data)
72 extern void psc_debug_dump(void);
74 static int mace_open(struct net_device *dev);
75 static int mace_close(struct net_device *dev);
76 static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev);
77 static struct net_device_stats *mace_stats(struct net_device *dev);
78 static void mace_set_multicast(struct net_device *dev);
79 static int mace_set_address(struct net_device *dev, void *addr);
80 static void mace_interrupt(int irq, void *dev_id, struct pt_regs *regs);
81 static void mace_dma_intr(int irq, void *dev_id, struct pt_regs *regs);
82 static void mace_tx_timeout(struct net_device *dev);
84 /* Bit-reverse one byte of an ethernet hardware address. */
86 static int bitrev(int b)
90 for (i = 0; i < 8; ++i, b >>= 1) {
91 d = (d << 1) | (b & 1);
98 * Load a receive DMA channel with a base address and ring length
101 static void mace_load_rxdma_base(struct net_device *dev, int set)
103 struct mace_data *mp = (struct mace_data *) dev->priv;
105 psc_write_word(PSC_ENETRD_CMD + set, 0x0100);
106 psc_write_long(PSC_ENETRD_ADDR + set, (u32) mp->rx_ring_phys);
107 psc_write_long(PSC_ENETRD_LEN + set, N_RX_RING);
108 psc_write_word(PSC_ENETRD_CMD + set, 0x9800);
113 * Reset the receive DMA subsystem
116 static void mace_rxdma_reset(struct net_device *dev)
118 struct mace_data *mp = (struct mace_data *) dev->priv;
119 volatile struct mace *mace = mp->mace;
120 u8 maccc = mace->maccc;
122 mace->maccc = maccc & ~ENRCV;
124 psc_write_word(PSC_ENETRD_CTL, 0x8800);
125 mace_load_rxdma_base(dev, 0x00);
126 psc_write_word(PSC_ENETRD_CTL, 0x0400);
128 psc_write_word(PSC_ENETRD_CTL, 0x8800);
129 mace_load_rxdma_base(dev, 0x10);
130 psc_write_word(PSC_ENETRD_CTL, 0x0400);
135 psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x9800);
136 psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x9800);
140 * Reset the transmit DMA subsystem
143 static void mace_txdma_reset(struct net_device *dev)
145 struct mace_data *mp = (struct mace_data *) dev->priv;
146 volatile struct mace *mace = mp->mace;
149 psc_write_word(PSC_ENETWR_CTL, 0x8800);
152 mace->maccc = maccc & ~ENXMT;
154 mp->tx_slot = mp->tx_sloti = 0;
155 mp->tx_count = N_TX_RING;
157 psc_write_word(PSC_ENETWR_CTL, 0x0400);
165 static void mace_dma_off(struct net_device *dev)
167 psc_write_word(PSC_ENETRD_CTL, 0x8800);
168 psc_write_word(PSC_ENETRD_CTL, 0x1000);
169 psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x1100);
170 psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x1100);
172 psc_write_word(PSC_ENETWR_CTL, 0x8800);
173 psc_write_word(PSC_ENETWR_CTL, 0x1000);
174 psc_write_word(PSC_ENETWR_CMD + PSC_SET0, 0x1100);
175 psc_write_word(PSC_ENETWR_CMD + PSC_SET1, 0x1100);
179 * Not really much of a probe. The hardware table tells us if this
180 * model of Macintrash has a MACE (AV macintoshes)
183 int mace_probe(struct net_device *unused)
186 struct mace_data *mp;
188 struct net_device *dev;
189 unsigned char checksum = 0;
190 static int found = 0;
192 if (found || macintosh_config->ether_type != MAC_ETHER_MACE) return -ENODEV;
194 found = 1; /* prevent 'finding' one on every device probe */
196 dev = init_etherdev(0, PRIV_BYTES);
197 if (!dev) return -ENOMEM;
199 mp = (struct mace_data *) dev->priv;
200 dev->base_addr = (u32)MACE_BASE;
201 mp->mace = (volatile struct mace *) MACE_BASE;
203 dev->irq = IRQ_MAC_MACE;
204 mp->dma_intr = IRQ_MAC_MACE_DMA;
207 * The PROM contains 8 bytes which total 0xFF when XOR'd
208 * together. Due to the usual peculiar apple brain damage
209 * the bytes are spaced out in a strange boundary and the
213 addr = (void *)MACE_PROM;
215 for (j = 0; j < 6; ++j) {
216 u8 v=bitrev(addr[j<<4]);
218 dev->dev_addr[j] = v;
221 checksum ^= bitrev(addr[j<<4]);
224 if (checksum != 0xFF) return -ENODEV;
226 memset(&mp->stats, 0, sizeof(mp->stats));
228 dev->open = mace_open;
229 dev->stop = mace_close;
230 dev->hard_start_xmit = mace_xmit_start;
231 dev->tx_timeout = mace_tx_timeout;
232 dev->watchdog_timeo = TX_TIMEOUT;
233 dev->get_stats = mace_stats;
234 dev->set_multicast_list = mace_set_multicast;
235 dev->set_mac_address = mace_set_address;
239 printk(KERN_INFO "%s: 68K MACE, hardware address %.2X", dev->name, dev->dev_addr[0]);
240 for (j = 1 ; j < 6 ; j++) printk(":%.2X", dev->dev_addr[j]);
247 * Load the address on a mace controller.
250 static int mace_set_address(struct net_device *dev, void *addr)
252 unsigned char *p = addr;
253 struct mace_data *mp = (struct mace_data *) dev->priv;
254 volatile struct mace *mb = mp->mace;
264 /* load up the hardware address */
265 mb->iac = ADDRCHG | PHYADDR;
266 while ((mb->iac & ADDRCHG) != 0);
268 for (i = 0; i < 6; ++i) {
269 mb->padr = dev->dev_addr[i] = p[i];
273 restore_flags(flags);
279 * Open the Macintosh MACE. Most of this is playing with the DMA
280 * engine. The ethernet chip is quite friendly.
283 static int mace_open(struct net_device *dev)
285 struct mace_data *mp = (struct mace_data *) dev->priv;
286 volatile struct mace *mb = mp->mace;
293 if (mb->biucc & SWRST) {
300 printk(KERN_ERR "%s: software reset failed!!\n", dev->name);
305 mb->biucc = XMTSP_64;
306 mb->fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU | XMTBRST | RCVBRST;
307 mb->xmtfc = AUTO_PAD_XMIT;
308 mb->plscc = PORTSEL_AUI;
309 /* mb->utr = RTRD; */
311 if (request_irq(dev->irq, mace_interrupt, 0, dev->name, dev)) {
312 printk(KERN_ERR "%s: can't get irq %d\n", dev->name, dev->irq);
315 if (request_irq(mp->dma_intr, mace_dma_intr, 0, dev->name, dev)) {
316 printk(KERN_ERR "%s: can't get irq %d\n", dev->name, mp->dma_intr);
317 free_irq(dev->irq, dev);
321 /* Allocate the DMA ring buffers */
323 mp->rx_ring = (void *) __get_free_pages(GFP_DMA, N_RX_PAGES);
324 mp->tx_ring = (void *) __get_free_pages(GFP_DMA, 0);
326 if (mp->tx_ring==NULL || mp->rx_ring==NULL) {
327 if (mp->rx_ring) free_pages((u32) mp->rx_ring, N_RX_PAGES);
328 if (mp->tx_ring) free_pages((u32) mp->tx_ring, 0);
329 free_irq(dev->irq, dev);
330 free_irq(mp->dma_intr, dev);
331 printk(KERN_ERR "%s: unable to allocate DMA buffers\n", dev->name);
335 mp->rx_ring_phys = (unsigned char *) virt_to_bus(mp->rx_ring);
336 mp->tx_ring_phys = (unsigned char *) virt_to_bus(mp->tx_ring);
338 /* We want the Rx buffer to be uncached and the Tx buffer to be writethrough */
340 kernel_set_cachemode((void *)mp->rx_ring, N_RX_PAGES * PAGE_SIZE, IOMAP_NOCACHE_NONSER);
341 kernel_set_cachemode((void *)mp->tx_ring, PAGE_SIZE, IOMAP_WRITETHROUGH);
345 /* Not sure what these do */
347 psc_write_word(PSC_ENETWR_CTL, 0x9000);
348 psc_write_word(PSC_ENETRD_CTL, 0x9000);
349 psc_write_word(PSC_ENETWR_CTL, 0x0400);
350 psc_write_word(PSC_ENETRD_CTL, 0x0400);
353 /* load up the hardware address */
355 mb->iac = ADDRCHG | PHYADDR;
357 while ((mb->iac & ADDRCHG) != 0);
359 for (i = 0; i < 6; ++i)
360 mb->padr = dev->dev_addr[i];
362 /* clear the multicast filter */
363 mb->iac = ADDRCHG | LOGADDR;
365 while ((mb->iac & ADDRCHG) != 0);
367 for (i = 0; i < 8; ++i)
370 mb->plscc = PORTSEL_GPSI + ENPLSIO;
372 mb->maccc = ENXMT | ENRCV;
376 mace_rxdma_reset(dev);
377 mace_txdma_reset(dev);
383 * Shut down the mace and its interrupt channel
386 static int mace_close(struct net_device *dev)
388 struct mace_data *mp = (struct mace_data *) dev->priv;
389 volatile struct mace *mb = mp->mace;
391 mb->maccc = 0; /* disable rx and tx */
392 mb->imr = 0xFF; /* disable all irqs */
393 mace_dma_off(dev); /* disable rx and tx dma */
395 free_irq(dev->irq, dev);
396 free_irq(IRQ_MAC_MACE_DMA, dev);
398 free_pages((u32) mp->rx_ring, N_RX_PAGES);
399 free_pages((u32) mp->tx_ring, 0);
408 static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
410 struct mace_data *mp = (struct mace_data *) dev->priv;
412 /* Stop the queue if the buffer is full */
415 netif_stop_queue(dev);
420 mp->stats.tx_packets++;
421 mp->stats.tx_bytes += skb->len;
423 /* We need to copy into our xmit buffer to take care of alignment and caching issues */
425 memcpy((void *) mp->tx_ring, skb->data, skb->len);
427 /* load the Tx DMA and fire it off */
429 psc_write_long(PSC_ENETWR_ADDR + mp->tx_slot, (u32) mp->tx_ring_phys);
430 psc_write_long(PSC_ENETWR_LEN + mp->tx_slot, skb->len);
431 psc_write_word(PSC_ENETWR_CMD + mp->tx_slot, 0x9800);
440 static struct net_device_stats *mace_stats(struct net_device *dev)
442 struct mace_data *p = (struct mace_data *) dev->priv;
446 static void mace_set_multicast(struct net_device *dev)
448 struct mace_data *mp = (struct mace_data *) dev->priv;
449 volatile struct mace *mb = mp->mace;
457 if (dev->flags & IFF_PROMISC) {
460 unsigned char multicast_filter[8];
461 struct dev_mc_list *dmi = dev->mc_list;
463 if (dev->flags & IFF_ALLMULTI) {
464 for (i = 0; i < 8; i++) {
465 multicast_filter[i] = 0xFF;
468 for (i = 0; i < 8; i++) {
469 multicast_filter[i] = 0;
471 for (i = 0; i < dev->mc_count; i++) {
472 crc = ether_crc_le(6, dmi->dmi_addr);
473 j = crc >> 26; /* bit number in multicast_filter */
474 multicast_filter[j >> 3] |= 1 << (j & 7);
479 mb->iac = ADDRCHG | LOGADDR;
480 while (mb->iac & ADDRCHG);
482 for (i = 0; i < 8; ++i) {
483 mb->ladrf = multicast_filter[i];
491 * Miscellaneous interrupts are handled here. We may end up
492 * having to bash the chip on the head for bad errors
495 static void mace_handle_misc_intrs(struct mace_data *mp, int intr)
497 volatile struct mace *mb = mp->mace;
498 static int mace_babbles, mace_jabbers;
501 mp->stats.rx_missed_errors += 256;
503 mp->stats.rx_missed_errors += mb->mpc; /* reading clears it */
506 mp->stats.rx_length_errors += 256;
508 mp->stats.rx_length_errors += mb->rntpc; /* reading clears it */
511 ++mp->stats.tx_heartbeat_errors;
514 if (mace_babbles++ < 4) {
515 printk(KERN_DEBUG "mace: babbling transmitter\n");
519 if (mace_jabbers++ < 4) {
520 printk(KERN_DEBUG "mace: jabbering transceiver\n");
526 * A transmit error has occurred. (We kick the transmit side from
527 * the DMA completion)
530 static void mace_xmit_error(struct net_device *dev)
532 struct mace_data *mp = (struct mace_data *) dev->priv;
533 volatile struct mace *mb = mp->mace;
541 printk("%s: DMA underrun.\n", dev->name);
542 mp->stats.tx_errors++;
543 mp->stats.tx_fifo_errors++;
544 mace_txdma_reset(dev);
547 mp->stats.collisions++;
553 * A receive interrupt occurred.
556 static void mace_recv_interrupt(struct net_device *dev)
558 /* struct mace_data *mp = (struct mace_data *) dev->priv; */
559 // volatile struct mace *mb = mp->mace;
563 * Process the chip interrupt
566 static void mace_interrupt(int irq, void *dev_id, struct pt_regs *regs)
568 struct net_device *dev = (struct net_device *) dev_id;
569 struct mace_data *mp = (struct mace_data *) dev->priv;
570 volatile struct mace *mb = mp->mace;
574 mace_handle_misc_intrs(mp, ir);
577 mace_xmit_error(dev);
580 mace_recv_interrupt(dev);
584 static void mace_tx_timeout(struct net_device *dev)
586 /* struct mace_data *mp = (struct mace_data *) dev->priv; */
587 // volatile struct mace *mb = mp->mace;
591 * Handle a newly arrived frame
594 static void mace_dma_rx_frame(struct net_device *dev, struct mace_frame *mf)
596 struct mace_data *mp = (struct mace_data *) dev->priv;
599 if (mf->status & RS_OFLO) {
600 printk("%s: fifo overflow.\n", dev->name);
601 mp->stats.rx_errors++;
602 mp->stats.rx_fifo_errors++;
604 if (mf->status&(RS_CLSN|RS_FRAMERR|RS_FCSERR))
605 mp->stats.rx_errors++;
607 if (mf->status&RS_CLSN) {
608 mp->stats.collisions++;
610 if (mf->status&RS_FRAMERR) {
611 mp->stats.rx_frame_errors++;
613 if (mf->status&RS_FCSERR) {
614 mp->stats.rx_crc_errors++;
617 skb = dev_alloc_skb(mf->len+2);
619 mp->stats.rx_dropped++;
623 memcpy(skb_put(skb, mf->len), mf->data, mf->len);
626 skb->protocol = eth_type_trans(skb, dev);
628 dev->last_rx = jiffies;
629 mp->stats.rx_packets++;
630 mp->stats.rx_bytes += mf->len;
634 * The PSC has passed us a DMA interrupt event.
637 static void mace_dma_intr(int irq, void *dev_id, struct pt_regs *regs)
639 struct net_device *dev = (struct net_device *) dev_id;
640 struct mace_data *mp = (struct mace_data *) dev->priv;
645 /* Not sure what this does */
647 while ((baka = psc_read_long(PSC_MYSTERY)) != psc_read_long(PSC_MYSTERY));
648 if (!(baka & 0x60000000)) return;
651 * Process the read queue
654 status = psc_read_word(PSC_ENETRD_CTL);
656 if (status & 0x2000) {
657 mace_rxdma_reset(dev);
658 } else if (status & 0x0100) {
659 psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x1100);
661 left = psc_read_long(PSC_ENETRD_LEN + mp->rx_slot);
662 head = N_RX_RING - left;
664 /* Loop through the ring buffer and process new packages */
666 while (mp->rx_tail < head) {
667 mace_dma_rx_frame(dev, (struct mace_frame *) (mp->rx_ring + (mp->rx_tail * 0x0800)));
671 /* If we're out of buffers in this ring then switch to */
672 /* the other set, otherwise just reactivate this one. */
675 mace_load_rxdma_base(dev, mp->rx_slot);
678 psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x9800);
683 * Process the write queue
686 status = psc_read_word(PSC_ENETWR_CTL);
688 if (status & 0x2000) {
689 mace_txdma_reset(dev);
690 } else if (status & 0x0100) {
691 psc_write_word(PSC_ENETWR_CMD + mp->tx_sloti, 0x0100);
692 mp->tx_sloti ^= 0x10;
694 netif_wake_queue(dev);
698 MODULE_LICENSE("GPL");