1 /* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
3 Written/copyright 1999-2001 by Donald Becker.
4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com)
5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com)
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL. License for under other terms may be
13 available. Contact the original author for details.
15 The original author may be reached as becker@scyld.com, or at
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
20 Support information and updates available at
21 http://www.scyld.com/network/netsemi.html
24 Linux kernel modifications:
28 - Bug fixes and better intr performance (Tjeerd)
30 - Now reads correct MAC address from eeprom
32 - Eliminate redundant priv->tx_full flag
33 - Call netif_start_queue from dev->tx_timeout
34 - wmb() in start_tx() to flush data
36 - Clean up PCI enable (davej)
38 - Merge Donald Becker's natsemi.c version 1.07
42 * ethtool support (jgarzik)
43 * Proper initialization of the card (which sometimes
44 fails to occur and leaves the card in a non-functional
47 * Some documented register settings to optimize some
48 of the 100Mbit autodetection circuitry in rev C cards. (uzi)
50 * Polling of the PHY intr for stuff like link state
51 change and auto- negotiation to finally work properly. (uzi)
53 * One-liner removal of a duplicate declaration of
56 Version 1.0.7: (Manfred Spraul)
59 * full reset added into tx_timeout
60 * correct multicast hash generation (both big and little endian)
61 [copied from a natsemi driver version
62 from Myrio Corporation, Greg Smith]
65 version 1.0.8 (Tim Hockin <thockin@sun.com>)
67 * Wake on lan support (Erik Gilling)
68 * MXDMA fixes for serverworks
71 version 1.0.9 (Manfred Spraul)
72 * Main change: fix lack of synchronize
73 netif_close/netif_suspend against a last interrupt
75 * do not enable superflous interrupts (e.g. the
76 drivers relies on TxDone - TxIntr not needed)
77 * wait that the hardware has really stopped in close
79 * workaround for the (at least) gcc-2.95.1 compiler
80 problem. Also simplifies the code a bit.
81 * disable_irq() in tx_timeout - needed to protect
82 against rx interrupts.
83 * stop the nic before switching into silent rx mode
84 for wol (required according to docu).
87 * use long for ee_addr (various)
88 * print pointers properly (DaveM)
89 * include asm/irq.h (?)
92 * check and reset if PHY errors appear (Adrian Sun)
93 * WoL cleanup (Tim Hockin)
94 * Magic number cleanup (Tim Hockin)
95 * Don't reload EEPROM on every reset (Tim Hockin)
96 * Save and restore EEPROM state across reset (Tim Hockin)
97 * MDIO Cleanup (Tim Hockin)
98 * Reformat register offsets/bits (jgarzik)
101 * ETHTOOL_* further support (Tim Hockin)
104 * ETHTOOL_[G]EEPROM support (Tim Hockin)
107 * crc cleanup (Matt Domsch <Matt_Domsch@dell.com>)
110 * Cleanup some messages and autoneg in ethtool (Tim Hockin)
113 * Get rid of cable_magic flag
114 * use new (National provided) solution for cable magic issue
117 * call netdev_rx() for RxErrors (Manfred Spraul)
118 * formatting and cleanups
119 * change options and full_duplex arrays to be zero
121 * enable only the WoL and PHY interrupts in wol mode
124 * only do cable_magic on 83815 and early 83816 (Tim Hockin)
125 * create a function for rx refill (Manfred Spraul)
126 * combine drain_ring and init_ring (Manfred Spraul)
127 * oom handling (Manfred Spraul)
128 * hands_off instead of playing with netif_device_{de,a}ttach
130 * be sure to write the MAC back to the chip (Manfred Spraul)
131 * lengthen EEPROM timeout, and always warn about timeouts
133 * comments update (Manfred)
134 * do the right thing on a phy-reset (Manfred and Tim)
137 * big endian support with CFG:BEM instead of cpu_to_le32
138 * support for an external PHY
142 #if !defined(__OPTIMIZE__)
143 #warning You must compile this file with the correct options!
144 #warning See the last lines of the source file.
145 #error You must compile this driver with "-O".
148 #include <linux/config.h>
149 #include <linux/module.h>
150 #include <linux/kernel.h>
151 #include <linux/string.h>
152 #include <linux/timer.h>
153 #include <linux/errno.h>
154 #include <linux/ioport.h>
155 #include <linux/slab.h>
156 #include <linux/interrupt.h>
157 #include <linux/pci.h>
158 #include <linux/netdevice.h>
159 #include <linux/etherdevice.h>
160 #include <linux/skbuff.h>
161 #include <linux/init.h>
162 #include <linux/spinlock.h>
163 #include <linux/ethtool.h>
164 #include <linux/delay.h>
165 #include <linux/rtnetlink.h>
166 #include <linux/mii.h>
167 #include <asm/processor.h> /* Processor type for cache alignment. */
168 #include <asm/bitops.h>
171 #include <asm/uaccess.h>
173 #define DRV_NAME "natsemi"
174 #define DRV_VERSION "1.07+LK1.0.17"
175 #define DRV_RELDATE "Sep 27, 2002"
177 /* Updated to recommendations in pci-skeleton v2.03. */
179 /* The user-configurable values.
180 These may be modified when a driver module is loaded.*/
182 #define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
187 static int debug = -1;
189 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
190 static int max_interrupt_work = 20;
193 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
194 This chip uses a 512 element hash table based on the Ethernet CRC. */
195 static int multicast_filter_limit = 100;
197 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
198 Setting to > 1518 effectively disables this feature. */
199 static int rx_copybreak;
201 /* Used to pass the media type, etc.
202 Both 'options[]' and 'full_duplex[]' should exist for driver
204 The media type is usually passed in 'options[]'.
206 #define MAX_UNITS 8 /* More are supported, limit only on options */
207 static int options[MAX_UNITS];
208 static int full_duplex[MAX_UNITS];
210 /* Operational parameters that are set at compile time. */
212 /* Keep the ring sizes a power of two for compile efficiency.
213 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
214 Making the Tx ring too large decreases the effectiveness of channel
215 bonding and packet priority.
216 There are no ill effects from too-large receive rings. */
217 #define TX_RING_SIZE 16
218 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
219 #define RX_RING_SIZE 32
221 /* Operational parameters that usually are not changed. */
222 /* Time in jiffies before concluding the transmitter is hung. */
223 #define TX_TIMEOUT (2*HZ)
225 #define NATSEMI_HW_TIMEOUT 400
226 #define NATSEMI_TIMER_FREQ 3*HZ
227 #define NATSEMI_PG0_NREGS 64
228 #define NATSEMI_RFDR_NREGS 8
229 #define NATSEMI_PG1_NREGS 4
230 #define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
232 #define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */
233 #define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
234 #define NATSEMI_EEPROM_SIZE 24 /* 12 16-bit values */
236 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
238 /* These identify the driver base version and may not be removed. */
239 static char version[] __devinitdata =
240 KERN_INFO DRV_NAME " dp8381x driver, version "
241 DRV_VERSION ", " DRV_RELDATE "\n"
242 KERN_INFO " originally by Donald Becker <becker@scyld.com>\n"
243 KERN_INFO " http://www.scyld.com/network/natsemi.html\n"
244 KERN_INFO " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
246 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
247 MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
248 MODULE_LICENSE("GPL");
250 MODULE_PARM(max_interrupt_work, "i");
251 MODULE_PARM(mtu, "i");
252 MODULE_PARM(debug, "i");
253 MODULE_PARM(rx_copybreak, "i");
254 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
255 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
256 MODULE_PARM_DESC(max_interrupt_work,
257 "DP8381x maximum events handled per interrupt");
258 MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
259 MODULE_PARM_DESC(debug, "DP8381x default debug level");
260 MODULE_PARM_DESC(rx_copybreak,
261 "DP8381x copy breakpoint for copy-only-tiny-frames");
262 MODULE_PARM_DESC(options,
263 "DP8381x: Bits 0-3: media type, bit 17: full duplex");
264 MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
269 I. Board Compatibility
271 This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
272 It also works with other chips in in the DP83810 series.
274 II. Board-specific settings
276 This driver requires the PCI interrupt line to be valid.
277 It honors the EEPROM-set values.
279 III. Driver operation
283 This driver uses two statically allocated fixed-size descriptor lists
284 formed into rings by a branch from the final descriptor to the beginning of
285 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
286 The NatSemi design uses a 'next descriptor' pointer that the driver forms
289 IIIb/c. Transmit/Receive Structure
291 This driver uses a zero-copy receive and transmit scheme.
292 The driver allocates full frame size skbuffs for the Rx ring buffers at
293 open() time and passes the skb->data field to the chip as receive data
294 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
295 a fresh skbuff is allocated and the frame is copied to the new skbuff.
296 When the incoming frame is larger, the skbuff is passed directly up the
297 protocol stack. Buffers consumed this way are replaced by newly allocated
298 skbuffs in a later phase of receives.
300 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
301 using a full-sized skbuff for small frames vs. the copying costs of larger
302 frames. New boards are typically used in generously configured machines
303 and the underfilled buffers have negligible impact compared to the benefit of
304 a single allocation size, so the default value of zero results in never
305 copying packets. When copying is done, the cost is usually mitigated by using
306 a combined copy/checksum routine. Copying also preloads the cache, which is
307 most useful with small frames.
309 A subtle aspect of the operation is that unaligned buffers are not permitted
310 by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
311 longword aligned for further processing. On copies frames are put into the
312 skbuff at an offset of "+2", 16-byte aligning the IP header.
314 IIId. Synchronization
316 Most operations are synchronized on the np->lock irq spinlock, except the
317 performance critical codepaths:
319 The rx process only runs in the interrupt handler. Access from outside
320 the interrupt handler is only permitted after disable_irq().
322 The rx process usually runs under the dev->xmit_lock. If np->intr_tx_reap
323 is set, then access is permitted under spin_lock_irq(&np->lock).
325 Thus configuration functions that want to access everything must call
326 disable_irq(dev->irq);
327 spin_lock_bh(dev->xmit_lock);
328 spin_lock_irq(&np->lock);
332 NatSemi PCI network controllers are very uncommon.
336 http://www.scyld.com/expert/100mbps.html
337 http://www.scyld.com/expert/NWay.html
338 Datasheet is available from:
339 http://www.national.com/pf/DP/DP83815.html
351 PCI_USES_MASTER = 0x04,
356 /* MMIO operations required */
357 #define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_MEM | PCI_ADDR1)
360 /* array of board data directly indexed by pci_tbl[x].driver_data */
364 } natsemi_pci_info[] __devinitdata = {
365 { "NatSemi DP8381[56]", PCI_IOTYPE },
368 static struct pci_device_id natsemi_pci_tbl[] __devinitdata = {
369 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID, PCI_ANY_ID, },
372 MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
374 /* Offsets to the device registers.
375 Unlike software-only systems, device drivers interact with complex hardware.
376 It's not useful to define symbolic names for every register bit in the
379 enum register_offsets {
387 IntrHoldoff = 0x16, /* DP83816 only */
414 /* These are from the spec, around page 78... on a separate table.
415 * The meaning of these registers depend on the value of PGSEL. */
422 /* the values for the 'magic' registers above (PGSEL=1) */
423 #define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
424 #define TSTDAT_VAL 0x0
425 #define DSPCFG_VAL 0x5040
426 #define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
427 #define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
428 #define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
430 /* misc PCI space registers */
431 enum pci_register_offsets {
445 enum ChipConfig_bits {
449 CfgAnegEnable = 0x2000,
451 CfgAnegFull = 0x8000,
452 CfgAnegDone = 0x8000000,
453 CfgFullDuplex = 0x20000000,
454 CfgSpeed100 = 0x40000000,
455 CfgLink = 0x80000000,
461 EE_ChipSelect = 0x08,
465 enum PCIBusCfg_bits {
469 /* Bits in the interrupt status/mask registers. */
470 enum IntrStatus_bits {
474 IntrRxEarly = 0x0008,
476 IntrRxOverrun = 0x0020,
481 IntrTxUnderrun = 0x0400,
486 IntrHighBits = 0x8000,
487 RxStatusFIFOOver = 0x10000,
488 IntrPCIErr = 0xf00000,
489 RxResetDone = 0x1000000,
490 TxResetDone = 0x2000000,
491 IntrAbnormalSummary = 0xCD20,
495 * Default Interrupts:
496 * Rx OK, Rx Packet Error, Rx Overrun,
497 * Tx OK, Tx Packet Error, Tx Underrun,
498 * MIB Service, Phy Interrupt, High Bits,
499 * Rx Status FIFO overrun,
500 * Received Target Abort, Received Master Abort,
501 * Signalled System Error, Received Parity Error
503 #define DEFAULT_INTR 0x00f1cd65
508 TxMxdmaMask = 0x700000,
510 TxMxdma_4 = 0x100000,
511 TxMxdma_8 = 0x200000,
512 TxMxdma_16 = 0x300000,
513 TxMxdma_32 = 0x400000,
514 TxMxdma_64 = 0x500000,
515 TxMxdma_128 = 0x600000,
516 TxMxdma_256 = 0x700000,
517 TxCollRetry = 0x800000,
518 TxAutoPad = 0x10000000,
519 TxMacLoop = 0x20000000,
520 TxHeartIgn = 0x40000000,
521 TxCarrierIgn = 0x80000000
526 RxMxdmaMask = 0x700000,
528 RxMxdma_4 = 0x100000,
529 RxMxdma_8 = 0x200000,
530 RxMxdma_16 = 0x300000,
531 RxMxdma_32 = 0x400000,
532 RxMxdma_64 = 0x500000,
533 RxMxdma_128 = 0x600000,
534 RxMxdma_256 = 0x700000,
535 RxAcceptLong = 0x8000000,
536 RxAcceptTx = 0x10000000,
537 RxAcceptRunt = 0x40000000,
538 RxAcceptErr = 0x80000000
557 WakeMagicSecure = 0x400,
558 SecureHack = 0x100000,
560 WokeUnicast = 0x800000,
561 WokeMulticast = 0x1000000,
562 WokeBroadcast = 0x2000000,
564 WokePMatch0 = 0x8000000,
565 WokePMatch1 = 0x10000000,
566 WokePMatch2 = 0x20000000,
567 WokePMatch3 = 0x40000000,
568 WokeMagic = 0x80000000,
569 WakeOptsSummary = 0x7ff
572 enum RxFilterAddr_bits {
573 RFCRAddressMask = 0x3ff,
574 AcceptMulticast = 0x00200000,
575 AcceptMyPhys = 0x08000000,
576 AcceptAllPhys = 0x10000000,
577 AcceptAllMulticast = 0x20000000,
578 AcceptBroadcast = 0x40000000,
579 RxFilterEnable = 0x80000000
582 enum StatsCtrl_bits {
589 enum MIntrCtrl_bits {
597 /* values we might find in the silicon revision register */
598 #define SRR_DP83815_C 0x0302
599 #define SRR_DP83815_D 0x0403
600 #define SRR_DP83816_A4 0x0504
601 #define SRR_DP83816_A5 0x0505
603 /* The Rx and Tx buffer descriptors. */
604 /* Note that using only 32 bit fields simplifies conversion to big-endian
613 /* Bits in network_desc.status */
614 enum desc_status_bits {
615 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
616 DescNoCRC=0x10000000, DescPktOK=0x08000000,
619 DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
620 DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
621 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
622 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
624 DescRxAbort=0x04000000, DescRxOver=0x02000000,
625 DescRxDest=0x01800000, DescRxLong=0x00400000,
626 DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
627 DescRxCRC=0x00080000, DescRxAlign=0x00040000,
628 DescRxLoop=0x00020000, DesRxColl=0x00010000,
631 struct netdev_private {
632 /* Descriptor rings first for alignment */
634 struct netdev_desc *rx_ring;
635 struct netdev_desc *tx_ring;
636 /* The addresses of receive-in-place skbuffs */
637 struct sk_buff *rx_skbuff[RX_RING_SIZE];
638 dma_addr_t rx_dma[RX_RING_SIZE];
639 /* address of a sent-in-place packet/buffer, for later free() */
640 struct sk_buff *tx_skbuff[TX_RING_SIZE];
641 dma_addr_t tx_dma[TX_RING_SIZE];
642 struct net_device_stats stats;
643 /* Media monitoring timer */
644 struct timer_list timer;
645 /* Frequently used values: keep some adjacent for cache effect */
646 struct pci_dev *pci_dev;
647 struct netdev_desc *rx_head_desc;
648 /* Producer/consumer ring indices */
649 unsigned int cur_rx, dirty_rx;
650 unsigned int cur_tx, dirty_tx;
651 /* Based on MTU+slack. */
652 unsigned int rx_buf_sz;
654 /* Do not touch the nic registers */
656 /* These values are keep track of the transceiver/media in use */
657 unsigned int full_duplex;
661 /* FIFO and PCI burst thresholds */
662 u32 tx_config, rx_config;
663 /* original contents of ClkRun register */
665 /* silicon revision */
667 /* expected DSPCFG value */
669 /* MII transceiver section */
676 static int eeprom_read(long ioaddr, int location);
677 static int mdio_read(struct net_device *dev, int phy_id, int reg);
678 static void mdio_write(struct net_device *dev, int phy_id, int reg, u16 data);
679 static void natsemi_reset(struct net_device *dev);
680 static void natsemi_reload_eeprom(struct net_device *dev);
681 static void natsemi_stop_rxtx(struct net_device *dev);
682 static int netdev_open(struct net_device *dev);
683 static void do_cable_magic(struct net_device *dev);
684 static void undo_cable_magic(struct net_device *dev);
685 static void check_link(struct net_device *dev);
686 static void netdev_timer(unsigned long data);
687 static void dump_ring(struct net_device *dev);
688 static void tx_timeout(struct net_device *dev);
689 static int alloc_ring(struct net_device *dev);
690 static void refill_rx(struct net_device *dev);
691 static void init_ring(struct net_device *dev);
692 static void drain_tx(struct net_device *dev);
693 static void drain_ring(struct net_device *dev);
694 static void free_ring(struct net_device *dev);
695 static void reinit_ring(struct net_device *dev);
696 static void init_registers(struct net_device *dev);
697 static int start_tx(struct sk_buff *skb, struct net_device *dev);
698 static void intr_handler(int irq, void *dev_instance, struct pt_regs *regs);
699 static void netdev_error(struct net_device *dev, int intr_status);
700 static void netdev_rx(struct net_device *dev);
701 static void netdev_tx_done(struct net_device *dev);
702 static void __set_rx_mode(struct net_device *dev);
703 static void set_rx_mode(struct net_device *dev);
704 static void __get_stats(struct net_device *dev);
705 static struct net_device_stats *get_stats(struct net_device *dev);
706 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
707 static int netdev_set_wol(struct net_device *dev, u32 newval);
708 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
709 static int netdev_set_sopass(struct net_device *dev, u8 *newval);
710 static int netdev_get_sopass(struct net_device *dev, u8 *data);
711 static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
712 static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
713 static void enable_wol_mode(struct net_device *dev, int enable_intr);
714 static int netdev_close(struct net_device *dev);
715 static int netdev_get_regs(struct net_device *dev, u8 *buf);
716 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
719 static int __devinit natsemi_probe1 (struct pci_dev *pdev,
720 const struct pci_device_id *ent)
722 struct net_device *dev;
723 struct netdev_private *np;
724 int i, option, irq, chip_idx = ent->driver_data;
725 static int find_cnt = -1;
726 unsigned long ioaddr, iosize;
727 const int pcibar = 1; /* PCI base address register */
731 /* when built into the kernel, we only print version if device is found */
733 static int printed_version;
734 if (!printed_version++)
738 i = pci_enable_device(pdev);
741 /* natsemi has a non-standard PM control register
742 * in PCI config space. Some boards apparently need
743 * to be brought to D0 in this manner.
745 pci_read_config_dword(pdev, PCIPM, &tmp);
746 if (tmp & PCI_PM_CTRL_STATE_MASK) {
747 /* D0 state, disable PME assertion */
748 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
749 pci_write_config_dword(pdev, PCIPM, newtmp);
753 ioaddr = pci_resource_start(pdev, pcibar);
754 iosize = pci_resource_len(pdev, pcibar);
757 //irq = 0x3;//The USI board
759 if (natsemi_pci_info[chip_idx].flags & PCI_USES_MASTER)
760 pci_set_master(pdev);
762 dev = alloc_etherdev(sizeof (struct netdev_private));
765 SET_MODULE_OWNER(dev);
767 i = pci_request_regions(pdev, dev->name);
774 void *mmio = ioremap (ioaddr, iosize);
776 pci_release_regions(pdev);
780 ioaddr = (unsigned long) mmio;
783 /* Work around the dropped serial bit. */
784 prev_eedata = eeprom_read(ioaddr, 6);
785 for (i = 0; i < 3; i++) {
786 int eedata = eeprom_read(ioaddr, i + 7);
787 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
788 dev->dev_addr[i*2+1] = eedata >> 7;
789 prev_eedata = eedata;
792 dev->base_addr = ioaddr;
798 pci_set_drvdata(pdev, dev);
800 spin_lock_init(&np->lock);
801 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
804 /* Reset the chip to erase previous misconfiguration. */
805 natsemi_reload_eeprom(dev);
808 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
810 option = dev->mem_start;
812 /* The lower four bits are the media type. */
818 "%s: ignoring user supplied media type %d",
819 dev->name, option & 15);
821 if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
824 /* The chip-specific entries in the device structure. */
825 dev->open = &netdev_open;
826 dev->hard_start_xmit = &start_tx;
827 dev->stop = &netdev_close;
828 dev->get_stats = &get_stats;
829 dev->set_multicast_list = &set_rx_mode;
830 dev->do_ioctl = &netdev_ioctl;
831 dev->tx_timeout = &tx_timeout;
832 dev->watchdog_timeo = TX_TIMEOUT;
837 i = register_netdev(dev);
839 pci_release_regions(pdev);
840 unregister_netdev(dev);
842 pci_set_drvdata(pdev, NULL);
845 netif_carrier_off(dev);
847 if (netif_msg_drv(np)) {
848 printk(KERN_INFO "%s: %s at %#08lx, ",
849 dev->name, natsemi_pci_info[chip_idx].name, ioaddr);
850 for (i = 0; i < ETH_ALEN-1; i++)
851 printk("%02x:", dev->dev_addr[i]);
852 printk("%02x, IRQ %d.\n", dev->dev_addr[i], irq);
855 np->advertising = mdio_read(dev, 1, MII_ADVERTISE);
856 if ((readl(ioaddr + ChipConfig) & 0xe000) != 0xe000
857 && netif_msg_probe(np)) {
858 u32 chip_config = readl(ioaddr + ChipConfig);
859 printk(KERN_INFO "%s: Transceiver default autonegotiation %s "
862 chip_config & CfgAnegEnable ?
863 "enabled, advertise" : "disabled, force",
864 chip_config & CfgAneg100 ? "0" : "",
865 chip_config & CfgAnegFull ? "full" : "half");
867 if (netif_msg_probe(np))
869 "%s: Transceiver status %#04x advertising %#04x.\n",
870 dev->name, mdio_read(dev, 1, MII_BMSR),
873 /* save the silicon revision for later querying */
874 np->srr = readl(ioaddr + SiliconRev);
875 if (netif_msg_hw(np))
876 printk(KERN_INFO "%s: silicon revision %#04x.\n",
884 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
885 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
887 /* Delay between EEPROM clock transitions.
888 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
889 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
890 made udelay() unreliable.
891 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
894 #define eeprom_delay(ee_addr) readl(ee_addr)
896 #define EE_Write0 (EE_ChipSelect)
897 #define EE_Write1 (EE_ChipSelect | EE_DataIn)
899 /* The EEPROM commands include the alway-set leading bit. */
901 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
904 static int eeprom_read(long addr, int location)
908 long ee_addr = addr + EECtrl;
909 int read_cmd = location | EE_ReadCmd;
910 writel(EE_Write0, ee_addr);
912 /* Shift the read command bits out. */
913 for (i = 10; i >= 0; i--) {
914 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
915 writel(dataval, ee_addr);
916 eeprom_delay(ee_addr);
917 writel(dataval | EE_ShiftClk, ee_addr);
918 eeprom_delay(ee_addr);
920 writel(EE_ChipSelect, ee_addr);
921 eeprom_delay(ee_addr);
923 for (i = 0; i < 16; i++) {
924 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
925 eeprom_delay(ee_addr);
926 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
927 writel(EE_ChipSelect, ee_addr);
928 eeprom_delay(ee_addr);
931 /* Terminate the EEPROM access. */
932 writel(EE_Write0, ee_addr);
937 /* MII transceiver control section.
938 * The 83815 series has an internal transceiver, and we present the
939 * management registers as if they were MII connected. */
941 static int mdio_read(struct net_device *dev, int phy_id, int reg)
943 if (phy_id == 1 && reg < 32)
944 return readl(dev->base_addr+BasicControl+(reg<<2))&0xffff;
949 static void mdio_write(struct net_device *dev, int phy_id, int reg, u16 data)
951 struct netdev_private *np = dev->priv;
952 if (phy_id == 1 && reg < 32) {
953 writew(data, dev->base_addr+BasicControl+(reg<<2));
955 case MII_ADVERTISE: np->advertising = data; break;
960 /* CFG bits [13:16] [18:23] */
961 #define CFG_RESET_SAVE 0xfde000
962 /* WCSR bits [0:4] [9:10] */
963 #define WCSR_RESET_SAVE 0x61f
964 /* RFCR bits [20] [22] [27:31] */
965 #define RFCR_RESET_SAVE 0xf8500000;
967 static void natsemi_reset(struct net_device *dev)
975 struct netdev_private *np = dev->priv;
978 * Resetting the chip causes some registers to be lost.
979 * Natsemi suggests NOT reloading the EEPROM while live, so instead
980 * we save the state that would have been loaded from EEPROM
981 * on a normal power-up (see the spec EEPROM map). This assumes
982 * whoever calls this will follow up with init_registers() eventually.
986 cfg = readl(dev->base_addr + ChipConfig) & CFG_RESET_SAVE;
988 wcsr = readl(dev->base_addr + WOLCmd) & WCSR_RESET_SAVE;
990 rfcr = readl(dev->base_addr + RxFilterAddr) & RFCR_RESET_SAVE;
992 for (i = 0; i < 3; i++) {
993 writel(i*2, dev->base_addr + RxFilterAddr);
994 pmatch[i] = readw(dev->base_addr + RxFilterData);
997 for (i = 0; i < 3; i++) {
998 writel(0xa+(i*2), dev->base_addr + RxFilterAddr);
999 sopass[i] = readw(dev->base_addr + RxFilterData);
1002 /* now whack the chip */
1003 writel(ChipReset, dev->base_addr + ChipCmd);
1004 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1005 if (!(readl(dev->base_addr + ChipCmd) & ChipReset))
1009 if (i==NATSEMI_HW_TIMEOUT) {
1010 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
1012 } else if (netif_msg_hw(np)) {
1013 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
1018 cfg |= readl(dev->base_addr + ChipConfig) & ~CFG_RESET_SAVE;
1019 writel(cfg, dev->base_addr + ChipConfig);
1021 wcsr |= readl(dev->base_addr + WOLCmd) & ~WCSR_RESET_SAVE;
1022 writel(wcsr, dev->base_addr + WOLCmd);
1024 rfcr |= readl(dev->base_addr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1025 /* restore PMATCH */
1026 for (i = 0; i < 3; i++) {
1027 writel(i*2, dev->base_addr + RxFilterAddr);
1028 writew(pmatch[i], dev->base_addr + RxFilterData);
1030 for (i = 0; i < 3; i++) {
1031 writel(0xa+(i*2), dev->base_addr + RxFilterAddr);
1032 writew(sopass[i], dev->base_addr + RxFilterData);
1035 writel(rfcr, dev->base_addr + RxFilterAddr);
1038 static void natsemi_reload_eeprom(struct net_device *dev)
1040 struct netdev_private *np = dev->priv;
1043 writel(EepromReload, dev->base_addr + PCIBusCfg);
1044 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1046 if (!(readl(dev->base_addr + PCIBusCfg) & EepromReload))
1049 if (i==NATSEMI_HW_TIMEOUT) {
1050 printk(KERN_WARNING "%s: EEPROM did not reload in %d usec.\n",
1052 } else if (netif_msg_hw(np)) {
1053 printk(KERN_DEBUG "%s: EEPROM reloaded in %d usec.\n",
1058 static void natsemi_stop_rxtx(struct net_device *dev)
1060 long ioaddr = dev->base_addr;
1061 struct netdev_private *np = dev->priv;
1064 writel(RxOff | TxOff, ioaddr + ChipCmd);
1065 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1066 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1070 if (i==NATSEMI_HW_TIMEOUT) {
1071 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
1073 } else if (netif_msg_hw(np)) {
1074 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1079 static int netdev_open(struct net_device *dev)
1081 struct netdev_private *np = dev->priv;
1082 long ioaddr = dev->base_addr;
1085 /* Reset the chip, just in case. */
1088 i = request_irq(dev->irq, &intr_handler, SA_SHIRQ, dev->name, dev);
1091 if (netif_msg_ifup(np))
1092 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
1093 dev->name, dev->irq);
1094 i = alloc_ring(dev);
1096 free_irq(dev->irq, dev);
1100 spin_lock_irq(&np->lock);
1101 init_registers(dev);
1102 /* now set the MAC address according to dev->dev_addr */
1103 for (i = 0; i < 3; i++) {
1104 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
1106 writel(i*2, ioaddr + RxFilterAddr);
1107 writew(mac, ioaddr + RxFilterData);
1109 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1110 spin_unlock_irq(&np->lock);
1112 netif_start_queue(dev);
1114 if (netif_msg_ifup(np))
1115 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
1116 dev->name, (int)readl(ioaddr + ChipCmd));
1118 /* Set the timer to check for link beat. */
1119 init_timer(&np->timer);
1120 np->timer.expires = jiffies + NATSEMI_TIMER_FREQ;
1121 np->timer.data = (unsigned long)dev;
1122 np->timer.function = &netdev_timer; /* timer handler */
1123 add_timer(&np->timer);
1128 static void do_cable_magic(struct net_device *dev)
1130 struct netdev_private *np = dev->priv;
1132 if (np->srr >= SRR_DP83816_A5)
1136 * 100 MBit links with short cables can trip an issue with the chip.
1137 * The problem manifests as lots of CRC errors and/or flickering
1138 * activity LED while idle. This process is based on instructions
1139 * from engineers at National.
1141 if (readl(dev->base_addr + ChipConfig) & CfgSpeed100) {
1144 writew(1, dev->base_addr + PGSEL);
1146 * coefficient visibility should already be enabled via
1149 data = readw(dev->base_addr + TSTDAT) & 0xff;
1151 * the value must be negative, and within certain values
1152 * (these values all come from National)
1154 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
1155 struct netdev_private *np = dev->priv;
1157 /* the bug has been triggered - fix the coefficient */
1158 writew(TSTDAT_FIXED, dev->base_addr + TSTDAT);
1159 /* lock the value */
1160 data = readw(dev->base_addr + DSPCFG);
1161 np->dspcfg = data | DSPCFG_LOCK;
1162 writew(np->dspcfg, dev->base_addr + DSPCFG);
1164 writew(0, dev->base_addr + PGSEL);
1168 static void undo_cable_magic(struct net_device *dev)
1171 struct netdev_private *np = dev->priv;
1173 if (np->srr >= SRR_DP83816_A5)
1176 writew(1, dev->base_addr + PGSEL);
1177 /* make sure the lock bit is clear */
1178 data = readw(dev->base_addr + DSPCFG);
1179 np->dspcfg = data & ~DSPCFG_LOCK;
1180 writew(np->dspcfg, dev->base_addr + DSPCFG);
1181 writew(0, dev->base_addr + PGSEL);
1184 static void check_link(struct net_device *dev)
1186 struct netdev_private *np = dev->priv;
1187 long ioaddr = dev->base_addr;
1189 int chipcfg = readl(ioaddr + ChipConfig);
1191 if (!(chipcfg & CfgLink)) {
1192 if (netif_carrier_ok(dev)) {
1193 if (netif_msg_link(np))
1194 printk(KERN_NOTICE "%s: link down.\n",
1196 netif_carrier_off(dev);
1197 undo_cable_magic(dev);
1201 if (!netif_carrier_ok(dev)) {
1202 if (netif_msg_link(np))
1203 printk(KERN_NOTICE "%s: link up.\n", dev->name);
1204 netif_carrier_on(dev);
1205 do_cable_magic(dev);
1208 duplex = np->full_duplex || (chipcfg & CfgFullDuplex ? 1 : 0);
1210 /* if duplex is set then bit 28 must be set, too */
1211 if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
1212 if (netif_msg_link(np))
1214 "%s: Setting %s-duplex based on negotiated "
1215 "link capability.\n", dev->name,
1216 duplex ? "full" : "half");
1218 np->rx_config |= RxAcceptTx;
1219 np->tx_config |= TxCarrierIgn | TxHeartIgn;
1221 np->rx_config &= ~RxAcceptTx;
1222 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
1224 writel(np->tx_config, ioaddr + TxConfig);
1225 writel(np->rx_config, ioaddr + RxConfig);
1229 static void init_registers(struct net_device *dev)
1231 struct netdev_private *np = dev->priv;
1232 long ioaddr = dev->base_addr;
1235 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1236 if (readl(dev->base_addr + ChipConfig) & CfgAnegDone)
1240 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
1242 "%s: autonegotiation did not complete in %d usec.\n",
1246 /* On page 78 of the spec, they recommend some settings for "optimum
1247 performance" to be done in sequence. These settings optimize some
1248 of the 100Mbit autodetection circuitry. They say we only want to
1249 do this for rev C of the chip, but engineers at NSC (Bradley
1250 Kennedy) recommends always setting them. If you don't, you get
1251 errors on some autonegotiations that make the device unusable.
1253 writew(1, ioaddr + PGSEL);
1254 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1255 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1256 writew(DSPCFG_VAL, ioaddr + DSPCFG);
1257 writew(SDCFG_VAL, ioaddr + SDCFG);
1258 writew(0, ioaddr + PGSEL);
1259 np->dspcfg = DSPCFG_VAL;
1261 /* Enable PHY Specific event based interrupts. Link state change
1262 and Auto-Negotiation Completion are among the affected.
1263 Read the intr status to clear it (needed for wake events).
1265 readw(ioaddr + MIntrStatus);
1266 writew(MICRIntEn, ioaddr + MIntrCtrl);
1268 /* clear any interrupts that are pending, such as wake events */
1269 readl(ioaddr + IntrStatus);
1271 writel(np->ring_dma, ioaddr + RxRingPtr);
1272 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
1273 ioaddr + TxRingPtr);
1275 /* Initialize other registers.
1276 * Configure the PCI bus bursts and FIFO thresholds.
1277 * Configure for standard, in-spec Ethernet.
1278 * Start with half-duplex. check_link will update
1279 * to the correct settings.
1282 /* DRTH: 2: start tx if 64 bytes are in the fifo
1283 * FLTH: 0x10: refill with next packet if 512 bytes are free
1284 * MXDMA: 0: up to 256 byte bursts.
1285 * MXDMA must be <= FLTH
1289 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 | (0x1002);
1290 writel(np->tx_config, ioaddr + TxConfig);
1292 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
1293 * MXDMA 0: up to 256 byte bursts
1295 np->rx_config = RxMxdma_256 | 0x20;
1296 writel(np->rx_config, ioaddr + RxConfig);
1299 * The PME bit is initialized from the EEPROM contents.
1300 * PCI cards probably have PME disabled, but motherboard
1301 * implementations may have PME set to enable WakeOnLan.
1302 * With PME set the chip will scan incoming packets but
1303 * nothing will be written to memory. */
1304 np->SavedClkRun = readl(ioaddr + ClkRun);
1305 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1306 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
1307 printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
1308 dev->name, readl(ioaddr + WOLCmd));
1314 /* Enable interrupts by setting the interrupt mask. */
1315 writel(DEFAULT_INTR, ioaddr + IntrMask);
1316 writel(1, ioaddr + IntrEnable);
1318 writel(RxOn | TxOn, ioaddr + ChipCmd);
1319 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
1325 * 1) check for link changes. Usually they are handled by the MII interrupt
1326 * but it doesn't hurt to check twice.
1327 * 2) check for sudden death of the NIC:
1328 * It seems that a reference set for this chip went out with incorrect info,
1329 * and there exist boards that aren't quite right. An unexpected voltage
1330 * drop can cause the PHY to get itself in a weird state (basically reset).
1331 * NOTE: this only seems to affect revC chips.
1332 * 3) check of death of the RX path due to OOM
1334 static void netdev_timer(unsigned long data)
1336 struct net_device *dev = (struct net_device *)data;
1337 struct netdev_private *np = dev->priv;
1338 int next_tick = 5*HZ;
1339 long ioaddr = dev->base_addr;
1342 if (netif_msg_timer(np)) {
1343 /* DO NOT read the IntrStatus register,
1344 * a read clears any pending interrupts.
1346 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
1350 spin_lock_irq(&np->lock);
1352 /* check for a nasty random phy-reset - use dspcfg as a flag */
1353 writew(1, ioaddr+PGSEL);
1354 dspcfg = readw(ioaddr+DSPCFG);
1355 writew(0, ioaddr+PGSEL);
1356 if (dspcfg != np->dspcfg) {
1357 if (!netif_queue_stopped(dev)) {
1358 spin_unlock_irq(&np->lock);
1359 if (netif_msg_hw(np))
1360 printk(KERN_NOTICE "%s: possible phy reset: "
1361 "re-initializing\n", dev->name);
1362 disable_irq(dev->irq);
1363 spin_lock_irq(&np->lock);
1364 natsemi_stop_rxtx(dev);
1367 init_registers(dev);
1368 spin_unlock_irq(&np->lock);
1369 enable_irq(dev->irq);
1373 spin_unlock_irq(&np->lock);
1376 /* init_registers() calls check_link() for the above case */
1378 spin_unlock_irq(&np->lock);
1381 disable_irq(dev->irq);
1384 enable_irq(dev->irq);
1386 writel(RxOn, dev->base_addr + ChipCmd);
1391 mod_timer(&np->timer, jiffies + next_tick);
1394 static void dump_ring(struct net_device *dev)
1396 struct netdev_private *np = dev->priv;
1398 if (netif_msg_pktdata(np)) {
1400 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
1401 for (i = 0; i < TX_RING_SIZE; i++) {
1402 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1403 i, np->tx_ring[i].next_desc,
1404 np->tx_ring[i].cmd_status,
1405 np->tx_ring[i].addr);
1407 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1408 for (i = 0; i < RX_RING_SIZE; i++) {
1409 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1410 i, np->rx_ring[i].next_desc,
1411 np->rx_ring[i].cmd_status,
1412 np->rx_ring[i].addr);
1417 static void tx_timeout(struct net_device *dev)
1419 struct netdev_private *np = dev->priv;
1420 long ioaddr = dev->base_addr;
1422 disable_irq(dev->irq);
1423 spin_lock_irq(&np->lock);
1424 if (!np->hands_off) {
1425 if (netif_msg_tx_err(np))
1427 "%s: Transmit timed out, status %#08x,"
1429 dev->name, readl(ioaddr + IntrStatus));
1434 init_registers(dev);
1437 "%s: tx_timeout while in hands_off state?\n",
1440 spin_unlock_irq(&np->lock);
1441 enable_irq(dev->irq);
1443 dev->trans_start = jiffies;
1444 np->stats.tx_errors++;
1445 netif_wake_queue(dev);
1448 static int alloc_ring(struct net_device *dev)
1450 struct netdev_private *np = dev->priv;
1451 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1452 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1456 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
1460 static void refill_rx(struct net_device *dev)
1462 struct netdev_private *np = dev->priv;
1464 /* Refill the Rx ring buffers. */
1465 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1466 struct sk_buff *skb;
1467 int entry = np->dirty_rx % RX_RING_SIZE;
1468 if (np->rx_skbuff[entry] == NULL) {
1469 skb = dev_alloc_skb(np->rx_buf_sz);
1470 np->rx_skbuff[entry] = skb;
1472 break; /* Better luck next round. */
1473 skb->dev = dev; /* Mark as being used by this device. */
1474 np->rx_dma[entry] = pci_map_single(np->pci_dev,
1475 skb->data, skb->len, PCI_DMA_FROMDEVICE);
1476 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1478 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
1480 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
1481 if (netif_msg_rx_err(np))
1482 printk(KERN_WARNING "%s: going OOM.\n", dev->name);
1487 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1488 static void init_ring(struct net_device *dev)
1490 struct netdev_private *np = dev->priv;
1494 np->dirty_tx = np->cur_tx = 0;
1495 for (i = 0; i < TX_RING_SIZE; i++) {
1496 np->tx_skbuff[i] = NULL;
1497 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1498 +sizeof(struct netdev_desc)
1499 *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
1500 np->tx_ring[i].cmd_status = 0;
1505 np->cur_rx = RX_RING_SIZE;
1506 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1508 np->rx_head_desc = &np->rx_ring[0];
1510 /* Please be carefull before changing this loop - at least gcc-2.95.1
1511 * miscompiles it otherwise.
1513 /* Initialize all Rx descriptors. */
1514 for (i = 0; i < RX_RING_SIZE; i++) {
1515 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1516 +sizeof(struct netdev_desc)
1517 *((i+1)%RX_RING_SIZE));
1518 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
1519 np->rx_skbuff[i] = NULL;
1525 static void drain_tx(struct net_device *dev)
1527 struct netdev_private *np = dev->priv;
1530 for (i = 0; i < TX_RING_SIZE; i++) {
1531 if (np->tx_skbuff[i]) {
1532 pci_unmap_single(np->pci_dev,
1533 np->rx_dma[i], np->rx_skbuff[i]->len,
1535 dev_kfree_skb(np->tx_skbuff[i]);
1536 np->stats.tx_dropped++;
1538 np->tx_skbuff[i] = NULL;
1542 static void drain_ring(struct net_device *dev)
1544 struct netdev_private *np = dev->priv;
1547 /* Free all the skbuffs in the Rx queue. */
1548 for (i = 0; i < RX_RING_SIZE; i++) {
1549 np->rx_ring[i].cmd_status = 0;
1550 np->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
1551 if (np->rx_skbuff[i]) {
1552 pci_unmap_single(np->pci_dev,
1553 np->rx_dma[i], np->rx_skbuff[i]->len,
1554 PCI_DMA_FROMDEVICE);
1555 dev_kfree_skb(np->rx_skbuff[i]);
1557 np->rx_skbuff[i] = NULL;
1562 static void free_ring(struct net_device *dev)
1564 struct netdev_private *np = dev->priv;
1565 pci_free_consistent(np->pci_dev,
1566 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1567 np->rx_ring, np->ring_dma);
1570 static void reinit_ring(struct net_device *dev)
1572 struct netdev_private *np = dev->priv;
1577 np->dirty_tx = np->cur_tx = 0;
1578 for (i=0;i<TX_RING_SIZE;i++)
1579 np->tx_ring[i].cmd_status = 0;
1583 np->cur_rx = RX_RING_SIZE;
1584 np->rx_head_desc = &np->rx_ring[0];
1585 /* Initialize all Rx descriptors. */
1586 for (i = 0; i < RX_RING_SIZE; i++)
1587 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
1592 static int start_tx(struct sk_buff *skb, struct net_device *dev)
1594 struct netdev_private *np = dev->priv;
1597 /* Note: Ordering is important here, set the field with the
1598 "ownership" bit last, and only then increment cur_tx. */
1600 /* Calculate the next Tx descriptor entry. */
1601 entry = np->cur_tx % TX_RING_SIZE;
1603 np->tx_skbuff[entry] = skb;
1604 np->tx_dma[entry] = pci_map_single(np->pci_dev,
1605 skb->data,skb->len, PCI_DMA_TODEVICE);
1607 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
1609 spin_lock_irq(&np->lock);
1611 if (!np->hands_off) {
1612 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
1613 /* StrongARM: Explicitly cache flush np->tx_ring and
1614 * skb->data,skb->len. */
1617 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
1618 netdev_tx_done(dev);
1619 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
1620 netif_stop_queue(dev);
1622 /* Wake the potentially-idle transmit channel. */
1623 writel(TxOn, dev->base_addr + ChipCmd);
1625 dev_kfree_skb_irq(skb);
1626 np->stats.tx_dropped++;
1628 spin_unlock_irq(&np->lock);
1630 dev->trans_start = jiffies;
1632 if (netif_msg_tx_queued(np)) {
1633 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
1634 dev->name, np->cur_tx, entry);
1639 static void netdev_tx_done(struct net_device *dev)
1641 struct netdev_private *np = dev->priv;
1643 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1644 int entry = np->dirty_tx % TX_RING_SIZE;
1645 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
1647 if (netif_msg_tx_done(np))
1649 "%s: tx frame #%d finished, status %#08x.\n",
1650 dev->name, np->dirty_tx,
1651 le32_to_cpu(np->tx_ring[entry].cmd_status));
1652 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
1653 np->stats.tx_packets++;
1654 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
1655 } else { /* Various Tx errors */
1657 le32_to_cpu(np->tx_ring[entry].cmd_status);
1658 if (tx_status & (DescTxAbort|DescTxExcColl))
1659 np->stats.tx_aborted_errors++;
1660 if (tx_status & DescTxFIFO)
1661 np->stats.tx_fifo_errors++;
1662 if (tx_status & DescTxCarrier)
1663 np->stats.tx_carrier_errors++;
1664 if (tx_status & DescTxOOWCol)
1665 np->stats.tx_window_errors++;
1666 np->stats.tx_errors++;
1668 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
1669 np->tx_skbuff[entry]->len,
1671 /* Free the original skb. */
1672 dev_kfree_skb_irq(np->tx_skbuff[entry]);
1673 np->tx_skbuff[entry] = NULL;
1675 if (netif_queue_stopped(dev)
1676 && np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
1677 /* The ring is no longer full, wake queue. */
1678 netif_wake_queue(dev);
1682 /* The interrupt handler does all of the Rx thread work and cleans up
1683 after the Tx thread. */
1684 static void intr_handler(int irq, void *dev_instance, struct pt_regs *rgs)
1686 struct net_device *dev = dev_instance;
1687 struct netdev_private *np = dev->priv;
1688 long ioaddr = dev->base_addr;
1689 int boguscnt = max_interrupt_work;
1694 /* Reading automatically acknowledges all int sources. */
1695 u32 intr_status = readl(ioaddr + IntrStatus);
1697 if (netif_msg_intr(np))
1699 "%s: Interrupt, status %#08x, mask %#08x.\n",
1700 dev->name, intr_status,
1701 readl(ioaddr + IntrMask));
1703 if (intr_status == 0)
1707 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
1708 IntrRxErr | IntrRxOverrun)) {
1713 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
1714 spin_lock(&np->lock);
1715 netdev_tx_done(dev);
1716 spin_unlock(&np->lock);
1719 /* Abnormal error summary/uncommon events handlers. */
1720 if (intr_status & IntrAbnormalSummary)
1721 netdev_error(dev, intr_status);
1723 if (--boguscnt < 0) {
1724 if (netif_msg_intr(np))
1726 "%s: Too much work at interrupt, "
1728 dev->name, intr_status);
1733 if (netif_msg_intr(np))
1734 printk(KERN_DEBUG "%s: exiting interrupt.\n", dev->name);
1737 /* This routine is logically part of the interrupt handler, but separated
1738 for clarity and better register allocation. */
1739 static void netdev_rx(struct net_device *dev)
1741 struct netdev_private *np = dev->priv;
1742 int entry = np->cur_rx % RX_RING_SIZE;
1743 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
1744 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
1746 /* If the driver owns the next entry it's a new packet. Send it up. */
1747 while (desc_status < 0) { /* e.g. & DescOwn */
1748 if (netif_msg_rx_status(np))
1750 " netdev_rx() entry %d status was %#08x.\n",
1751 entry, desc_status);
1754 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
1755 if (desc_status & DescMore) {
1756 if (netif_msg_rx_err(np))
1758 "%s: Oversized(?) Ethernet "
1759 "frame spanned multiple "
1760 "buffers, entry %#08x "
1761 "status %#08x.\n", dev->name,
1762 np->cur_rx, desc_status);
1763 np->stats.rx_length_errors++;
1765 /* There was an error. */
1766 np->stats.rx_errors++;
1767 if (desc_status & (DescRxAbort|DescRxOver))
1768 np->stats.rx_over_errors++;
1769 if (desc_status & (DescRxLong|DescRxRunt))
1770 np->stats.rx_length_errors++;
1771 if (desc_status & (DescRxInvalid|DescRxAlign))
1772 np->stats.rx_frame_errors++;
1773 if (desc_status & DescRxCRC)
1774 np->stats.rx_crc_errors++;
1777 struct sk_buff *skb;
1778 /* Omit CRC size. */
1779 int pkt_len = (desc_status & DescSizeMask) - 4;
1780 /* Check if the packet is long enough to accept
1781 * without copying to a minimally-sized skbuff. */
1782 if (pkt_len < rx_copybreak
1783 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1785 /* 16 byte align the IP header */
1786 skb_reserve(skb, 2);
1787 pci_dma_sync_single(np->pci_dev,
1789 np->rx_skbuff[entry]->len,
1790 PCI_DMA_FROMDEVICE);
1792 eth_copy_and_sum(skb,
1793 np->rx_skbuff[entry]->tail, pkt_len, 0);
1794 skb_put(skb, pkt_len);
1796 memcpy(skb_put(skb, pkt_len),
1797 np->rx_skbuff[entry]->tail, pkt_len);
1800 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
1801 np->rx_skbuff[entry]->len,
1802 PCI_DMA_FROMDEVICE);
1803 skb_put(skb = np->rx_skbuff[entry], pkt_len);
1804 np->rx_skbuff[entry] = NULL;
1806 skb->protocol = eth_type_trans(skb, dev);
1808 dev->last_rx = jiffies;
1809 np->stats.rx_packets++;
1810 np->stats.rx_bytes += pkt_len;
1812 entry = (++np->cur_rx) % RX_RING_SIZE;
1813 np->rx_head_desc = &np->rx_ring[entry];
1814 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
1818 /* Restart Rx engine if stopped. */
1820 mod_timer(&np->timer, jiffies + 1);
1822 writel(RxOn, dev->base_addr + ChipCmd);
1825 static void netdev_error(struct net_device *dev, int intr_status)
1827 struct netdev_private *np = dev->priv;
1828 long ioaddr = dev->base_addr;
1830 spin_lock(&np->lock);
1831 if (intr_status & LinkChange) {
1832 u16 adv = mdio_read(dev, 1, MII_ADVERTISE);
1833 u16 lpa = mdio_read(dev, 1, MII_LPA);
1834 if (mdio_read(dev, 1, MII_BMCR) & BMCR_ANENABLE
1835 && netif_msg_link(np)) {
1837 "%s: Autonegotiation advertising"
1838 " %#04x partner %#04x.\n", dev->name,
1842 /* read MII int status to clear the flag */
1843 readw(ioaddr + MIntrStatus);
1846 if (intr_status & StatsMax) {
1849 if (intr_status & IntrTxUnderrun) {
1850 if ((np->tx_config & TxDrthMask) < 62)
1852 if (netif_msg_tx_err(np))
1854 "%s: increased Tx threshold, txcfg %#08x.\n",
1855 dev->name, np->tx_config);
1856 writel(np->tx_config, ioaddr + TxConfig);
1858 if (intr_status & WOLPkt && netif_msg_wol(np)) {
1859 int wol_status = readl(ioaddr + WOLCmd);
1860 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
1861 dev->name, wol_status);
1863 if (intr_status & RxStatusFIFOOver) {
1864 if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
1865 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
1868 np->stats.rx_fifo_errors++;
1870 /* Hmmmmm, it's not clear how to recover from PCI faults. */
1871 if (intr_status & IntrPCIErr) {
1872 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
1873 intr_status & IntrPCIErr);
1874 np->stats.tx_fifo_errors++;
1875 np->stats.rx_fifo_errors++;
1877 spin_unlock(&np->lock);
1880 static void __get_stats(struct net_device *dev)
1882 long ioaddr = dev->base_addr;
1883 struct netdev_private *np = dev->priv;
1885 /* The chip only need report frame silently dropped. */
1886 np->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
1887 np->stats.rx_missed_errors += readl(ioaddr + RxMissed);
1890 static struct net_device_stats *get_stats(struct net_device *dev)
1892 struct netdev_private *np = dev->priv;
1894 /* The chip only need report frame silently dropped. */
1895 spin_lock_irq(&np->lock);
1896 if (netif_running(dev) && !np->hands_off)
1898 spin_unlock_irq(&np->lock);
1904 * dp83815_crc - computer CRC for hash table entries
1906 * Note - this is, for some reason, *not* the same function
1907 * as ether_crc_le() or ether_crc(), though it uses the
1908 * same big-endian polynomial.
1910 #define DP_POLYNOMIAL 0x04C11DB7
1911 static unsigned dp83815_crc(int length, unsigned char *data)
1919 for (byte=0; byte<length; byte++) {
1921 for (bit=0; bit<8; bit++) {
1924 if (msb ^ (cur_byte & 1)) {
1925 crc ^= DP_POLYNOMIAL;
1937 void set_bit_le(int offset, unsigned char * data)
1939 data[offset >> 3] |= (1 << (offset & 0x07));
1941 #define HASH_TABLE 0x200
1942 static void __set_rx_mode(struct net_device *dev)
1944 long ioaddr = dev->base_addr;
1945 struct netdev_private *np = dev->priv;
1946 u8 mc_filter[64]; /* Multicast hash filter */
1949 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1950 /* Unconditionally log net taps. */
1951 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
1953 rx_mode = RxFilterEnable | AcceptBroadcast
1954 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
1955 } else if ((dev->mc_count > multicast_filter_limit)
1956 || (dev->flags & IFF_ALLMULTI)) {
1957 rx_mode = RxFilterEnable | AcceptBroadcast
1958 | AcceptAllMulticast | AcceptMyPhys;
1960 struct dev_mc_list *mclist;
1962 memset(mc_filter, 0, sizeof(mc_filter));
1963 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1964 i++, mclist = mclist->next) {
1966 dp83815_crc(ETH_ALEN, mclist->dmi_addr) & 0x1ff,
1969 rx_mode = RxFilterEnable | AcceptBroadcast
1970 | AcceptMulticast | AcceptMyPhys;
1971 for (i = 0; i < 64; i += 2) {
1972 writew(HASH_TABLE + i, ioaddr + RxFilterAddr);
1973 writew((mc_filter[i+1]<<8) + mc_filter[i],
1974 ioaddr + RxFilterData);
1977 writel(rx_mode, ioaddr + RxFilterAddr);
1978 np->cur_rx_mode = rx_mode;
1981 static void set_rx_mode(struct net_device *dev)
1983 struct netdev_private *np = dev->priv;
1984 spin_lock_irq(&np->lock);
1987 spin_unlock_irq(&np->lock);
1990 static int netdev_ethtool_ioctl(struct net_device *dev, void *useraddr)
1992 struct netdev_private *np = dev->priv;
1995 if (get_user(cmd, (u32 *)useraddr))
1999 /* get driver info */
2000 case ETHTOOL_GDRVINFO: {
2001 struct ethtool_drvinfo info = {ETHTOOL_GDRVINFO};
2002 strncpy(info.driver, DRV_NAME, ETHTOOL_BUSINFO_LEN);
2003 strncpy(info.version, DRV_VERSION, ETHTOOL_BUSINFO_LEN);
2004 info.fw_version[0] = '\0';
2005 strncpy(info.bus_info, np->pci_dev->slot_name,
2006 ETHTOOL_BUSINFO_LEN);
2007 info.eedump_len = NATSEMI_EEPROM_SIZE;
2008 info.regdump_len = NATSEMI_REGS_SIZE;
2009 if (copy_to_user(useraddr, &info, sizeof(info)))
2014 case ETHTOOL_GSET: {
2015 struct ethtool_cmd ecmd = { ETHTOOL_GSET };
2016 spin_lock_irq(&np->lock);
2017 netdev_get_ecmd(dev, &ecmd);
2018 spin_unlock_irq(&np->lock);
2019 if (copy_to_user(useraddr, &ecmd, sizeof(ecmd)))
2024 case ETHTOOL_SSET: {
2025 struct ethtool_cmd ecmd;
2027 if (copy_from_user(&ecmd, useraddr, sizeof(ecmd)))
2029 spin_lock_irq(&np->lock);
2030 r = netdev_set_ecmd(dev, &ecmd);
2031 spin_unlock_irq(&np->lock);
2034 /* get wake-on-lan */
2035 case ETHTOOL_GWOL: {
2036 struct ethtool_wolinfo wol = {ETHTOOL_GWOL};
2037 spin_lock_irq(&np->lock);
2038 netdev_get_wol(dev, &wol.supported, &wol.wolopts);
2039 netdev_get_sopass(dev, wol.sopass);
2040 spin_unlock_irq(&np->lock);
2041 if (copy_to_user(useraddr, &wol, sizeof(wol)))
2045 /* set wake-on-lan */
2046 case ETHTOOL_SWOL: {
2047 struct ethtool_wolinfo wol;
2049 if (copy_from_user(&wol, useraddr, sizeof(wol)))
2051 spin_lock_irq(&np->lock);
2052 netdev_set_wol(dev, wol.wolopts);
2053 r = netdev_set_sopass(dev, wol.sopass);
2054 spin_unlock_irq(&np->lock);
2058 case ETHTOOL_GREGS: {
2059 struct ethtool_regs regs;
2060 u8 regbuf[NATSEMI_REGS_SIZE];
2063 if (copy_from_user(®s, useraddr, sizeof(regs)))
2066 if (regs.len > NATSEMI_REGS_SIZE) {
2067 regs.len = NATSEMI_REGS_SIZE;
2069 regs.version = NATSEMI_REGS_VER;
2070 if (copy_to_user(useraddr, ®s, sizeof(regs)))
2073 useraddr += offsetof(struct ethtool_regs, data);
2075 spin_lock_irq(&np->lock);
2076 r = netdev_get_regs(dev, regbuf);
2077 spin_unlock_irq(&np->lock);
2081 if (copy_to_user(useraddr, regbuf, regs.len))
2085 /* get message-level */
2086 case ETHTOOL_GMSGLVL: {
2087 struct ethtool_value edata = {ETHTOOL_GMSGLVL};
2088 edata.data = np->msg_enable;
2089 if (copy_to_user(useraddr, &edata, sizeof(edata)))
2093 /* set message-level */
2094 case ETHTOOL_SMSGLVL: {
2095 struct ethtool_value edata;
2096 if (copy_from_user(&edata, useraddr, sizeof(edata)))
2098 np->msg_enable = edata.data;
2101 /* restart autonegotiation */
2102 case ETHTOOL_NWAY_RST: {
2105 /* if autoneg is off, it's an error */
2106 tmp = mdio_read(dev, 1, MII_BMCR);
2107 if (tmp & BMCR_ANENABLE) {
2108 tmp |= (BMCR_ANRESTART);
2109 mdio_write(dev, 1, MII_BMCR, tmp);
2114 /* get link status */
2115 case ETHTOOL_GLINK: {
2116 struct ethtool_value edata = {ETHTOOL_GLINK};
2117 /* LSTATUS is latched low until a read - so read twice */
2118 mdio_read(dev, 1, MII_BMSR);
2119 edata.data = (mdio_read(dev, 1, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
2120 if (copy_to_user(useraddr, &edata, sizeof(edata)))
2125 case ETHTOOL_GEEPROM: {
2126 struct ethtool_eeprom eeprom;
2127 u8 eebuf[NATSEMI_EEPROM_SIZE];
2130 if (copy_from_user(&eeprom, useraddr, sizeof(eeprom)))
2133 if (eeprom.offset > eeprom.offset+eeprom.len)
2136 if ((eeprom.offset+eeprom.len) > NATSEMI_EEPROM_SIZE) {
2137 eeprom.len = NATSEMI_EEPROM_SIZE-eeprom.offset;
2139 eeprom.magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
2140 if (copy_to_user(useraddr, &eeprom, sizeof(eeprom)))
2143 useraddr += offsetof(struct ethtool_eeprom, data);
2145 spin_lock_irq(&np->lock);
2146 r = netdev_get_eeprom(dev, eebuf);
2147 spin_unlock_irq(&np->lock);
2151 if (copy_to_user(useraddr, eebuf+eeprom.offset, eeprom.len))
2161 static int netdev_set_wol(struct net_device *dev, u32 newval)
2163 struct netdev_private *np = dev->priv;
2164 u32 data = readl(dev->base_addr + WOLCmd) & ~WakeOptsSummary;
2166 /* translate to bitmasks this chip understands */
2167 if (newval & WAKE_PHY)
2169 if (newval & WAKE_UCAST)
2170 data |= WakeUnicast;
2171 if (newval & WAKE_MCAST)
2172 data |= WakeMulticast;
2173 if (newval & WAKE_BCAST)
2174 data |= WakeBroadcast;
2175 if (newval & WAKE_ARP)
2177 if (newval & WAKE_MAGIC)
2179 if (np->srr >= SRR_DP83815_D) {
2180 if (newval & WAKE_MAGICSECURE) {
2181 data |= WakeMagicSecure;
2185 writel(data, dev->base_addr + WOLCmd);
2190 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
2192 struct netdev_private *np = dev->priv;
2193 u32 regval = readl(dev->base_addr + WOLCmd);
2195 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
2196 | WAKE_ARP | WAKE_MAGIC);
2198 if (np->srr >= SRR_DP83815_D) {
2199 /* SOPASS works on revD and higher */
2200 *supported |= WAKE_MAGICSECURE;
2204 /* translate from chip bitmasks */
2205 if (regval & WakePhy)
2207 if (regval & WakeUnicast)
2209 if (regval & WakeMulticast)
2211 if (regval & WakeBroadcast)
2213 if (regval & WakeArp)
2215 if (regval & WakeMagic)
2217 if (regval & WakeMagicSecure) {
2218 /* this can be on in revC, but it's broken */
2219 *cur |= WAKE_MAGICSECURE;
2225 static int netdev_set_sopass(struct net_device *dev, u8 *newval)
2227 struct netdev_private *np = dev->priv;
2228 u16 *sval = (u16 *)newval;
2231 if (np->srr < SRR_DP83815_D) {
2235 /* enable writing to these registers by disabling the RX filter */
2236 addr = readl(dev->base_addr + RxFilterAddr) & ~RFCRAddressMask;
2237 addr &= ~RxFilterEnable;
2238 writel(addr, dev->base_addr + RxFilterAddr);
2240 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
2241 writel(addr | 0xa, dev->base_addr + RxFilterAddr);
2242 writew(sval[0], dev->base_addr + RxFilterData);
2244 writel(addr | 0xc, dev->base_addr + RxFilterAddr);
2245 writew(sval[1], dev->base_addr + RxFilterData);
2247 writel(addr | 0xe, dev->base_addr + RxFilterAddr);
2248 writew(sval[2], dev->base_addr + RxFilterData);
2250 /* re-enable the RX filter */
2251 writel(addr | RxFilterEnable, dev->base_addr + RxFilterAddr);
2256 static int netdev_get_sopass(struct net_device *dev, u8 *data)
2258 struct netdev_private *np = dev->priv;
2259 u16 *sval = (u16 *)data;
2262 if (np->srr < SRR_DP83815_D) {
2263 sval[0] = sval[1] = sval[2] = 0;
2267 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
2268 addr = readl(dev->base_addr + RxFilterAddr) & ~RFCRAddressMask;
2270 writel(addr | 0xa, dev->base_addr + RxFilterAddr);
2271 sval[0] = readw(dev->base_addr + RxFilterData);
2273 writel(addr | 0xc, dev->base_addr + RxFilterAddr);
2274 sval[1] = readw(dev->base_addr + RxFilterData);
2276 writel(addr | 0xe, dev->base_addr + RxFilterAddr);
2277 sval[2] = readw(dev->base_addr + RxFilterData);
2279 writel(addr, dev->base_addr + RxFilterAddr);
2284 static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2289 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2290 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2291 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
2293 /* only supports twisted-pair or MII */
2294 tmp = readl(dev->base_addr + ChipConfig);
2295 if (tmp & CfgExtPhy)
2296 ecmd->port = PORT_MII;
2298 ecmd->port = PORT_TP;
2300 /* only supports internal transceiver */
2301 ecmd->transceiver = XCVR_INTERNAL;
2303 /* not sure what this is for */
2304 ecmd->phy_address = readw(dev->base_addr + PhyCtrl) & PhyAddrMask;
2306 ecmd->advertising = ADVERTISED_TP | ADVERTISED_MII;
2307 tmp = mdio_read(dev, 1, MII_ADVERTISE);
2308 if (tmp & ADVERTISE_10HALF)
2309 ecmd->advertising |= ADVERTISED_10baseT_Half;
2310 if (tmp & ADVERTISE_10FULL)
2311 ecmd->advertising |= ADVERTISED_10baseT_Full;
2312 if (tmp & ADVERTISE_100HALF)
2313 ecmd->advertising |= ADVERTISED_100baseT_Half;
2314 if (tmp & ADVERTISE_100FULL)
2315 ecmd->advertising |= ADVERTISED_100baseT_Full;
2317 tmp = mdio_read(dev, 1, MII_BMCR);
2318 if (tmp & BMCR_ANENABLE) {
2319 ecmd->advertising |= ADVERTISED_Autoneg;
2320 ecmd->autoneg = AUTONEG_ENABLE;
2322 ecmd->autoneg = AUTONEG_DISABLE;
2325 tmp = readl(dev->base_addr + ChipConfig);
2326 if (tmp & CfgSpeed100) {
2327 ecmd->speed = SPEED_100;
2329 ecmd->speed = SPEED_10;
2332 if (tmp & CfgFullDuplex) {
2333 ecmd->duplex = DUPLEX_FULL;
2335 ecmd->duplex = DUPLEX_HALF;
2338 /* ignore maxtxpkt, maxrxpkt for now */
2343 static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2345 struct netdev_private *np = dev->priv;
2348 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2350 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2352 if (ecmd->port != PORT_TP && ecmd->port != PORT_MII)
2354 if (ecmd->transceiver != XCVR_INTERNAL)
2356 if (ecmd->autoneg != AUTONEG_DISABLE && ecmd->autoneg != AUTONEG_ENABLE)
2358 /* ignore phy_address, maxtxpkt, maxrxpkt for now */
2360 /* WHEW! now lets bang some bits */
2362 tmp = mdio_read(dev, 1, MII_BMCR);
2363 if (ecmd->autoneg == AUTONEG_ENABLE) {
2364 /* turn on autonegotiation */
2365 tmp |= BMCR_ANENABLE;
2366 np->advertising = mdio_read(dev, 1, MII_ADVERTISE);
2368 /* turn off auto negotiation, set speed and duplexity */
2369 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
2370 if (ecmd->speed == SPEED_100)
2371 tmp |= BMCR_SPEED100;
2372 if (ecmd->duplex == DUPLEX_FULL)
2373 tmp |= BMCR_FULLDPLX;
2375 np->full_duplex = 0;
2377 mdio_write(dev, 1, MII_BMCR, tmp);
2381 static int netdev_get_regs(struct net_device *dev, u8 *buf)
2386 u32 *rbuf = (u32 *)buf;
2388 /* read all of page 0 of registers */
2389 for (i = 0; i < NATSEMI_PG0_NREGS; i++) {
2390 rbuf[i] = readl(dev->base_addr + i*4);
2393 /* read only the 'magic' registers from page 1 */
2394 writew(1, dev->base_addr + PGSEL);
2395 rbuf[i++] = readw(dev->base_addr + PMDCSR);
2396 rbuf[i++] = readw(dev->base_addr + TSTDAT);
2397 rbuf[i++] = readw(dev->base_addr + DSPCFG);
2398 rbuf[i++] = readw(dev->base_addr + SDCFG);
2399 writew(0, dev->base_addr + PGSEL);
2401 /* read RFCR indexed registers */
2402 rfcr = readl(dev->base_addr + RxFilterAddr);
2403 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
2404 writel(j*2, dev->base_addr + RxFilterAddr);
2405 rbuf[i++] = readw(dev->base_addr + RxFilterData);
2407 writel(rfcr, dev->base_addr + RxFilterAddr);
2409 /* the interrupt status is clear-on-read - see if we missed any */
2410 if (rbuf[4] & rbuf[5]) {
2412 "%s: shoot, we dropped an interrupt (%#08x)\n",
2413 dev->name, rbuf[4] & rbuf[5]);
2419 #define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
2420 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
2421 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
2422 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
2423 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
2424 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
2425 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
2426 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
2428 static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
2431 u16 *ebuf = (u16 *)buf;
2433 /* eeprom_read reads 16 bits, and indexes by 16 bits */
2434 for (i = 0; i < NATSEMI_EEPROM_SIZE/2; i++) {
2435 ebuf[i] = eeprom_read(dev->base_addr, i);
2436 /* The EEPROM itself stores data bit-swapped, but eeprom_read
2437 * reads it back "sanely". So we swap it back here in order to
2438 * present it to userland as it is stored. */
2439 ebuf[i] = SWAP_BITS(ebuf[i]);
2444 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2446 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&rq->ifr_data;
2450 return netdev_ethtool_ioctl(dev, (void *) rq->ifr_data);
2451 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2452 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
2456 case SIOCGMIIREG: /* Read MII PHY register. */
2457 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
2458 data->val_out = mdio_read(dev, data->phy_id & 0x1f,
2459 data->reg_num & 0x1f);
2462 case SIOCSMIIREG: /* Write MII PHY register. */
2463 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
2464 if (!capable(CAP_NET_ADMIN))
2466 mdio_write(dev, data->phy_id & 0x1f, data->reg_num & 0x1f,
2474 static void enable_wol_mode(struct net_device *dev, int enable_intr)
2476 long ioaddr = dev->base_addr;
2477 struct netdev_private *np = dev->priv;
2479 if (netif_msg_wol(np))
2480 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
2483 /* For WOL we must restart the rx process in silent mode.
2484 * Write NULL to the RxRingPtr. Only possible if
2485 * rx process is stopped
2487 writel(0, ioaddr + RxRingPtr);
2489 /* read WoL status to clear */
2490 readl(ioaddr + WOLCmd);
2492 /* PME on, clear status */
2493 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
2495 /* and restart the rx process */
2496 writel(RxOn, ioaddr + ChipCmd);
2499 /* enable the WOL interrupt.
2500 * Could be used to send a netlink message.
2502 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
2503 writel(1, ioaddr + IntrEnable);
2507 static int netdev_close(struct net_device *dev)
2509 long ioaddr = dev->base_addr;
2510 struct netdev_private *np = dev->priv;
2512 if (netif_msg_ifdown(np))
2514 "%s: Shutting down ethercard, status was %#04x.\n",
2515 dev->name, (int)readl(ioaddr + ChipCmd));
2516 if (netif_msg_pktdata(np))
2518 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
2519 dev->name, np->cur_tx, np->dirty_tx,
2520 np->cur_rx, np->dirty_rx);
2523 * FIXME: what if someone tries to close a device
2524 * that is suspended?
2525 * Should we reenable the nic to switch to
2526 * the final WOL settings?
2529 del_timer_sync(&np->timer);
2530 disable_irq(dev->irq);
2531 spin_lock_irq(&np->lock);
2532 /* Disable interrupts, and flush posted writes */
2533 writel(0, ioaddr + IntrEnable);
2534 readl(ioaddr + IntrEnable);
2536 spin_unlock_irq(&np->lock);
2537 enable_irq(dev->irq);
2539 free_irq(dev->irq, dev);
2541 /* Interrupt disabled, interrupt handler released,
2542 * queue stopped, timer deleted, rtnl_lock held
2543 * All async codepaths that access the driver are disabled.
2545 spin_lock_irq(&np->lock);
2547 readl(ioaddr + IntrMask);
2548 readw(ioaddr + MIntrStatus);
2551 writel(StatsFreeze, ioaddr + StatsCtrl);
2553 /* Stop the chip's Tx and Rx processes. */
2554 natsemi_stop_rxtx(dev);
2557 spin_unlock_irq(&np->lock);
2559 /* clear the carrier last - an interrupt could reenable it otherwise */
2560 netif_carrier_off(dev);
2561 netif_stop_queue(dev);
2568 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
2570 /* restart the NIC in WOL mode.
2571 * The nic must be stopped for this.
2573 enable_wol_mode(dev, 0);
2575 /* Restore PME enable bit unmolested */
2576 writel(np->SavedClkRun, ioaddr + ClkRun);
2583 static void __devexit natsemi_remove1 (struct pci_dev *pdev)
2585 struct net_device *dev = pci_get_drvdata(pdev);
2587 unregister_netdev (dev);
2588 pci_release_regions (pdev);
2589 iounmap ((char *) dev->base_addr);
2591 pci_set_drvdata(pdev, NULL);
2597 * The ns83815 chip doesn't have explicit RxStop bits.
2598 * Kicking the Rx or Tx process for a new packet reenables the Rx process
2599 * of the nic, thus this function must be very careful:
2601 * suspend/resume synchronization:
2603 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler,
2604 * start_tx, tx_timeout
2606 * No function accesses the hardware without checking np->hands_off.
2607 * the check occurs under spin_lock_irq(&np->lock);
2609 * * netdev_ioctl: noncritical access.
2610 * * netdev_open: cannot happen due to the device_detach
2611 * * netdev_close: doesn't hurt.
2612 * * netdev_timer: timer stopped by natsemi_suspend.
2613 * * intr_handler: doesn't acquire the spinlock. suspend calls
2614 * disable_irq() to enforce synchronization.
2616 * Interrupts must be disabled, otherwise hands_off can cause irq storms.
2619 static int natsemi_suspend (struct pci_dev *pdev, u32 state)
2621 struct net_device *dev = pci_get_drvdata (pdev);
2622 struct netdev_private *np = dev->priv;
2623 long ioaddr = dev->base_addr;
2626 if (netif_running (dev)) {
2627 del_timer_sync(&np->timer);
2629 disable_irq(dev->irq);
2630 spin_lock_irq(&np->lock);
2632 writel(0, ioaddr + IntrEnable);
2634 natsemi_stop_rxtx(dev);
2635 netif_stop_queue(dev);
2637 spin_unlock_irq(&np->lock);
2638 enable_irq(dev->irq);
2640 /* Update the error counts. */
2643 /* pci_power_off(pdev, -1); */
2646 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
2647 /* Restore PME enable bit */
2649 /* restart the NIC in WOL mode.
2650 * The nic must be stopped for this.
2651 * FIXME: use the WOL interupt
2653 enable_wol_mode(dev, 0);
2655 /* Restore PME enable bit unmolested */
2656 writel(np->SavedClkRun, ioaddr + ClkRun);
2660 netif_device_detach(dev);
2666 static int natsemi_resume (struct pci_dev *pdev)
2668 struct net_device *dev = pci_get_drvdata (pdev);
2669 struct netdev_private *np = dev->priv;
2672 if (netif_device_present(dev))
2674 if (netif_running(dev)) {
2675 BUG_ON(!np->hands_off);
2676 pci_enable_device(pdev);
2677 /* pci_power_on(pdev); */
2681 disable_irq(dev->irq);
2682 spin_lock_irq(&np->lock);
2684 init_registers(dev);
2685 netif_device_attach(dev);
2686 spin_unlock_irq(&np->lock);
2687 enable_irq(dev->irq);
2689 mod_timer(&np->timer, jiffies + 1*HZ);
2691 netif_device_attach(dev);
2697 #endif /* CONFIG_PM */
2699 static struct pci_driver natsemi_driver = {
2701 .id_table = natsemi_pci_tbl,
2702 .probe = natsemi_probe1,
2703 .remove = __devexit_p(natsemi_remove1),
2705 .suspend = natsemi_suspend,
2706 .resume = natsemi_resume,
2710 static int __init natsemi_init_mod (void)
2712 /* when a module, this is printed whether or not devices are found in probe */
2717 return pci_module_init (&natsemi_driver);
2720 static void __exit natsemi_exit_mod (void)
2722 pci_unregister_driver (&natsemi_driver);
2725 module_init(natsemi_init_mod);
2726 module_exit(natsemi_exit_mod);